1 /***************************************************************************\
3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
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36 |* those rights set forth herein. *|
38 \***************************************************************************/
39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.8tsi Exp $ */
41 #ifndef __NV_LOCAL_H__
42 #define __NV_LOCAL_H__
45 * This file includes any environment or machine specific values to access the
46 * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
47 * can stay generic in nature.
50 #include "xf86_OSproc.h"
53 * HW access macros. These assume memory-mapped I/O, and not normal I/O space.
55 #define NV_WR08(p,i,d) MMIO_OUT8((pointer)(p), (i), (d))
56 #define NV_RD08(p,i) MMIO_IN8((pointer)(p), (i))
57 #define NV_WR16(p,i,d) MMIO_OUT16((pointer)(p), (i), (d))
58 #define NV_RD16(p,i) MMIO_IN16((pointer)(p), (i))
59 #define NV_WR32(p,i,d) MMIO_OUT32((pointer)(p), (i), (d))
60 #define NV_RD32(p,i) MMIO_IN32((pointer)(p), (i))
62 /* VGA I/O is now always done through MMIO */
63 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
64 #define VGA_RD08(p,i) NV_RD08(p,i)
67 #define _NV_FENCE() outb(0x3D0, 0);
69 #define _NV_FENCE() mem_barrier();
73 #define READ_GET(pNv) (((pNv)->FIFO[0x0011] - pNv->fifo.put_base) >> 2)
75 #define WRITE_PUT(pNv, data) { \
76 volatile CARD8 scratch; \
78 scratch = ((char*)(pNv)->FB->map)[0]; \
79 (pNv)->FIFO[0x0010] = ((data) << 2) + pNv->fifo.put_base; \
80 xf86DrvMsg(0, X_INFO, "WRITE_PUT: 0x%08x\n", ((data) << 2) + pNv->fifo.put_base); \
84 #define WRITE_PUT(pNv, data) { \
85 volatile CARD8 scratch; \
87 scratch = ((char*)(pNv)->FB->map)[0]; \
88 (pNv)->FIFO[0x0010] = ((data) << 2) + pNv->fifo.put_base; \
94 static inline int log2i(int i)
102 if (i & 0x0000ff00) {
106 if (i & 0x000000f0) {
110 if (i & 0x0000000c) {
114 if (i & 0x00000002) {
122 #endif /* __NV_LOCAL_H__ */