2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include "nv_include.h"
28 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
29 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
30 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
31 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
32 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
33 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
34 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
35 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
37 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
39 ScrnInfoPtr pScrn = crtc->scrn;
40 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
41 NVPtr pNv = NVPTR(pScrn);
43 return NVReadCRTC(pNv, nv_crtc->head, reg);
46 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
48 ScrnInfoPtr pScrn = crtc->scrn;
49 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
50 NVPtr pNv = NVPTR(pScrn);
52 NVWriteCRTC(pNv, nv_crtc->head, reg, val);
55 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
57 ScrnInfoPtr pScrn = crtc->scrn;
58 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
59 NVPtr pNv = NVPTR(pScrn);
61 return NVReadRAMDAC(pNv, nv_crtc->head, reg);
64 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
66 ScrnInfoPtr pScrn = crtc->scrn;
67 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
68 NVPtr pNv = NVPTR(pScrn);
70 NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
73 void NVCrtcLockUnlock(xf86CrtcPtr crtc, bool lock)
75 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
76 NVPtr pNv = NVPTR(crtc->scrn);
78 NVLockVgaCrtc(pNv, nv_crtc->head, lock);
81 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
82 /* They are only valid for NV4x, appearantly reordered for NV5x */
83 /* gpu pll: 0x4000 + 0x4004
84 * unknown pll: 0x4008 + 0x400c
85 * vpll1: 0x4010 + 0x4014
86 * vpll2: 0x4018 + 0x401c
87 * unknown pll: 0x4020 + 0x4024
88 * unknown pll: 0x4038 + 0x403c
89 * Some of the unknown's are probably memory pll's.
90 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
91 * 1 and 2 refer to the registers of each pair. There is only one post divider.
92 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
93 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
94 * bit8: A switch that turns of the second divider and multiplier off.
95 * bit12: Also a switch, i haven't seen it yet.
97 * but 28-31: Something related to the mode that is used (see bit8).
98 * 2) bit0-7: m-divider (a)
99 * bit8-15: n-multiplier (a)
100 * bit16-23: m-divider (b)
101 * bit24-31: n-multiplier (b)
104 /* Modifying the gpu pll for example requires:
105 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
106 * This is not needed for the vpll's which have their own bits.
109 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
111 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
112 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
113 NVPtr pNv = NVPTR(crtc->scrn);
116 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
117 if (pNv->twoStagePLL)
118 regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
120 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
121 if (pNv->twoStagePLL)
122 regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
125 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
126 state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
127 if (pNv->Architecture == NV_ARCH_40)
128 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
131 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
133 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
134 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
135 ScrnInfoPtr pScrn = crtc->scrn;
136 NVPtr pNv = NVPTR(pScrn);
137 uint32_t savedc040 = 0;
139 /* This sequence is important, the NV28 is very sensitive in this area. */
140 /* Keep pllsel last and sel_clk first. */
142 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
144 if (pNv->Architecture == NV_ARCH_40) {
145 savedc040 = nvReadMC(pNv, 0xc040);
147 /* for vpll1 change bits 16 and 17 are disabled */
148 /* for vpll2 change bits 18 and 19 are disabled */
149 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
153 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
154 if (pNv->twoStagePLL)
155 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
157 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
158 if (pNv->twoStagePLL)
159 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
162 if (pNv->Architecture == NV_ARCH_40) {
163 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
165 /* We need to wait a while */
167 nvWriteMC(pNv, 0xc040, savedc040);
170 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
171 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
174 static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
176 NVPtr pNv = NVPTR(crtc->scrn);
177 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
178 uint32_t cursor_start;
179 uint8_t *CRTC = pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC;
181 if (pNv->Architecture == NV_ARCH_04)
182 cursor_start = 0x5E00 << 2;
184 cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
186 CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
187 if (pNv->Architecture != NV_ARCH_04)
188 CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
189 CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
190 if (crtc->mode.Flags & V_DBLSCAN)
191 CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
192 CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
194 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
195 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
196 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
197 if (pNv->Architecture == NV_ARCH_40)
198 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
201 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
203 ScrnInfoPtr pScrn = crtc->scrn;
204 NVPtr pNv = NVPTR(pScrn);
205 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
206 RIVA_HW_STATE *state = &pNv->ModeReg;
207 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
208 struct pll_lims pll_lim;
209 int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
210 uint32_t g70_pll_special_bits = 0;
211 bool nv4x_single_stage_pll_mode = false;
212 uint8_t arbitration0;
213 uint16_t arbitration1;
215 if (get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
218 if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
219 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
220 nv4x_single_stage_pll_mode = true;
221 /* Turn the second set of divider and multiplier off */
222 /* Bogus data, the same nvidia uses */
224 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
226 VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
228 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
230 /* Are these all the (relevant) G70 cards? */
231 if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
232 /* This is a big guess, but should be reasonable until we can narrow it down. */
233 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
234 if (nv4x_single_stage_pll_mode)
235 g70_pll_special_bits = 0x1;
237 g70_pll_special_bits = 0x3;
240 if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
241 /* See nvregisters.xml for details. */
242 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
244 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
245 regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
247 if (nv4x_single_stage_pll_mode) {
248 if (nv_crtc->head == 0)
249 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
251 state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
253 if (nv_crtc->head == 0)
254 state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
256 state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
259 /* The NV40 seems to have more similarities to NV3x than other NV4x */
260 if (pNv->NVArch < 0x41)
261 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
262 NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
263 /* The blob uses this always, so let's do the same */
264 if (pNv->Architecture == NV_ARCH_40)
265 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
267 if (nv_crtc->head == 1) {
268 if (!nv4x_single_stage_pll_mode)
269 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
271 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
272 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
274 if (!nv4x_single_stage_pll_mode)
275 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
277 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
278 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
281 if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
282 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
284 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
286 if (pNv->Architecture < NV_ARCH_30)
287 nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);
288 else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
289 (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
291 arbitration1 = 0x0480;
293 nv30UpdateArbitrationSettings(&arbitration0, &arbitration1);
295 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arbitration0;
296 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arbitration1 & 0xff;
297 if (pNv->Architecture >= NV_ARCH_30)
298 regp->CRTC[NV_CIO_CRE_47] = arbitration1 >> 8;
300 nv_crtc_cursor_set(crtc);
304 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
306 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
307 ScrnInfoPtr pScrn = crtc->scrn;
308 NVPtr pNv = NVPTR(pScrn);
309 unsigned char seq1 = 0, crtc17 = 0;
310 unsigned char crtc1A;
312 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting dpms mode %d on CRTC %d\n", mode, nv_crtc->head);
314 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
317 nv_crtc->last_dpms = mode;
320 NVSetOwner(pNv, nv_crtc->head);
322 crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
324 case DPMSModeStandby:
325 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
330 case DPMSModeSuspend:
331 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
337 /* Screen: Off; HSync: Off, VSync: Off */
344 /* Screen: On; HSync: On, VSync: On */
350 NVVgaSeqReset(pNv, nv_crtc->head, true);
351 /* Each head has it's own sequencer, so we can turn it off when we want */
352 seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
353 NVWriteVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX, seq1);
354 crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80);
356 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17);
357 NVVgaSeqReset(pNv, nv_crtc->head, false);
359 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
363 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
364 DisplayModePtr adjusted_mode)
370 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
372 ScrnInfoPtr pScrn = crtc->scrn;
373 NVPtr pNv = NVPTR(pScrn);
374 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
375 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
377 /* Calculate our timings */
378 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
379 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
380 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
381 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
382 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
383 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
384 int vertDisplay = mode->CrtcVDisplay - 1;
385 int vertStart = mode->CrtcVSyncStart - 1;
386 int vertEnd = mode->CrtcVSyncEnd - 1;
387 int vertTotal = mode->CrtcVTotal - 2;
388 int vertBlankStart = mode->CrtcVDisplay - 1;
389 int vertBlankEnd = mode->CrtcVTotal - 1;
391 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
392 bool fp_output = false;
395 for (i = 0; i < xf86_config->num_output; i++) {
396 xf86OutputPtr output = xf86_config->output[i];
397 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
399 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
400 nv_encoder->dcb->type == OUTPUT_TMDS))
405 vertStart = vertTotal - 3;
406 vertEnd = vertTotal - 2;
407 vertBlankStart = vertStart;
408 horizStart = horizTotal - 5;
409 horizEnd = horizTotal - 2;
410 horizBlankEnd = horizTotal + 4;
411 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
412 /* This reportedly works around some video overlay bandwidth problems */
416 if (mode->Flags & V_INTERLACE)
420 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
421 ErrorF("horizStart: 0x%X \n", horizStart);
422 ErrorF("horizEnd: 0x%X \n", horizEnd);
423 ErrorF("horizTotal: 0x%X \n", horizTotal);
424 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
425 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
426 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
427 ErrorF("vertStart: 0x%X \n", vertStart);
428 ErrorF("vertEnd: 0x%X \n", vertEnd);
429 ErrorF("vertTotal: 0x%X \n", vertTotal);
430 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
431 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
435 * compute correct Hsync & Vsync polarity
437 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
438 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
440 regp->MiscOutReg = 0x23;
441 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
442 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
444 int VDisplay = mode->VDisplay;
445 if (mode->Flags & V_DBLSCAN)
448 VDisplay *= mode->VScan;
450 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
451 else if (VDisplay < 480)
452 regp->MiscOutReg = 0x63; /* -hsync +vsync */
453 else if (VDisplay < 768)
454 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
456 regp->MiscOutReg = 0x23; /* +hsync +vsync */
459 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
464 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
465 /* 0x20 disables the sequencer */
466 if (mode->Flags & V_CLKDIV2)
467 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
469 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
470 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
471 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
472 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
477 regp->CRTC[NV_CIO_CR_HDT_INDEX] = Set8Bits(horizTotal);
478 regp->CRTC[NV_CIO_CR_HDE_INDEX] = Set8Bits(horizDisplay);
479 regp->CRTC[NV_CIO_CR_HBS_INDEX] = Set8Bits(horizBlankStart);
480 regp->CRTC[NV_CIO_CR_HBE_INDEX] = SetBitField(horizBlankEnd,4:0,4:0)
482 regp->CRTC[NV_CIO_CR_HRS_INDEX] = Set8Bits(horizStart);
483 regp->CRTC[NV_CIO_CR_HRE_INDEX] = SetBitField(horizBlankEnd,5:5,7:7)
484 | SetBitField(horizEnd,4:0,4:0);
485 regp->CRTC[NV_CIO_CR_VDT_INDEX] = SetBitField(vertTotal,7:0,7:0);
486 regp->CRTC[NV_CIO_CR_OVL_INDEX] = SetBitField(vertTotal,8:8,0:0)
487 | SetBitField(vertDisplay,8:8,1:1)
488 | SetBitField(vertStart,8:8,2:2)
489 | SetBitField(vertBlankStart,8:8,3:3)
491 | SetBitField(vertTotal,9:9,5:5)
492 | SetBitField(vertDisplay,9:9,6:6)
493 | SetBitField(vertStart,9:9,7:7);
494 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
495 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = SetBitField(vertBlankStart,9:9,5:5)
497 | (mode->Flags & V_DBLSCAN) * NV_CIO_CR_CELL_HT_SCANDBL;
498 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
499 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
500 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
501 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
502 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
503 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
504 regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart);
505 /* What is the meaning of bit5, it is empty in the vga spec. */
506 regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
507 regp->CRTC[NV_CIO_CR_VDE_INDEX] = Set8Bits(vertDisplay);
508 /* framebuffer can be larger than crtc scanout area. */
509 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
510 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
511 regp->CRTC[NV_CIO_CR_VBS_INDEX] = Set8Bits(vertBlankStart);
512 regp->CRTC[NV_CIO_CR_VBE_INDEX] = Set8Bits(vertBlankEnd);
513 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
514 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
517 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
520 /* framebuffer can be larger than crtc scanout area. */
521 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
522 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
523 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = SetBitField(horizBlankEnd,6:6,4:4)
524 | SetBitField(vertBlankStart,10:10,3:3)
525 | SetBitField(vertStart,10:10,2:2)
526 | SetBitField(vertDisplay,10:10,1:1)
527 | SetBitField(vertTotal,10:10,0:0);
529 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = SetBitField(horizTotal,8:8,0:0)
530 | SetBitField(horizDisplay,8:8,1:1)
531 | SetBitField(horizBlankStart,8:8,2:2)
532 | SetBitField(horizStart,8:8,3:3);
534 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = SetBitField(vertTotal,11:11,0:0)
535 | SetBitField(vertDisplay,11:11,2:2)
536 | SetBitField(vertStart,11:11,4:4)
537 | SetBitField(vertBlankStart,11:11,6:6);
539 if(mode->Flags & V_INTERLACE) {
540 horizTotal = (horizTotal >> 1) & ~1;
541 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = Set8Bits(horizTotal);
542 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= SetBitField(horizTotal,8:8,4:4);
544 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
547 * Graphics Display Controller
549 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
550 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
551 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
552 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
553 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
554 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
555 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
556 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
557 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
559 regp->Attribute[0] = 0x00; /* standard colormap translation */
560 regp->Attribute[1] = 0x01;
561 regp->Attribute[2] = 0x02;
562 regp->Attribute[3] = 0x03;
563 regp->Attribute[4] = 0x04;
564 regp->Attribute[5] = 0x05;
565 regp->Attribute[6] = 0x06;
566 regp->Attribute[7] = 0x07;
567 regp->Attribute[8] = 0x08;
568 regp->Attribute[9] = 0x09;
569 regp->Attribute[10] = 0x0A;
570 regp->Attribute[11] = 0x0B;
571 regp->Attribute[12] = 0x0C;
572 regp->Attribute[13] = 0x0D;
573 regp->Attribute[14] = 0x0E;
574 regp->Attribute[15] = 0x0F;
575 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
577 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
578 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
579 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
580 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
584 * Sets up registers for the given mode/adjusted_mode pair.
586 * The clocks, CRTCs and outputs attached to this CRTC must be off.
588 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
589 * be easily turned on/off after this.
592 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
594 ScrnInfoPtr pScrn = crtc->scrn;
595 NVPtr pNv = NVPTR(pScrn);
596 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
597 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
598 NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
599 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
600 bool lvds_output = false, tmds_output = false;
603 for (i = 0; i < xf86_config->num_output; i++) {
604 xf86OutputPtr output = xf86_config->output[i];
605 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
607 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
609 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
613 /* Registers not directly related to the (s)vga mode */
615 /* bit2 = 0 -> fine pitched crtc granularity */
616 /* The rest disables double buffering on CRTC access */
617 regp->CRTC[NV_CIO_CRE_21] = 0xfa;
619 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
620 * 1 << 30 on 0x60.830), for no apparent reason */
621 regp->CRTC[NV_CIO_CRE_59] = 0x0;
622 if (tmds_output && pNv->Architecture < NV_ARCH_40)
623 regp->CRTC[NV_CIO_CRE_59] |= 0x1;
625 /* What is the meaning of this register? */
626 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
627 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
630 /* Except for rare conditions I2C is enabled on the primary crtc */
631 if (nv_crtc->head == 0)
632 regp->head |= NV_CRTC_FSEL_I2C;
633 /* Set overlay to desired crtc. */
634 if (pNv->overlayAdaptor) {
635 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
636 if (pPriv->overlayCRTC == nv_crtc->head)
637 regp->head |= NV_CRTC_FSEL_OVERLAY;
640 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
641 /* This fixes my cursor corruption issue */
642 regp->cursorConfig = 0x0;
643 if(mode->Flags & V_DBLSCAN)
644 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
645 if (pNv->alphaCursor) {
646 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
647 NV_CRTC_CURSOR_CONFIG_64PIXELS |
648 NV_CRTC_CURSOR_CONFIG_64LINES |
649 NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
651 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
653 /* Unblock some timings */
654 regp->CRTC[NV_CIO_CRE_53] = 0;
655 regp->CRTC[NV_CIO_CRE_54] = 0;
657 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
659 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
660 else if (tmds_output)
661 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
663 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
665 /* These values seem to vary */
666 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
667 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
669 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
671 /* What does this do?:
676 if (nv_crtc->head == 0)
677 regp->CRTC[NV_CIO_CRE_4B] = 0x81;
679 regp->CRTC[NV_CIO_CRE_4B] = 0x80;
682 regp->CRTC[NV_CIO_CRE_4B] |= 0x40;
684 /* The blob seems to take the current value from crtc 0, add 4 to that
685 * and reuse the old value for crtc 1 */
686 regp->CRTC[NV_CIO_CRE_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_CIO_CRE_52];
688 regp->CRTC[NV_CIO_CRE_52] += 4;
690 regp->unk830 = mode->CrtcVDisplay - 3;
691 regp->unk834 = mode->CrtcVDisplay - 1;
694 /* This is what the blob does */
695 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
697 /* Never ever modify gpio, unless you know very well what you're doing */
698 regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
701 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
703 regp->config = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
706 if (pNv->Architecture == NV_ARCH_40) {
707 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
708 regp->CRTC[NV_CIO_CRE_86] = 0x1;
711 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (pScrn->depth + 1) / 8;
712 /* Enable slaved mode */
713 if (lvds_output || tmds_output)
714 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
716 /* Generic PRAMDAC regs */
718 if (pNv->Architecture >= NV_ARCH_10)
719 /* Only bit that bios and blob set. */
720 regp->nv10_cursync = (1 << 25);
722 switch (pScrn->depth) {
725 regp->general = 0x00100130;
729 regp->general = 0x00101130;
732 if (pNv->alphaCursor)
733 /* PIPE_LONG mode, something to do with the size of the cursor? */
734 regp->general |= 1 << 29;
736 regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
738 /* Some values the blob sets */
740 regp->unk_a24 = 0xfffff;
744 /* this could be set in nv_output, but would require some rework of load/save */
746 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
748 ScrnInfoPtr pScrn = crtc->scrn;
749 NVPtr pNv = NVPTR(pScrn);
750 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
751 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
752 NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
753 struct nouveau_encoder *nv_encoder = NULL;
754 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
756 bool is_lvds = false;
757 uint32_t mode_ratio, panel_ratio;
760 for (i = 0; i < xf86_config->num_output; i++) {
761 xf86OutputPtr output = xf86_config->output[i];
762 /* assuming one fp output per crtc seems ok */
763 nv_encoder = to_nouveau_encoder(output);
765 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
767 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
775 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
776 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
777 if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
778 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
780 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
781 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
782 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
783 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
784 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
786 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
787 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
788 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
789 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
790 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
791 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
792 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
795 * bit0: positive vsync
796 * bit4: positive hsync
797 * bit8: enable center mode
798 * bit9: enable native mode
799 * bit24: 12/24 bit interface (12bit=on, 24bit=off)
800 * bit26: a bit sometimes seen on some g70 cards
801 * bit28: fp display enable bit
802 * bit31: set for dual link LVDS
805 regp->fp_control = (savep->fp_control & 0x04100000) |
806 NV_RAMDAC_FP_CONTROL_DISPEN_POS;
808 /* Deal with vsync/hsync polarity */
809 /* LVDS screens do set this, but modes with +ve syncs are very rare */
810 if (adjusted_mode->Flags & V_PVSYNC)
811 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
812 if (adjusted_mode->Flags & V_PHSYNC)
813 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
815 if (nv_encoder->scaling_mode == SCALE_PANEL ||
816 nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
817 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
818 /* This is also true for panel scaling, so we must put the panel scale check first */
819 else if (mode->HDisplay == adjusted_mode->HDisplay &&
820 mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
821 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
822 else /* gpu needs to scale */
823 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
825 if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
826 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
828 if (is_lvds && pNv->VBIOS.fp.dual_link)
829 regp->fp_control |= (8 << 28);
831 /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
832 regp->debug_0 = 0x01101191;
833 /* We want automatic scaling */
835 /* This can override HTOTAL and VTOTAL */
838 /* Use 20.12 fixed point format to avoid floats */
839 mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
840 panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
841 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
842 * get treated the same as SCALE_FULLSCREEN */
843 if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
844 uint32_t diff, scale;
846 if (mode_ratio < panel_ratio) {
847 /* vertical needs to expand to glass size (automatic)
848 * horizontal needs to be scaled at vertical scale factor
849 * to maintain aspect */
851 scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
852 regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
854 /* restrict area of screen used, horizontally */
855 diff = adjusted_mode->HDisplay -
856 adjusted_mode->VDisplay * mode_ratio / (1 << 12);
857 regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
858 regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
861 if (mode_ratio > panel_ratio) {
862 /* horizontal needs to expand to glass size (automatic)
863 * vertical needs to be scaled at horizontal scale factor
864 * to maintain aspect */
866 scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
867 regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
869 /* restrict area of screen used, vertically */
870 diff = adjusted_mode->VDisplay -
871 (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
872 regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
873 regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
877 /* Flatpanel support needs at least a NV10 */
879 /* Output property. */
880 if (nv_encoder && nv_encoder->dithering) {
881 if (pNv->NVArch == 0x11)
882 regp->dither = savep->dither | 0x00010000;
885 regp->dither = savep->dither | 0x00000001;
886 for (i = 0; i < 3; i++) {
887 regp->dither_regs[i] = 0xe4e4e4e4;
888 regp->dither_regs[i + 3] = 0x44444444;
892 if (pNv->NVArch != 0x11) {
895 for (i = 0; i < 3; i++) {
896 regp->dither_regs[i] = savep->dither_regs[i];
897 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
900 regp->dither = savep->dither;
903 regp->dither = savep->dither;
907 * Sets up registers for the given mode/adjusted_mode pair.
909 * The clocks, CRTCs and outputs attached to this CRTC must be off.
911 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
912 * be easily turned on/off after this.
915 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
916 DisplayModePtr adjusted_mode,
919 ScrnInfoPtr pScrn = crtc->scrn;
920 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
921 NVPtr pNv = NVPTR(pScrn);
923 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CTRC mode on CRTC %d:\n", nv_crtc->head);
924 xf86PrintModeline(pScrn->scrnIndex, mode);
925 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output mode on CRTC %d:\n", nv_crtc->head);
926 xf86PrintModeline(pScrn->scrnIndex, adjusted_mode);
928 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
930 /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
931 if (pNv->Architecture == NV_ARCH_40)
932 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
933 nv_crtc_mode_set_regs(crtc, mode);
934 nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
935 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
937 NVVgaProtect(pNv, nv_crtc->head, true);
938 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
939 nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
940 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
941 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
942 nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
944 NVVgaProtect(pNv, nv_crtc->head, false);
946 NVCrtcSetBase(crtc, x, y);
948 #if X_BYTE_ORDER == X_BIG_ENDIAN
949 /* turn on LFB swapping */
951 uint8_t tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
952 tmp |= NV_CIO_CRE_RCR_ENDIAN_BIG;
953 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp);
958 static void nv_crtc_save(xf86CrtcPtr crtc)
960 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
961 NVPtr pNv = NVPTR(crtc->scrn);
964 NVSetOwner(pNv, nv_crtc->head);
966 /* We just came back from terminal, so unlock */
967 NVCrtcLockUnlock(crtc, false);
969 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
970 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
971 nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
972 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
973 nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
975 /* init some state to saved value */
976 pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
977 pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
978 pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX];
981 static void nv_crtc_restore(xf86CrtcPtr crtc)
983 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
984 NVPtr pNv = NVPTR(crtc->scrn);
986 /* Just to be safe */
987 NVCrtcLockUnlock(crtc, false);
990 NVSetOwner(pNv, nv_crtc->head);
992 NVVgaProtect(pNv, nv_crtc->head, true);
993 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
994 nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
995 nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
996 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
997 nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
998 NVVgaProtect(pNv, nv_crtc->head, false);
1000 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1003 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1005 ScrnInfoPtr pScrn = crtc->scrn;
1006 NVPtr pNv = NVPTR(pScrn);
1007 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1010 NVSetOwner(pNv, nv_crtc->head);
1013 NVCrtcLockUnlock(crtc, 0);
1015 crtc->funcs->dpms(crtc, DPMSModeOff);
1017 /* Sync the engine before adjust mode */
1018 if (pNv->EXADriverPtr) {
1019 exaMarkSync(pScrn->pScreen);
1020 exaWaitSync(pScrn->pScreen);
1023 NVBlankScreen(pNv, nv_crtc->head, true);
1025 /* Some more preperation. */
1026 NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
1027 if (pNv->Architecture == NV_ARCH_40) {
1028 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1029 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1033 static void nv_crtc_commit(xf86CrtcPtr crtc)
1035 crtc->funcs->dpms (crtc, DPMSModeOn);
1037 if (crtc->scrn->pScreen != NULL) {
1038 NVPtr pNv = NVPTR(crtc->scrn);
1040 xf86_reload_cursors (crtc->scrn->pScreen);
1041 if (!pNv->alphaCursor) {
1042 /* this works round the fact that xf86_reload_cursors
1043 * will quite happily show the hw cursor when it knows
1044 * the hardware can't do alpha, and the current cursor
1045 * has an alpha channel
1047 xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1048 xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1053 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1055 xfree(to_nouveau_crtc(crtc));
1058 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1063 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1068 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1071 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1072 ScrnInfoPtr pScrn = crtc->scrn;
1073 NVPtr pNv = NVPTR(pScrn);
1074 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1077 switch (pScrn->depth) {
1080 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1081 for (i = 0; i < 32; i++)
1082 for (j = 0; j < 8; j++) {
1083 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1084 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1085 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1090 /* First deal with the 5 bit colors */
1091 for (i = 0; i < 32; i++)
1092 for (j = 0; j < 8; j++) {
1093 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1094 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1096 /* Now deal with the 6 bit color */
1097 for (i = 0; i < 64; i++)
1098 for (j = 0; j < 4; j++)
1099 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1103 for (i = 0; i < 256; i++) {
1104 regp->DAC[i * 3] = red[i] >> 8;
1105 regp->DAC[(i * 3) + 1] = green[i] >> 8;
1106 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1111 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1115 * Allocates memory for a locked-in-framebuffer shadow of the given
1116 * width and height for this CRTC's rotated shadow framebuffer.
1120 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1122 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1123 ScrnInfoPtr pScrn = crtc->scrn;
1124 #if !NOUVEAU_EXA_PIXMAPS
1125 ScreenPtr pScreen = pScrn->pScreen;
1126 #endif /* !NOUVEAU_EXA_PIXMAPS */
1127 NVPtr pNv = NVPTR(pScrn);
1130 unsigned long rotate_pitch;
1131 int size, align = 64;
1133 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1134 size = rotate_pitch * height;
1136 assert(nv_crtc->shadow == NULL);
1137 #if NOUVEAU_EXA_PIXMAPS
1138 if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1139 align, size, &nv_crtc->shadow)) {
1140 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1144 if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1145 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1146 "Failed to map shadow buffer.\n");
1150 offset = nv_crtc->shadow->map;
1153 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1154 "Can't allocate shadow memory for rotated CRTC at server regeneration\n");
1157 nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1158 if (nv_crtc->shadow == NULL) {
1159 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1160 "Couldn't allocate shadow memory for rotated CRTC.\n");
1163 offset = pNv->FB->map + nv_crtc->shadow->offset;
1164 #endif /* NOUVEAU_EXA_PIXMAPS */
1170 * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1173 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1175 ScrnInfoPtr pScrn = crtc->scrn;
1176 #if NOUVEAU_EXA_PIXMAPS
1177 ScreenPtr pScreen = pScrn->pScreen;
1178 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1179 #endif /* NOUVEAU_EXA_PIXMAPS */
1180 unsigned long rotate_pitch;
1181 PixmapPtr rotate_pixmap;
1182 #if NOUVEAU_EXA_PIXMAPS
1183 struct nouveau_pixmap *nvpix;
1184 #endif /* NOUVEAU_EXA_PIXMAPS */
1187 data = crtc->funcs->shadow_allocate (crtc, width, height);
1189 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1191 #if NOUVEAU_EXA_PIXMAPS
1192 /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1193 rotate_pixmap = pScreen->CreatePixmap(pScreen,
1196 #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1201 #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1203 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1206 pScrn->bitsPerPixel,
1209 #endif /* NOUVEAU_EXA_PIXMAPS */
1211 if (rotate_pixmap == NULL) {
1212 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1213 "Couldn't allocate shadow pixmap for rotated CRTC\n");
1216 #if NOUVEAU_EXA_PIXMAPS
1217 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1219 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1221 nvpix->bo = nv_crtc->shadow;
1222 nvpix->mapped = TRUE;
1225 /* Modify the pixmap to actually be the one we need. */
1226 pScreen->ModifyPixmapHeader(rotate_pixmap,
1230 pScrn->bitsPerPixel,
1234 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1235 if (!nvpix || !nvpix->bo)
1236 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1237 #endif /* NOUVEAU_EXA_PIXMAPS */
1239 return rotate_pixmap;
1243 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1245 ScrnInfoPtr pScrn = crtc->scrn;
1246 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1247 ScreenPtr pScreen = pScrn->pScreen;
1249 if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1250 pScreen->DestroyPixmap(rotate_pixmap);
1253 #if !NOUVEAU_EXA_PIXMAPS
1254 if (data && nv_crtc->shadow) {
1255 exaOffscreenFree(pScreen, nv_crtc->shadow);
1257 #endif /* !NOUVEAU_EXA_PIXMAPS */
1259 nv_crtc->shadow = NULL;
1262 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1263 .dpms = nv_crtc_dpms,
1264 .save = nv_crtc_save,
1265 .restore = nv_crtc_restore,
1266 .mode_fixup = nv_crtc_mode_fixup,
1267 .mode_set = nv_crtc_mode_set,
1268 .prepare = nv_crtc_prepare,
1269 .commit = nv_crtc_commit,
1270 .destroy = nv_crtc_destroy,
1271 .lock = nv_crtc_lock,
1272 .unlock = nv_crtc_unlock,
1273 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1274 .set_cursor_position = nv_crtc_set_cursor_position,
1275 .show_cursor = nv_crtc_show_cursor,
1276 .hide_cursor = nv_crtc_hide_cursor,
1277 .load_cursor_argb = nv_crtc_load_cursor_argb,
1278 .gamma_set = nv_crtc_gamma_set,
1279 .shadow_create = nv_crtc_shadow_create,
1280 .shadow_allocate = nv_crtc_shadow_allocate,
1281 .shadow_destroy = nv_crtc_shadow_destroy,
1285 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1287 NVPtr pNv = NVPTR(pScrn);
1288 static xf86CrtcFuncsRec crtcfuncs;
1290 struct nouveau_crtc *nv_crtc;
1291 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1294 crtcfuncs = nv_crtc_funcs;
1296 /* NV04-NV10 doesn't support alpha cursors */
1297 if (pNv->NVArch < 0x11) {
1298 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1299 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1300 crtcfuncs.load_cursor_argb = NULL;
1303 crtcfuncs.shadow_create = NULL;
1304 crtcfuncs.shadow_allocate = NULL;
1305 crtcfuncs.shadow_destroy = NULL;
1308 if (!(crtc = xf86CrtcCreate(pScrn, &crtcfuncs)))
1311 if (!(nv_crtc = xcalloc(1, sizeof (struct nouveau_crtc)))) {
1312 xf86CrtcDestroy(crtc);
1316 nv_crtc->head = crtc_num;
1317 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1319 crtc->driver_private = nv_crtc;
1321 /* Initialise the default LUT table. */
1322 for (i = 0; i < 256; i++) {
1324 regp->DAC[(i*3)+1] = i;
1325 regp->DAC[(i*3)+2] = i;
1328 NVCrtcLockUnlock(crtc, false);
1331 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1333 ScrnInfoPtr pScrn = crtc->scrn;
1334 NVPtr pNv = NVPTR(pScrn);
1335 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1337 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1339 NVWritePRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
1341 for (i = 0; i < 5; i++)
1342 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1344 for (i = 0; i < 25; i++)
1345 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1347 for (i = 0; i < 9; i++)
1348 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1350 NVSetEnablePalette(pNv, nv_crtc->head, true);
1351 for (i = 0; i < 21; i++)
1352 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1354 NVSetEnablePalette(pNv, nv_crtc->head, false);
1357 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1359 ScrnInfoPtr pScrn = crtc->scrn;
1360 NVPtr pNv = NVPTR(pScrn);
1361 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1365 regp = &state->crtc_reg[nv_crtc->head];
1367 if (pNv->Architecture >= NV_ARCH_10) {
1369 /* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some
1370 * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1371 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1373 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1374 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1375 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1376 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1377 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1378 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1379 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1380 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1381 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1383 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21, regp->CRTC[NV_CIO_CRE_21]);
1384 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1385 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1386 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1387 if (pNv->Architecture == NV_ARCH_40) {
1388 NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1389 NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1392 if (pNv->Architecture == NV_ARCH_40) {
1393 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1394 if (regp->config == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
1395 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1397 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1401 NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1402 NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1404 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX, regp->CRTC[NV_CIO_CRE_RPC0_INDEX]);
1405 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, regp->CRTC[NV_CIO_CRE_RPC1_INDEX]);
1406 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX, regp->CRTC[NV_CIO_CRE_LSR_INDEX]);
1407 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX, regp->CRTC[NV_CIO_CRE_PIXEL_INDEX]);
1408 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX, regp->CRTC[NV_CIO_CRE_LCD__INDEX]);
1409 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX, regp->CRTC[NV_CIO_CRE_HEB__INDEX]);
1410 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX, regp->CRTC[NV_CIO_CRE_ENH_INDEX]);
1411 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX, regp->CRTC[NV_CIO_CRE_FF_INDEX]);
1412 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX, regp->CRTC[NV_CIO_CRE_FFLWM__INDEX]);
1413 if (pNv->Architecture >= NV_ARCH_30)
1414 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47, regp->CRTC[NV_CIO_CRE_47]);
1416 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
1417 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
1418 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
1419 if (pNv->Architecture == NV_ARCH_40)
1420 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
1421 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX, regp->CRTC[NV_CIO_CRE_ILACE__INDEX]);
1423 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]);
1424 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]);
1425 if (pNv->Architecture >= NV_ARCH_10) {
1426 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX, regp->CRTC[NV_CIO_CRE_EBR_INDEX]);
1427 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB, regp->CRTC[NV_CIO_CRE_CSB]);
1428 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B, regp->CRTC[NV_CIO_CRE_4B]);
1429 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52, regp->CRTC[NV_CIO_CRE_52]);
1431 /* NV11 and NV20 stop at 0x52. */
1432 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1433 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53, regp->CRTC[NV_CIO_CRE_53]);
1434 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54, regp->CRTC[NV_CIO_CRE_54]);
1436 for (i = 0; i < 0x10; i++)
1437 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1438 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59, regp->CRTC[NV_CIO_CRE_59]);
1440 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85, regp->CRTC[NV_CIO_CRE_85]);
1441 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86, regp->CRTC[NV_CIO_CRE_86]);
1444 NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1446 /* Setting 1 on this value gives you interrupts for every vblank period. */
1447 NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1448 NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1451 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1453 ScrnInfoPtr pScrn = crtc->scrn;
1454 NVPtr pNv = NVPTR(pScrn);
1455 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1457 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1459 regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__READ);
1461 for (i = 0; i < 25; i++)
1462 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1464 NVSetEnablePalette(pNv, nv_crtc->head, true);
1465 for (i = 0; i < 21; i++)
1466 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1467 NVSetEnablePalette(pNv, nv_crtc->head, false);
1469 for (i = 0; i < 9; i++)
1470 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1472 for (i = 0; i < 5; i++)
1473 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1476 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1478 ScrnInfoPtr pScrn = crtc->scrn;
1479 NVPtr pNv = NVPTR(pScrn);
1480 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1484 regp = &state->crtc_reg[nv_crtc->head];
1486 regp->CRTC[NV_CIO_CRE_LCD__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX);
1487 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX);
1488 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX);
1489 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX);
1490 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX);
1491 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX);
1492 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX);
1494 regp->CRTC[NV_CIO_CRE_FF_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX);
1495 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX);
1496 regp->CRTC[NV_CIO_CRE_21] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21);
1497 if (pNv->Architecture >= NV_ARCH_30)
1498 regp->CRTC[NV_CIO_CRE_47] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47);
1499 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1500 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1501 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1502 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX);
1504 if (pNv->Architecture >= NV_ARCH_10) {
1505 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1506 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1507 if (pNv->Architecture == NV_ARCH_40) {
1508 regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1509 regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1512 regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1513 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1516 regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1517 regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1519 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX);
1520 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX);
1521 if (pNv->Architecture >= NV_ARCH_10) {
1522 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX);
1523 regp->CRTC[NV_CIO_CRE_CSB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB);
1524 regp->CRTC[NV_CIO_CRE_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B);
1525 regp->CRTC[NV_CIO_CRE_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52);
1527 /* NV11 and NV20 don't have this, they stop at 0x52. */
1528 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1529 for (i = 0; i < 0x10; i++)
1530 regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1532 regp->CRTC[NV_CIO_CRE_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59);
1533 regp->CRTC[NV_CIO_CRE_53] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53);
1534 regp->CRTC[NV_CIO_CRE_54] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54);
1536 regp->CRTC[NV_CIO_CRE_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85);
1537 regp->CRTC[NV_CIO_CRE_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86);
1540 regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1543 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1545 ScrnInfoPtr pScrn = crtc->scrn;
1546 NVPtr pNv = NVPTR(pScrn);
1547 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1551 regp = &state->crtc_reg[nv_crtc->head];
1553 regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1555 if (pNv->twoHeads) {
1556 if (pNv->NVArch >= 0x17)
1557 regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1558 regp->fp_control = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1559 regp->debug_0 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1560 regp->debug_1 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1561 regp->debug_2 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1563 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1564 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1565 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1568 if (pNv->NVArch == 0x11) {
1569 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1570 } else if (pNv->twoHeads) {
1571 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1572 for (i = 0; i < 3; i++) {
1573 regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1574 regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1577 if (pNv->Architecture >= NV_ARCH_10)
1578 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1580 /* The regs below are 0 for non-flatpanels, so you can load and save them */
1582 for (i = 0; i < 7; i++) {
1583 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1584 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1587 for (i = 0; i < 7; i++) {
1588 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1589 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1593 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1595 ScrnInfoPtr pScrn = crtc->scrn;
1596 NVPtr pNv = NVPTR(pScrn);
1597 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1601 regp = &state->crtc_reg[nv_crtc->head];
1603 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1605 if (pNv->twoHeads) {
1606 if (pNv->NVArch >= 0x17)
1607 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1608 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1609 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1610 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1611 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1612 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1613 uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1614 NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1617 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1618 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1619 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1622 if (pNv->NVArch == 0x11)
1623 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1624 else if (pNv->twoHeads) {
1625 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1626 for (i = 0; i < 3; i++) {
1627 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1628 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1631 if (pNv->Architecture >= NV_ARCH_10)
1632 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1634 /* The regs below are 0 for non-flatpanels, so you can load and save them */
1636 for (i = 0; i < 7; i++) {
1637 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1638 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1641 for (i = 0; i < 7; i++) {
1642 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1643 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1647 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1649 ScrnInfoPtr pScrn = crtc->scrn;
1650 NVPtr pNv = NVPTR(pScrn);
1651 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1652 uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1654 if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1655 #if NOUVEAU_EXA_PIXMAPS
1656 start = nv_crtc->shadow->offset;
1658 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
1661 start += pNv->FB->offset;
1663 /* 30 bits addresses in 32 bits according to haiku */
1665 pNv->ModeReg.crtc_reg[nv_crtc->head].fb_start = start;
1666 NVCrtcWriteCRTC(crtc, NV_CRTC_START, start);
1672 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1674 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1675 NVPtr pNv = NVPTR(crtc->scrn);
1676 int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1678 VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1679 VGA_WR08(pNv->REGS, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1681 for (i = 0; i < 768; i++) {
1682 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset);
1683 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1686 NVSetEnablePalette(pNv, nv_crtc->head, false);
1688 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1690 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1691 NVPtr pNv = NVPTR(crtc->scrn);
1692 int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1694 VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1695 VGA_WR08(pNv->REGS, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1697 for (i = 0; i < 768; i++) {
1698 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1699 NV_WR08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1702 NVSetEnablePalette(pNv, nv_crtc->head, false);