git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x08 or 0x09 pxclk in MHz
 130  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 131  *                                      high nibble for xlat strap value
 132  */
 133
 134 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 135 {
 136         NVWriteVGA(pNv, head, 0x57, index);
 137         NVWriteVGA(pNv, head, 0x58, value);
 138 }
 139
 140 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 141 {
 142         NVWriteVGA(pNv, head, 0x57, index);
 143         return NVReadVGA(pNv, head, 0x58);
 144 }
 145
 146 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         NVWriteVGA(pNv, nv_crtc->head, index, value);
 153 }
 154
 155 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         return NVReadVGA(pNv, nv_crtc->head, index);
 162 }
 163
 164 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 165 {
 166         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 167         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 168 }
 169
 170 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 171 {
 172         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 173         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 174 }
 175
 176 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 177 {
 178         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 179         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 180 }
 181
 182 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 183 {
 184         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 186 }
 187
 188
 189 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 190 {
 191   ScrnInfoPtr pScrn = crtc->scrn;
 192   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 193   NVPtr pNv = NVPTR(pScrn);
 194   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 195
 196   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 197   if (nv_crtc->paletteEnabled)
 198     index &= ~0x20;
 199   else
 200     index |= 0x20;
 201   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 202   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 203 }
 204
 205 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 206 {
 207   ScrnInfoPtr pScrn = crtc->scrn;
 208   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209   NVPtr pNv = NVPTR(pScrn);
 210   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213   if (nv_crtc->paletteEnabled)
 214     index &= ~0x20;
 215   else
 216     index |= 0x20;
 217   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 218   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 219 }
 220
 221 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 222 {
 223         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 224         ScrnInfoPtr pScrn = crtc->scrn;
 225         NVPtr pNv = NVPTR(pScrn);
 226         /* Non standard beheaviour required by NV11 */
 227         if (pNv) {
 228                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 229                 ErrorF("pre-Owner: 0x%X\n", owner);
 230                 if (owner == 0x04) {
 231                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 232                         ErrorF("pbus84: 0x%X\n", pbus84);
 233                         pbus84 &= ~(1<<28);
 234                         ErrorF("pbus84: 0x%X\n", pbus84);
 235                         nvWriteMC(pNv, 0x1084, pbus84);
 236                 }
 237                 /* The blob never writes owner to pcio1, so should we */
 238                 if (pNv->NVArch == 0x11) {
 239                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 240                 }
 241                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 242                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 243                 ErrorF("post-Owner: 0x%X\n", owner);
 244         } else {
 245                 ErrorF("pNv pointer is NULL\n");
 246         }
 247 }
 248
 249 static void
 250 NVEnablePalette(xf86CrtcPtr crtc)
 251 {
 252   ScrnInfoPtr pScrn = crtc->scrn;
 253   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 254   NVPtr pNv = NVPTR(pScrn);
 255   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 256
 257   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 258   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 259   nv_crtc->paletteEnabled = TRUE;
 260 }
 261
 262 static void
 263 NVDisablePalette(xf86CrtcPtr crtc)
 264 {
 265   ScrnInfoPtr pScrn = crtc->scrn;
 266   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 267   NVPtr pNv = NVPTR(pScrn);
 268   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 269
 270   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 271   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 272   nv_crtc->paletteEnabled = FALSE;
 273 }
 274
 275 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 276 {
 277  ScrnInfoPtr pScrn = crtc->scrn;
 278   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 279   NVPtr pNv = NVPTR(pScrn);
 280   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 281
 282   NV_WR08(pCRTCReg, reg, value);
 283 }
 284
 285 /* perform a sequencer reset */
 286 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 287 {
 288   if (start)
 289     NVWriteVgaSeq(crtc, 0x00, 0x1);
 290   else
 291     NVWriteVgaSeq(crtc, 0x00, 0x3);
 292
 293 }
 294 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 295 {
 296         CARD8 tmp;
 297
 298         if (on) {
 299                 tmp = NVReadVgaSeq(crtc, 0x1);
 300                 NVVgaSeqReset(crtc, TRUE);
 301                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 302
 303                 NVEnablePalette(crtc);
 304         } else {
 305                 /*
 306                  * Reenable sequencer, then turn on screen.
 307                  */
 308                 tmp = NVReadVgaSeq(crtc, 0x1);
 309                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 310                 NVVgaSeqReset(crtc, FALSE);
 311
 312                 NVDisablePalette(crtc);
 313         }
 314 }
 315
 316 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 317 {
 318         CARD8 cr11;
 319
 320         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 321         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 322         if (Lock) cr11 |= 0x80;
 323         else cr11 &= ~0x80;
 324         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 325 }
 326
 327 xf86OutputPtr
 328 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 329 {
 330         ScrnInfoPtr pScrn = crtc->scrn;
 331         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 332         int i;
 333         for (i = 0; i < xf86_config->num_output; i++) {
 334                 xf86OutputPtr output = xf86_config->output[i];
 335
 336                 if (output->crtc == crtc) {
 337                         return output;
 338                 }
 339         }
 340
 341         return NULL;
 342 }
 343
 344 xf86CrtcPtr
 345 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 346 {
 347         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 348         int i;
 349
 350         for (i = 0; i < xf86_config->num_crtc; i++) {
 351                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 352                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 353                 if (nv_crtc->crtc == index)
 354                         return crtc;
 355         }
 356
 357         return NULL;
 358 }
 359
 360 /*
 361  * Calculate the Video Clock parameters for the PLL.
 362  */
 363 static void CalcVClock (
 364         uint32_t                clockIn,
 365         uint32_t                *clockOut,
 366         CARD32          *pllOut,
 367         NVPtr           pNv
 368 )
 369 {
 370         unsigned lowM, highM, highP;
 371         unsigned DeltaNew, DeltaOld;
 372         unsigned VClk, Freq;
 373         unsigned M, N, P;
 374
 375         /* M: PLL reference frequency postscaler divider */
 376         /* P: PLL VCO output postscaler divider */
 377         /* N: PLL VCO postscaler setting */
 378
 379         DeltaOld = 0xFFFFFFFF;
 380
 381         VClk = (unsigned)clockIn;
 382
 383         /* Taken from Haiku, after someone with an NV28 had an issue */
 384         switch(pNv->NVArch) {
 385                 case 0x28:
 386                         lowM = 1;
 387                         highP = 32;
 388                         if (VClk > 340000) {
 389                                 highM = 2;
 390                         } else if (VClk > 200000) {
 391                                 highM = 4;
 392                         } else if (VClk > 150000) {
 393                                 highM = 6;
 394                         } else {
 395                                 highM = 14;
 396                         }
 397                         break;
 398                 default:
 399                         lowM = 1;
 400                         highP = 16;
 401                         if (VClk > 340000) {
 402                                 highM = 2;
 403                         } else if (VClk > 250000) {
 404                                 highM = 6;
 405                         } else {
 406                                 highM = 14;
 407                         }
 408                         break;
 409         }
 410
 411         for (P = 1; P <= highP; P++) {
 412                 Freq = VClk << P;
 413                 if ((Freq >= 128000) && (Freq <= 350000)) {
 414                         for (M = lowM; M <= highM; M++) {
 415                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 416                                 if (N <= 255) {
 417                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 418                                         if (Freq > VClk) {
 419                                                 DeltaNew = Freq - VClk;
 420                                         } else {
 421                                                 DeltaNew = VClk - Freq;
 422                                         }
 423                                         if (DeltaNew < DeltaOld) {
 424                                                 *pllOut   = (P << 16) | (N << 8) | M;
 425                                                 *clockOut = Freq;
 426                                                 DeltaOld  = DeltaNew;
 427                                         }
 428                                 }
 429                         }
 430                 }
 431         }
 432 }
 433
 434 static void CalcVClock2Stage (
 435         uint32_t                clockIn,
 436         uint32_t                *clockOut,
 437         CARD32          *pllOut,
 438         CARD32          *pllBOut,
 439         NVPtr           pNv
 440 )
 441 {
 442         unsigned DeltaNew, DeltaOld;
 443         unsigned VClk, Freq;
 444         unsigned M, N, P;
 445         unsigned lowM, highM, highP;
 446
 447         DeltaOld = 0xFFFFFFFF;
 448
 449         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 450
 451         VClk = (unsigned)clockIn;
 452
 453         /* Taken from Haiku, after someone with an NV28 had an issue */
 454         switch(pNv->NVArch) {
 455                 case 0x28:
 456                         lowM = 1;
 457                         highP = 32;
 458                         if (VClk > 340000) {
 459                                 highM = 2;
 460                         } else if (VClk > 200000) {
 461                                 highM = 4;
 462                         } else if (VClk > 150000) {
 463                                 highM = 6;
 464                         } else {
 465                                 highM = 14;
 466                         }
 467                         break;
 468                 default:
 469                         lowM = 1;
 470                         highP = 15;
 471                         if (VClk > 340000) {
 472                                 highM = 2;
 473                         } else if (VClk > 250000) {
 474                                 highM = 6;
 475                         } else {
 476                                 highM = 14;
 477                         }
 478                         break;
 479         }
 480
 481         for (P = 0; P <= highP; P++) {
 482                 Freq = VClk << P;
 483                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 484                         for (M = lowM; M <= highM; M++) {
 485                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 486                                 if ((N >= 5) && (N <= 255)) {
 487                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 488                                         if (Freq > VClk) {
 489                                                 DeltaNew = Freq - VClk;
 490                                         } else {
 491                                                 DeltaNew = VClk - Freq;
 492                                         }
 493                                         if (DeltaNew < DeltaOld) {
 494                                                 *pllOut   = (P << 16) | (N << 8) | M;
 495                                                 *clockOut = Freq;
 496                                                 DeltaOld  = DeltaNew;
 497                                         }
 498                                 }
 499                         }
 500                 }
 501         }
 502 }
 503
 504 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 505
 506 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 507 /* They are only valid for NV4x, appearantly reordered for NV5x */
 508 /* gpu pll: 0x4000 + 0x4004
 509  * unknown pll: 0x4008 + 0x400c
 510  * vpll1: 0x4010 + 0x4014
 511  * vpll2: 0x4018 + 0x401c
 512  * unknown pll: 0x4020 + 0x4024
 513  * unknown pll: 0x4038 + 0x403c
 514  * Some of the unknown's are probably memory pll's.
 515  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 516  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 517  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 518  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 519  *     bit8: A switch that turns of the second divider and multiplier off.
 520  *     bit12: Also a switch, i haven't seen it yet.
 521  *     bit16-19: p-divider
 522  *     but 28-31: Something related to the mode that is used (see bit8).
 523  * 2) bit0-7: m-divider (a)
 524  *     bit8-15: n-multiplier (a)
 525  *     bit16-23: m-divider (b)
 526  *     bit24-31: n-multiplier (b)
 527  */
 528
 529 /* Modifying the gpu pll for example requires:
 530  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 531  * This is not needed for the vpll's which have their own bits.
 532  */
 533
 534 static void
 535 CalculateVClkNV4x(
 536         NVPtr pNv,
 537         uint32_t requested_clock,
 538         uint32_t *given_clock,
 539         uint32_t *pll_a,
 540         uint32_t *pll_b,
 541         uint32_t *reg580,
 542         Bool    *db1_ratio,
 543         Bool primary,
 544         uint8_t special_bits
 545 )
 546 {
 547         uint32_t DeltaOld, DeltaNew;
 548         uint32_t freq, temp;
 549         /* We have 2 mulitpliers, 2 dividers and one post divider */
 550         /* Note that p is only 4 bits */
 551         uint32_t m1, m2, n1, n2, p;
 552         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 553
 554         DeltaOld = 0xFFFFFFFF;
 555
 556         /* This is no solid limit, but a reasonable boundary. */
 557         /* NV40 is a strange card, let's stay on the safe side .*/
 558         if (requested_clock < 120000 && pNv->NVArch > 0x40) {
 559                 *db1_ratio = TRUE;
 560                 /* Turn the second set of divider and multiplier off */
 561                 /* Neutral settings */
 562                 n2 = 1;
 563                 m2 = 1;
 564         } else {
 565                 *db1_ratio = FALSE;
 566                 /* Fixed at x4 for the moment */
 567                 n2 = 4;
 568                 m2 = 1;
 569         }
 570
 571         n2_best = n2;
 572         m2_best = m2;
 573
 574         /* Single pll */
 575         if (*db1_ratio) {
 576                 temp = 0.4975 * 250000;
 577                 p = 0;
 578
 579                 while (requested_clock <= temp) {
 580                         temp /= 2;
 581                         p++;
 582                 }
 583
 584                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 585                 /* The maximum clock is 25 Mhz */
 586                 for (m1 = 2; m1 <= 9; m1++) {
 587                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 588                         if (n1 > 0 && n1 <= 255) {
 589                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 590                                 if (freq > requested_clock) {
 591                                         DeltaNew = freq - requested_clock;
 592                                 } else {
 593                                         DeltaNew = requested_clock - freq;
 594                                 }
 595                                 if (DeltaNew < DeltaOld) {
 596                                         m1_best = m1;
 597                                         n1_best = n1;
 598                                         p_best = p;
 599                                         DeltaOld = DeltaNew;
 600                                 }
 601                         }
 602                 }
 603         /* Dual pll */
 604         } else {
 605                 for (p = 0; p <= 6; p++) {
 606                         /* Assuming a fixed 2nd stage */
 607                         freq = requested_clock << p;
 608                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 609                         if (freq > 400000 && freq < 1000000) {
 610                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 611                                 /* The maximum clock is 25 Mhz */
 612                                 for (m1 = 2; m1 <= 9; m1++) {
 613                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 614                                         if (n1 >= 5 && n1 <= 255) {
 615                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 616                                                 if (freq > requested_clock) {
 617                                                         DeltaNew = freq - requested_clock;
 618                                                 } else {
 619                                                         DeltaNew = requested_clock - freq;
 620                                                 }
 621                                                 if (DeltaNew < DeltaOld) {
 622                                                         m1_best = m1;
 623                                                         n1_best = n1;
 624                                                         p_best = p;
 625                                                         DeltaOld = DeltaNew;
 626                                                 }
 627                                         }
 628                                 }
 629                         }
 630                 }
 631         }
 632
 633         if (*db1_ratio) {
 634                 /* Bogus data, the same nvidia uses */
 635                 n2_best = 1;
 636                 m2_best = 31;
 637         }
 638
 639         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 640         /* Let's keep the special bits, if the bios already set them */
 641         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 642         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 643
 644         if (*db1_ratio) {
 645                 if (primary) {
 646                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 647                 } else {
 648                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 649                 }
 650         } else {
 651                 if (primary) {
 652                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 653                 } else {
 654                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 655                 }
 656         }
 657
 658         if (*db1_ratio) {
 659                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 660         } else {
 661                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 662         }
 663 }
 664
 665 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 666 {
 667         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 668         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 669         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 670         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 671         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 672         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 673         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 674         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 675 }
 676
 677 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 678 {
 679         CARD32 fp_debug_0[2];
 680         uint32_t index[2];
 681         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 682         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 683
 684         /* The TMDS_PLL switch is on the actual ramdac */
 685         if (state->crosswired) {
 686                 index[0] = 1;
 687                 index[1] = 0;
 688                 ErrorF("Crosswired pll state load\n");
 689         } else {
 690                 index[0] = 0;
 691                 index[1] = 1;
 692         }
 693
 694         if (state->vpll2_b) {
 695                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 696                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 697
 698                 /* Wait for the situation to stabilise */
 699                 usleep(5000);
 700
 701                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 702                 /* for vpll2 change bits 18 and 19 are disabled */
 703                 reg_c040 &= ~(0x3 << 18);
 704                 nvWriteMC(pNv, 0xc040, reg_c040);
 705
 706                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 707                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 708
 709                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 710                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 711
 712                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 713                 /* Let's keep the primary vpll off */
 714                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 715
 716                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 717                 ErrorF("writing reg580 %08X\n", state->reg580);
 718
 719                 /* We need to wait a while */
 720                 usleep(5000);
 721                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 722
 723                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 724
 725                 /* Wait for the situation to stabilise */
 726                 usleep(5000);
 727         }
 728
 729         if (state->vpll1_b) {
 730                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 731                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 732
 733                 /* Wait for the situation to stabilise */
 734                 usleep(5000);
 735
 736                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 737                 /* for vpll2 change bits 16 and 17 are disabled */
 738                 reg_c040 &= ~(0x3 << 16);
 739                 nvWriteMC(pNv, 0xc040, reg_c040);
 740
 741                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 742                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 743
 744                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 745                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 746
 747                 ErrorF("writing pllsel %08X\n", state->pllsel);
 748                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 749
 750                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 751                 ErrorF("writing reg580 %08X\n", state->reg580);
 752
 753                 /* We need to wait a while */
 754                 usleep(5000);
 755                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 756
 757                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 758
 759                 /* Wait for the situation to stabilise */
 760                 usleep(5000);
 761         }
 762
 763         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 764         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 765
 766         ErrorF("writing reg594 %08X\n", state->reg594);
 767         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 768 }
 769
 770 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 771 {
 772         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 773         if(pNv->twoHeads) {
 774                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 775         }
 776         if(pNv->twoStagePLL) {
 777                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 778                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 779         }
 780         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 781         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 782 }
 783
 784
 785 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 786 {
 787         if (state->vpll2) {
 788                 if(pNv->twoHeads) {
 789                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 790                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 791                 }
 792                 if(pNv->twoStagePLL) {
 793                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 794                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 795                 }
 796
 797                 ErrorF("writing pllsel %08X\n", state->pllsel);
 798                 /* Let's keep the primary vpll off */
 799                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 800         }
 801
 802         if (state->vpll) {
 803                 ErrorF("writing vpll %08X\n", state->vpll);
 804                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 805                 if(pNv->twoStagePLL) {
 806                         ErrorF("writing vpllB %08X\n", state->vpllB);
 807                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 808                 }
 809
 810                 ErrorF("writing pllsel %08X\n", state->pllsel);
 811                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 812         }
 813
 814         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 815         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 816 }
 817
 818 /* It is unknown if the bus has a similar meaning on pre-NV40 hardware. */
 819 /* This code is currently used and pending removal should it turn out not be needed.*/
 820
 821 static uint8_t
 822 nv_get_sel_clk_offset(uint8_t NVArch, uint8_t bus)
 823 {
 824         switch(bus) {
 825                 case 0:
 826                         if (NVArch >= 0x44) {
 827                                 return 8;
 828                         } else {
 829                                 return 12;
 830                         }
 831                 case 1:
 832                         return 16;
 833                 case 2: /* bus 2 or 3 are either dvi on mobile or tv-out */
 834                 case 3: /* don't use this for tv-out */
 835                         return 4;
 836                 default:
 837                         ErrorF("Unknown bus, bad things may happen\n");
 838                         return 16;
 839         }
 840 }
 841
 842 static void
 843 nv_wipe_other_clocks(uint32_t *sel_clk, uint8_t NVArch, uint8_t head, uint8_t bus)
 844 {
 845         int i;
 846         /* head0 = 1, head1 = 4 */
 847         uint8_t our_clock = 1 + head*3;
 848
 849         if (!sel_clk)
 850                 return;
 851
 852         for (i = 0; i < 5; i++) {
 853                 int offset = i*4;
 854                 if (nv_get_sel_clk_offset(NVArch, bus) == offset) /* Let's keep our own clock */
 855                         continue;
 856
 857                 if (((*sel_clk << offset) & 0xf) == (our_clock << offset)) /* Let's wipe other entries */
 858                         *sel_clk &= ~(0xf << offset);
 859         }
 860 }
 861
 862 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 863 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 864
 865 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 866
 867 /*
 868  * Calculate extended mode parameters (SVGA) and save in a
 869  * mode state structure.
 870  * State is not specific to a single crtc, but shared.
 871  */
 872 void nv_crtc_calc_state_ext(
 873         xf86CrtcPtr     crtc,
 874         int                     bpp,
 875         int                     DisplayWidth, /* Does this change after setting the mode? */
 876         int                     CrtcHDisplay,
 877         int                     CrtcVDisplay,
 878         int                     dotClock,
 879         int                     flags
 880 )
 881 {
 882         ScrnInfoPtr pScrn = crtc->scrn;
 883         uint32_t pixelDepth, VClk = 0;
 884         CARD32 CursorStart;
 885         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 886         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 887         NVCrtcRegPtr regp;
 888         NVPtr pNv = NVPTR(pScrn);
 889         RIVA_HW_STATE *state, *sv_state;
 890         int num_crtc_enabled, i;
 891
 892         state = &pNv->ModeReg;
 893         sv_state = &pNv->SavedReg;
 894
 895         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 896
 897         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 898         NVOutputPrivatePtr nv_output = NULL;
 899         if (output) {
 900                 nv_output = output->driver_private;
 901         }
 902
 903         /*
 904          * Extended RIVA registers.
 905          */
 906         pixelDepth = (bpp + 1)/8;
 907         if (pNv->Architecture == NV_ARCH_40) {
 908                 /* Does register 0x580 already have a value? */
 909                 if (!state->reg580) {
 910                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 911                 }
 912                 if (nv_crtc->head == 1) {
 913                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE, (sv_state->vpll2_a >> 30));
 914                 } else {
 915                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE, (sv_state->vpll1_a >> 30));
 916                 }
 917         } else if (pNv->twoStagePLL) {
 918                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 919         } else {
 920                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 921         }
 922
 923         switch (pNv->Architecture) {
 924         case NV_ARCH_04:
 925                 nv4UpdateArbitrationSettings(VClk,
 926                                                 pixelDepth * 8,
 927                                                 &(state->arbitration0),
 928                                                 &(state->arbitration1),
 929                                                 pNv);
 930                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 931                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 932                 if (flags & V_DBLSCAN)
 933                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 934                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 935                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 936                 state->config   = 0x00001114;
 937                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 938                 break;
 939         case NV_ARCH_10:
 940         case NV_ARCH_20:
 941         case NV_ARCH_30:
 942         default:
 943                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 944                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 945                         state->arbitration0 = 128;
 946                         state->arbitration1 = 0x0480;
 947                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 948                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 949                         nForceUpdateArbitrationSettings(VClk,
 950                                                 pixelDepth * 8,
 951                                                 &(state->arbitration0),
 952                                                 &(state->arbitration1),
 953                                                 pNv);
 954                 } else if (pNv->Architecture < NV_ARCH_30) {
 955                         nv10UpdateArbitrationSettings(VClk,
 956                                                 pixelDepth * 8,
 957                                                 &(state->arbitration0),
 958                                                 &(state->arbitration1),
 959                                                 pNv);
 960                 } else {
 961                         nv30UpdateArbitrationSettings(pNv,
 962                                                 &(state->arbitration0),
 963                                                 &(state->arbitration1));
 964                 }
 965
 966                 CursorStart = pNv->Cursor->offset;
 967
 968                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 969                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 970                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 971
 972                 if (flags & V_DBLSCAN)
 973                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 974
 975                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 976                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 977                 break;
 978         }
 979
 980         /* okay do we have 2 CRTCs running ? */
 981         num_crtc_enabled = 0;
 982         for (i = 0; i < xf86_config->num_crtc; i++) {
 983                 if (xf86_config->crtc[i]->enabled) {
 984                         num_crtc_enabled++;
 985                 }
 986         }
 987
 988         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 989
 990         if (pNv->Architecture < NV_ARCH_40) {
 991                 /* We need this before the next code */
 992                 if (nv_crtc->head == 1) {
 993                         state->vpll2 = state->pll;
 994                         state->vpll2B = state->pllB;
 995                 } else {
 996                         state->vpll = state->pll;
 997                         state->vpllB = state->pllB;
 998                 }
 999         }
1000
1001         /* This stuff also applies to NV3x to some extend, but the rules may be different. */
1002         if (pNv->Architecture == NV_ARCH_40) {
1003                 /* This register is only used on the primary ramdac */
1004                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1005
1006                 if (!state->sel_clk)
1007                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1008
1009                 /* Note: Lower bits also exist, but trying to mess with those (in advance) is a bad idea.
1010                  * The blob doesn't do it, so it's probably not needed.
1011                  * I hope this solves the previous mess.
1012                  */
1013
1014                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1015                         /* Only wipe when are a relevant (digital) output. */
1016                         state->sel_clk &= ~(0xf << 16);
1017                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1018                         /* Even with two dvi, this should not conflict. */
1019                         if (crossed_clocks) {
1020                                 state->sel_clk |= (0x1 << 16);
1021                         } else {
1022                                 state->sel_clk |= (0x4 << 16);
1023                         }
1024                 }
1025
1026                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1027                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1028                  * This is all based on default settings found in mmio-traces.
1029                  * The blob never changes these, as it doesn't run unusual output configurations.
1030                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1031                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1032                  */
1033                 for (i = 0; i < 4; i++) {
1034                         if (state->sel_clk & (0xf << 4*i)) {
1035                                 state->sel_clk &= ~(0xf << 4*i);
1036                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1037                                 if (crossed_clocks) {
1038                                         state->sel_clk |= (0x4 << 4*i);
1039                                 } else {
1040                                         state->sel_clk |= (0x1 << 4*i);
1041                                 }
1042                                 break; /* This should only occur once. */
1043                         }
1044                 }
1045
1046                 /* Are we crosswired? */
1047                 if (output && nv_crtc->head != nv_output->preferred_output) {
1048                         state->crosswired = TRUE;
1049                 } else {
1050                         state->crosswired = FALSE;
1051                 }
1052
1053                 if (nv_crtc->head == 1) {
1054                         if (state->db1_ratio[1])
1055                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1056                 } else if (nv_crtc->head == 0) {
1057                         if (state->db1_ratio[0])
1058                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1059                 }
1060         } else {
1061                 /* This seems true for nv34 */
1062                 state->sel_clk = 0x0;
1063                 state->crosswired = FALSE;
1064         }
1065
1066         if (nv_crtc->head == 1) {
1067                 if (!state->db1_ratio[1]) {
1068                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1069                 } else {
1070                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1071                 }
1072                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1073         } else {
1074                 /* The NV40 seems to have more similarities to NV3x than other cards. */
1075                 if (pNv->NVArch < 0x41)
1076                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1077                 else
1078                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1079                 if (!state->db1_ratio[0]) {
1080                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1081                 } else {
1082                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1083                 }
1084         }
1085
1086         /* The blob uses this always, so let's do the same */
1087         if (pNv->Architecture == NV_ARCH_40) {
1088                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1089         }
1090
1091         /* The primary output doesn't seem to care */
1092         if (nv_output->preferred_output == 1) { /* This is the "output" */
1093                 /* non-zero values are for analog, don't know about tv-out and the likes */
1094                 if (output && nv_output->type != OUTPUT_ANALOG) {
1095                         state->reg594 = 0x0;
1096                 } else {
1097                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1098                         /* bit 16-19 are bits that are set on some G70 cards */
1099                         /* Those bits are also set to the 3rd OUTPUT register */
1100                         if (nv_crtc->head == 1) {
1101                                 state->reg594 = 0x101;
1102                         } else {
1103                                 state->reg594 = 0x1;
1104                         }
1105                 }
1106         }
1107
1108         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1109         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1110         if (pNv->Architecture >= NV_ARCH_30) {
1111                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1112         }
1113
1114         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1115         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1116 }
1117
1118 static void
1119 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1120 {
1121         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1122         ScrnInfoPtr pScrn = crtc->scrn;
1123         NVPtr pNv = NVPTR(pScrn);
1124         unsigned char seq1 = 0, crtc17 = 0;
1125         unsigned char crtc1A;
1126
1127         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1128
1129         NVCrtcSetOwner(crtc);
1130
1131         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1132         switch(mode) {
1133                 case DPMSModeStandby:
1134                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1135                 seq1 = 0x20;
1136                 crtc17 = 0x80;
1137                 crtc1A |= 0x80;
1138                 break;
1139         case DPMSModeSuspend:
1140                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1141                 seq1 = 0x20;
1142                 crtc17 = 0x80;
1143                 crtc1A |= 0x40;
1144                 break;
1145         case DPMSModeOff:
1146                 /* Screen: Off; HSync: Off, VSync: Off */
1147                 seq1 = 0x20;
1148                 crtc17 = 0x00;
1149                 crtc1A |= 0xC0;
1150                 break;
1151         case DPMSModeOn:
1152         default:
1153                 /* Screen: On; HSync: On, VSync: On */
1154                 seq1 = 0x00;
1155                 crtc17 = 0x80;
1156                 break;
1157         }
1158
1159         NVVgaSeqReset(crtc, TRUE);
1160         /* Each head has it's own sequencer, so we can turn it off when we want */
1161         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1162         NVWriteVgaSeq(crtc, 0x1, seq1);
1163         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1164         usleep(10000);
1165         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1166         NVVgaSeqReset(crtc, FALSE);
1167
1168         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1169
1170         /* I hope this is the right place */
1171         if (crtc->enabled && mode == DPMSModeOn) {
1172                 pNv->crtc_active[nv_crtc->head] = TRUE;
1173         } else {
1174                 pNv->crtc_active[nv_crtc->head] = FALSE;
1175         }
1176 }
1177
1178 static Bool
1179 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1180                      DisplayModePtr adjusted_mode)
1181 {
1182         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1183         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1184
1185         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1186         NVOutputPrivatePtr nv_output = NULL;
1187         if (output) {
1188                 nv_output = output->driver_private;
1189         }
1190
1191         /* For internal panels and gpu scaling on DVI we need the native mode */
1192         if (output && ((nv_output->type == OUTPUT_LVDS) || (nv_output->scaling_mode > 0 && (nv_output->type == OUTPUT_TMDS)))) {
1193                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1194                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1195                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1196                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1197                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1198                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1199                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1200                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1201                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1202                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1203                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1204
1205                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1206         }
1207
1208         return TRUE;
1209 }
1210
1211 static void
1212 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1213 {
1214         ScrnInfoPtr pScrn = crtc->scrn;
1215         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1216         NVCrtcRegPtr regp;
1217         NVPtr pNv = NVPTR(pScrn);
1218         NVFBLayout *pLayout = &pNv->CurrentLayout;
1219         int depth = pScrn->depth;
1220
1221         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1222
1223         /* Calculate our timings */
1224         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1225         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1226         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1227         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1228         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1229         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1230         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1231         int vertStart           = mode->CrtcVSyncStart          - 1;
1232         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1233         int vertTotal           = mode->CrtcVTotal                      - 2;
1234         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1235         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1236
1237         Bool is_fp = FALSE;
1238
1239         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1240         NVOutputPrivatePtr nv_output = NULL;
1241         if (output) {
1242                 nv_output = output->driver_private;
1243
1244                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1245                         is_fp = TRUE;
1246         }
1247
1248         ErrorF("Mode clock: %d\n", mode->Clock);
1249         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1250
1251         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1252         if (is_fp) {
1253                 vertStart = vertTotal - 3;
1254                 vertEnd = vertTotal - 2;
1255                 vertBlankStart = vertStart;
1256                 horizStart = horizTotal - 5;
1257                 horizEnd = horizTotal - 2;
1258                 horizBlankEnd = horizTotal + 4;
1259                 if (pNv->overlayAdaptor) {
1260                         /* This reportedly works around Xv some overlay bandwidth problems*/
1261                         horizTotal += 2;
1262                 }
1263         }
1264
1265         if(mode->Flags & V_INTERLACE)
1266                 vertTotal |= 1;
1267
1268         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1269         ErrorF("horizStart: 0x%X \n", horizStart);
1270         ErrorF("horizEnd: 0x%X \n", horizEnd);
1271         ErrorF("horizTotal: 0x%X \n", horizTotal);
1272         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1273         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1274         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1275         ErrorF("vertStart: 0x%X \n", vertStart);
1276         ErrorF("vertEnd: 0x%X \n", vertEnd);
1277         ErrorF("vertTotal: 0x%X \n", vertTotal);
1278         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1279         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1280
1281         /*
1282         * compute correct Hsync & Vsync polarity
1283         */
1284         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1285                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1286
1287                 regp->MiscOutReg = 0x23;
1288                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1289                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1290         } else {
1291                 int VDisplay = mode->VDisplay;
1292                 if (mode->Flags & V_DBLSCAN)
1293                         VDisplay *= 2;
1294                 if (mode->VScan > 1)
1295                         VDisplay *= mode->VScan;
1296                 if (VDisplay < 400) {
1297                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1298                 } else if (VDisplay < 480) {
1299                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1300                 } else if (VDisplay < 768) {
1301                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1302                 } else {
1303                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1304                 }
1305         }
1306
1307         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1308
1309         /*
1310         * Time Sequencer
1311         */
1312         if (depth == 4) {
1313                 regp->Sequencer[0] = 0x02;
1314         } else {
1315                 regp->Sequencer[0] = 0x00;
1316         }
1317         /* 0x20 disables the sequencer */
1318         if (mode->Flags & V_CLKDIV2) {
1319                 regp->Sequencer[1] = 0x29;
1320         } else {
1321                 regp->Sequencer[1] = 0x21;
1322         }
1323         if (depth == 1) {
1324                 regp->Sequencer[2] = 1 << BIT_PLANE;
1325         } else {
1326                 regp->Sequencer[2] = 0x0F;
1327                 regp->Sequencer[3] = 0x00;                     /* Font select */
1328         }
1329         if (depth < 8) {
1330                 regp->Sequencer[4] = 0x06;                             /* Misc */
1331         } else {
1332                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1333         }
1334
1335         /*
1336         * CRTC Controller
1337         */
1338         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1339         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1340         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1341         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1342                                 | SetBit(7);
1343         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1344         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1345                                 | SetBitField(horizEnd,4:0,4:0);
1346         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1347         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1348                                 | SetBitField(vertDisplay,8:8,1:1)
1349                                 | SetBitField(vertStart,8:8,2:2)
1350                                 | SetBitField(vertBlankStart,8:8,3:3)
1351                                 | SetBit(4)
1352                                 | SetBitField(vertTotal,9:9,5:5)
1353                                 | SetBitField(vertDisplay,9:9,6:6)
1354                                 | SetBitField(vertStart,9:9,7:7);
1355         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1356         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1357                                 | SetBit(6)
1358                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1359         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1360         regp->CRTC[0xb] = 0x00;
1361         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1362         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1363         regp->CRTC[0xe] = 0x00;
1364         regp->CRTC[0xf] = 0x00;
1365         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1366         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1367         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1368         regp->CRTC[0x14] = 0x00;
1369         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1370         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1371         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1372         /* 0x80 enables the sequencer, we don't want that */
1373         if (depth < 8) {
1374                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1375         } else {
1376                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1377         }
1378         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1379
1380         /*
1381          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1382          */
1383
1384         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1385                                 | SetBitField(vertBlankStart,10:10,3:3)
1386                                 | SetBitField(vertStart,10:10,2:2)
1387                                 | SetBitField(vertDisplay,10:10,1:1)
1388                                 | SetBitField(vertTotal,10:10,0:0);
1389
1390         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1391                                 | SetBitField(horizDisplay,8:8,1:1)
1392                                 | SetBitField(horizBlankStart,8:8,2:2)
1393                                 | SetBitField(horizStart,8:8,3:3);
1394
1395         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1396                                 | SetBitField(vertDisplay,11:11,2:2)
1397                                 | SetBitField(vertStart,11:11,4:4)
1398                                 | SetBitField(vertBlankStart,11:11,6:6);
1399
1400         if(mode->Flags & V_INTERLACE) {
1401                 horizTotal = (horizTotal >> 1) & ~1;
1402                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1403                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1404         } else {
1405                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1406         }
1407
1408         /*
1409         * Theory resumes here....
1410         */
1411
1412         /*
1413         * Graphics Display Controller
1414         */
1415         regp->Graphics[0] = 0x00;
1416         regp->Graphics[1] = 0x00;
1417         regp->Graphics[2] = 0x00;
1418         regp->Graphics[3] = 0x00;
1419         if (depth == 1) {
1420                 regp->Graphics[4] = BIT_PLANE;
1421                 regp->Graphics[5] = 0x00;
1422         } else {
1423                 regp->Graphics[4] = 0x00;
1424                 if (depth == 4) {
1425                         regp->Graphics[5] = 0x02;
1426                 } else {
1427                         regp->Graphics[5] = 0x40;
1428                 }
1429         }
1430         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1431         regp->Graphics[7] = 0x0F;
1432         regp->Graphics[8] = 0xFF;
1433
1434         /* I ditched the mono stuff */
1435         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1436         regp->Attribute[1]  = 0x01;
1437         regp->Attribute[2]  = 0x02;
1438         regp->Attribute[3]  = 0x03;
1439         regp->Attribute[4]  = 0x04;
1440         regp->Attribute[5]  = 0x05;
1441         regp->Attribute[6]  = 0x06;
1442         regp->Attribute[7]  = 0x07;
1443         regp->Attribute[8]  = 0x08;
1444         regp->Attribute[9]  = 0x09;
1445         regp->Attribute[10] = 0x0A;
1446         regp->Attribute[11] = 0x0B;
1447         regp->Attribute[12] = 0x0C;
1448         regp->Attribute[13] = 0x0D;
1449         regp->Attribute[14] = 0x0E;
1450         regp->Attribute[15] = 0x0F;
1451         /* These two below are non-vga */
1452         regp->Attribute[16] = 0x01;
1453         regp->Attribute[17] = 0x00;
1454         regp->Attribute[18] = 0x0F;
1455         regp->Attribute[19] = 0x00;
1456         regp->Attribute[20] = 0x00;
1457 }
1458
1459 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1460 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1461
1462 /**
1463  * Sets up registers for the given mode/adjusted_mode pair.
1464  *
1465  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1466  *
1467  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1468  * be easily turned on/off after this.
1469  */
1470 static void
1471 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1472 {
1473         ScrnInfoPtr pScrn = crtc->scrn;
1474         NVPtr pNv = NVPTR(pScrn);
1475         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1476         NVFBLayout *pLayout = &pNv->CurrentLayout;
1477         NVCrtcRegPtr regp, savep;
1478         unsigned int i;
1479         Bool is_fp = FALSE;
1480
1481         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1482         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1483
1484         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1485         NVOutputPrivatePtr nv_output = NULL;
1486         if (output) {
1487                 nv_output = output->driver_private;
1488
1489                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1490                         is_fp = TRUE;
1491         }
1492
1493         /* Registers not directly related to the (s)vga mode */
1494
1495         /* bit2 = 0 -> fine pitched crtc granularity */
1496         /* The rest disables double buffering on CRTC access */
1497         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1498
1499         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1500                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1501                 if (nv_crtc->head == 0) {
1502                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1503                 }
1504
1505                 if (is_fp) {
1506                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1507                 }
1508         } else {
1509                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1510                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1511         }
1512
1513         /* Sometimes 0x10 is used, what is this? */
1514         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1515         /* Some kind of tmds switch for older cards */
1516         if (pNv->Architecture < NV_ARCH_40) {
1517                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1518         }
1519
1520         /*
1521         * Initialize DAC palette.
1522         */
1523         if(pLayout->bitsPerPixel != 8 ) {
1524                 for (i = 0; i < 256; i++) {
1525                         regp->DAC[i*3]     = i;
1526                         regp->DAC[(i*3)+1] = i;
1527                         regp->DAC[(i*3)+2] = i;
1528                 }
1529         }
1530
1531         /*
1532         * Calculate the extended registers.
1533         */
1534
1535         if(pLayout->depth < 24) {
1536                 i = pLayout->depth;
1537         } else {
1538                 i = 32;
1539         }
1540
1541         if(pNv->Architecture >= NV_ARCH_10) {
1542                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1543         }
1544
1545         /* What is the meaning of this register? */
1546         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1547         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1548
1549         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1550         /* But what are those special conditions? */
1551         if (pNv->Architecture <= NV_ARCH_30) {
1552                 if (is_fp) {
1553                         if(nv_crtc->head == 1) {
1554                                 regp->head |= NV_CRTC_FSEL_FPP1;
1555                         } else if (pNv->twoHeads) {
1556                                 regp->head |= NV_CRTC_FSEL_FPP2;
1557                         }
1558                 }
1559         } else {
1560                 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1561                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1562                         regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1563                 }
1564         }
1565
1566         /* Except for rare conditions I2C is enabled on the primary crtc */
1567         if (nv_crtc->head == 0) {
1568                 if (pNv->overlayAdaptor) {
1569                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1570                 }
1571                 regp->head |= NV_CRTC_FSEL_I2C;
1572         }
1573
1574         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1575         /* This fixes my cursor corruption issue */
1576         regp->cursorConfig = 0x0;
1577         if(mode->Flags & V_DBLSCAN)
1578                 regp->cursorConfig |= (1 << 4);
1579         if (pNv->alphaCursor) {
1580                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1581                 regp->cursorConfig |= 0x14011000;
1582         } else {
1583                 regp->cursorConfig |= 0x02000000;
1584         }
1585
1586         /* Unblock some timings */
1587         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1588         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1589
1590         /* What is the purpose of this register? */
1591         /* 0x14 may be disabled? */
1592         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1593
1594         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1595         /* 0x11 is LVDS? */
1596         if (is_fp) {
1597                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1598         } else {
1599                 /* 0x20 is also seen sometimes, why? */
1600                 if (nv_crtc->head == 1) {
1601                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x24;
1602                 } else {
1603                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1604                 }
1605         }
1606
1607         /* These values seem to vary */
1608         if (nv_crtc->head == 1) {
1609                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1610         } else {
1611                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1612         }
1613
1614         /* 0x80 seems to be used very often, if not always */
1615         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1616
1617         if (nv_crtc->head == 1) {
1618                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1619         } else {
1620                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1621         }
1622
1623         if (is_fp)
1624                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1625
1626         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1627         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1628
1629         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1630         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1631
1632         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1633         if (nv_crtc->head == 1) {
1634                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1635         } else {
1636                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1637         }
1638
1639         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1640         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1641
1642         regp->unk830 = mode->CrtcVDisplay - 3;
1643         regp->unk834 = mode->CrtcVDisplay - 1;
1644
1645         /* This is what the blob does */
1646         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1647
1648         /* Never ever modify gpio, unless you know very well what you're doing */
1649         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1650
1651         /* Switch to non-vga mode (the so called HSYNC mode) */
1652         regp->config = 0x2;
1653
1654         /*
1655          * Calculate the state that is common to all crtc's (stored in the state struct).
1656          */
1657         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1658         nv_crtc_calc_state_ext(crtc,
1659                                 i,
1660                                 pScrn->displayWidth,
1661                                 mode->CrtcHDisplay,
1662                                 mode->CrtcVDisplay,
1663                                 adjusted_mode->Clock,
1664                                 mode->Flags);
1665
1666         /* Enable slaved mode */
1667         if (is_fp) {
1668                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1669         }
1670 }
1671
1672 static void
1673 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1674 {
1675         ScrnInfoPtr pScrn = crtc->scrn;
1676         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1677         NVCrtcRegPtr regp;
1678         NVPtr pNv = NVPTR(pScrn);
1679         NVFBLayout *pLayout = &pNv->CurrentLayout;
1680         Bool is_fp = FALSE;
1681         Bool is_lvds = FALSE;
1682         float aspect_ratio, panel_ratio;
1683         uint32_t h_scale, v_scale;
1684
1685         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1686
1687         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1688         NVOutputPrivatePtr nv_output = NULL;
1689         if (output) {
1690                 nv_output = output->driver_private;
1691
1692                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1693                         is_fp = TRUE;
1694
1695                 if (nv_output->type == OUTPUT_LVDS)
1696                         is_lvds = TRUE;
1697         }
1698
1699         if (is_fp) {
1700                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1701                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1702                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1703                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1704                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1705                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1706                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1707
1708                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1709                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1710                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1711                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1712                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1713                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1714                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1715
1716                 ErrorF("Horizontal:\n");
1717                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1718                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1719                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1720                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1721                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1722                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1723                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1724
1725                 ErrorF("Vertical:\n");
1726                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1727                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1728                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1729                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1730                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1731                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1732                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1733         }
1734
1735         /*
1736         * bit0: positive vsync
1737         * bit4: positive hsync
1738         * bit8: enable center mode
1739         * bit9: enable native mode
1740         * bit26: a bit sometimes seen on some g70 cards
1741         * bit31: set for dual link LVDS
1742         * nv10reg contains a few more things, but i don't quite get what it all means.
1743         */
1744
1745         if (pNv->Architecture >= NV_ARCH_30) {
1746                 regp->fp_control = 0x01100000;
1747         } else {
1748                 regp->fp_control = 0x00000000;
1749         }
1750
1751         if (is_fp) {
1752                 regp->fp_control |= (1 << 28);
1753         } else {
1754                 regp->fp_control |= (2 << 28);
1755                 if (pNv->Architecture < NV_ARCH_30)
1756                         regp->fp_control |= (1 << 24);
1757         }
1758
1759         if (is_lvds && pNv->VBIOS.fp.dual_link) {
1760                 regp->fp_control |= (8 << 28);
1761         } else {
1762                 /* If the special bit exists, it exists on both ramdac's */
1763                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1764         }
1765
1766         if (is_fp) {
1767                 if (nv_output->scaling_mode == 0) { /* panel needs to scale */
1768                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1769                 /* This is also true for panel scaling, so we must put the panel scale check first */
1770                 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1771                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1772                 } else { /* gpu needs to scale */
1773                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1774                 }
1775         }
1776
1777         /* Deal with vsync/hsync polarity */
1778         if (is_fp) {
1779                 if (adjusted_mode->Flags & V_PVSYNC) {
1780                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1781                 }
1782
1783                 if (adjusted_mode->Flags & V_PHSYNC) {
1784                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1785                 }
1786         } else {
1787                 /* The blob doesn't always do this, but often */
1788                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1789                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1790         }
1791
1792         if (is_fp) {
1793                 ErrorF("Pre-panel scaling\n");
1794                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1795                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1796                 ErrorF("panel_ratio=%f\n", panel_ratio);
1797                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1798                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1799                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1800                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1801                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1802                 ErrorF("h_scale=%d\n", h_scale);
1803                 ErrorF("v_scale=%d\n", v_scale);
1804
1805                 /* This can override HTOTAL and VTOTAL */
1806                 regp->debug_2 = 0;
1807
1808                 /* We want automatic scaling */
1809                 regp->debug_1 = 0;
1810
1811                 regp->fp_hvalid_start = 0;
1812                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1813
1814                 regp->fp_vvalid_start = 0;
1815                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1816
1817                 /* 0 = panel scaling */
1818                 if (nv_output->scaling_mode == 0) {
1819                         ErrorF("Flat panel is doing the scaling.\n");
1820                 } else {
1821                         ErrorF("GPU is doing the scaling.\n");
1822
1823                         /* 1 = fullscale gpu */
1824                         /* 2 = aspect ratio scaling */
1825                         /* 3 = no scaling */
1826                         if (nv_output->scaling_mode == 2) {
1827                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1828                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1829                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1830                                         uint32_t diff;
1831
1832                                         ErrorF("Scaling resolution on a widescreen panel\n");
1833
1834                                         /* Scaling in both directions needs to the same */
1835                                         h_scale = v_scale;
1836
1837                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1838                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1839
1840                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1841                                         regp->fp_hvalid_start = diff/2;
1842                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1843                                 }
1844
1845                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1846                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1847                                         uint32_t diff;
1848
1849                                         ErrorF("Scaling resolution on a portrait panel\n");
1850
1851                                         /* Scaling in both directions needs to the same */
1852                                         v_scale = h_scale;
1853
1854                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1855                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1856
1857                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1858                                         regp->fp_vvalid_start = diff/2;
1859                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1860                                 }
1861                         }
1862                 }
1863
1864                 ErrorF("Post-panel scaling\n");
1865         }
1866
1867         if (pNv->Architecture >= NV_ARCH_10) {
1868                 /* Bios and blob don't seem to do anything (else) */
1869                 regp->nv10_cursync = (1<<25);
1870         }
1871
1872         /* These are the common blob values, minus a few fp specific bit's */
1873         /* Let's keep the TMDS pll and fpclock running in all situations */
1874         regp->debug_0 = 0x1101100;
1875
1876         if (is_fp && nv_output->scaling_mode != 3) { /* !no_scale mode */
1877                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1878                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1879         } else if (is_fp) { /* no_scale mode, so we must center it */
1880                 uint32_t diff;
1881
1882                 diff = nv_output->fpWidth - mode->HDisplay;
1883                 regp->fp_hvalid_start = diff/2;
1884                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1885
1886                 diff = nv_output->fpHeight - mode->VDisplay;
1887                 regp->fp_vvalid_start = diff/2;
1888                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1889         }
1890
1891         /* Is this crtc bound or output bound? */
1892         /* Does the bios TMDS script try to change this sometimes? */
1893         if (is_fp) {
1894                 /* I am not completely certain, but seems to be set only for dfp's */
1895                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1896         }
1897
1898         if (output)
1899                 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
1900
1901         /* Flatpanel support needs at least a NV10 */
1902         if(pNv->twoHeads) {
1903                 /* The blob does this differently. */
1904                 /* TODO: Find out what precisely and why. */
1905                 if(pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
1906                         if (pNv->NVArch == 0x11) {
1907                                 regp->dither = 0x00010000;
1908                         } else {
1909                                 regp->dither = 0x00000001;
1910                         }
1911                 }
1912         }
1913
1914         /* Kindly borrowed from haiku driver */
1915         /* bit4 and bit5 activate indirect mode trough color palette */
1916         switch (pLayout->depth) {
1917                 case 32:
1918                 case 16:
1919                         regp->general = 0x00101130;
1920                         break;
1921                 case 24:
1922                 case 15:
1923                         regp->general = 0x00100130;
1924                         break;
1925                 case 8:
1926                 default:
1927                         regp->general = 0x00101100;
1928                         break;
1929         }
1930
1931         if (pNv->alphaCursor) {
1932                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1933                 regp->general |= (1<<29);
1934         }
1935
1936         /* Some values the blob sets */
1937         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1938         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1939         regp->unk_a20 = 0x0;
1940         regp->unk_a24 = 0xfffff;
1941         regp->unk_a34 = 0x1;
1942 }
1943
1944 /**
1945  * Sets up registers for the given mode/adjusted_mode pair.
1946  *
1947  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1948  *
1949  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1950  * be easily turned on/off after this.
1951  */
1952 static void
1953 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1954                  DisplayModePtr adjusted_mode,
1955                  int x, int y)
1956 {
1957         ScrnInfoPtr pScrn = crtc->scrn;
1958         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1959         NVPtr pNv = NVPTR(pScrn);
1960
1961         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1962
1963         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1964         xf86PrintModeline(pScrn->scrnIndex, mode);
1965         NVCrtcSetOwner(crtc);
1966
1967         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1968         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1969         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1970
1971         /* Just in case */
1972         NVCrtcLockUnlock(crtc, FALSE);
1973
1974         NVVgaProtect(crtc, TRUE);
1975         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1976         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1977         if (pNv->Architecture == NV_ARCH_40) {
1978                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1979         } else {
1980                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1981         }
1982         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1983
1984         NVVgaProtect(crtc, FALSE);
1985
1986         NVCrtcSetBase(crtc, x, y);
1987
1988 #if X_BYTE_ORDER == X_BIG_ENDIAN
1989         /* turn on LFB swapping */
1990         {
1991                 unsigned char tmp;
1992
1993                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1994                 tmp |= (1 << 7);
1995                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1996         }
1997 #endif
1998 }
1999
2000 void nv_crtc_save(xf86CrtcPtr crtc)
2001 {
2002         ScrnInfoPtr pScrn = crtc->scrn;
2003         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2004         NVPtr pNv = NVPTR(pScrn);
2005
2006         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
2007
2008         /* We just came back from terminal, so unlock */
2009         NVCrtcLockUnlock(crtc, FALSE);
2010
2011         NVCrtcSetOwner(crtc);
2012         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2013         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2014         if (pNv->Architecture == NV_ARCH_40) {
2015                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2016         } else {
2017                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2018         }
2019         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2020 }
2021
2022 void nv_crtc_restore(xf86CrtcPtr crtc)
2023 {
2024         ScrnInfoPtr pScrn = crtc->scrn;
2025         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2026         NVPtr pNv = NVPTR(pScrn);
2027         RIVA_HW_STATE *state;
2028
2029         state = &pNv->SavedReg;
2030
2031         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
2032
2033         NVCrtcSetOwner(crtc);
2034
2035         /* Just to be safe */
2036         NVCrtcLockUnlock(crtc, FALSE);
2037
2038         NVVgaProtect(crtc, TRUE);
2039         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2040         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2041         if (pNv->Architecture == NV_ARCH_40) {
2042                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
2043         } else {
2044                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2045         }
2046         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2047         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2048         NVVgaProtect(crtc, FALSE);
2049
2050         /* We must lock the door if we leave ;-) */
2051         NVCrtcLockUnlock(crtc, TRUE);
2052 }
2053
2054 void nv_crtc_prepare(xf86CrtcPtr crtc)
2055 {
2056         ScrnInfoPtr pScrn = crtc->scrn;
2057         NVPtr pNv = NVPTR(pScrn);
2058         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2059
2060         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
2061
2062         crtc->funcs->dpms(crtc, DPMSModeOff);
2063
2064         /* Sync the engine before adjust mode */
2065         if (pNv->EXADriverPtr) {
2066                 exaMarkSync(pScrn->pScreen);
2067                 exaWaitSync(pScrn->pScreen);
2068         }
2069 }
2070
2071 void nv_crtc_commit(xf86CrtcPtr crtc)
2072 {
2073         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2074         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
2075
2076         crtc->funcs->dpms (crtc, DPMSModeOn);
2077
2078         if (crtc->scrn->pScreen != NULL)
2079                 xf86_reload_cursors (crtc->scrn->pScreen);
2080 }
2081
2082 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2083 {
2084         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2085         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
2086
2087         return FALSE;
2088 }
2089
2090 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2091 {
2092         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2093         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
2094 }
2095
2096 static void
2097 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2098                                         int size)
2099 {
2100         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2101         ScrnInfoPtr pScrn = crtc->scrn;
2102         NVPtr pNv = NVPTR(pScrn);
2103         int i, j;
2104
2105         NVCrtcRegPtr regp;
2106         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2107
2108         switch (pNv->CurrentLayout.depth) {
2109         case 15:
2110                 /* R5G5B5 */
2111                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2112                 for (i = 0; i < 32; i++) {
2113                         for (j = 0; j < 8; j++) {
2114                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2115                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2116                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2117                         }
2118                 }
2119                 break;
2120         case 16:
2121                 /* R5G6B5 */
2122                 /* First deal with the 5 bit colors */
2123                 for (i = 0; i < 32; i++) {
2124                         for (j = 0; j < 8; j++) {
2125                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2126                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2127                         }
2128                 }
2129                 /* Now deal with the 6 bit color */
2130                 for (i = 0; i < 64; i++) {
2131                         for (j = 0; j < 4; j++) {
2132                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2133                         }
2134                 }
2135                 break;
2136         default:
2137                 /* R8G8B8 */
2138                 for (i = 0; i < 256; i++) {
2139                         regp->DAC[i * 3] = red[i] >> 8;
2140                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2141                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2142                 }
2143                 break;
2144         }
2145
2146         NVCrtcLoadPalette(crtc);
2147 }
2148
2149 /* NV04-NV10 doesn't support alpha cursors */
2150 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2151         .dpms = nv_crtc_dpms,
2152         .save = nv_crtc_save, /* XXX */
2153         .restore = nv_crtc_restore, /* XXX */
2154         .mode_fixup = nv_crtc_mode_fixup,
2155         .mode_set = nv_crtc_mode_set,
2156         .prepare = nv_crtc_prepare,
2157         .commit = nv_crtc_commit,
2158         .destroy = NULL, /* XXX */
2159         .lock = nv_crtc_lock,
2160         .unlock = nv_crtc_unlock,
2161         .set_cursor_colors = nv_crtc_set_cursor_colors,
2162         .set_cursor_position = nv_crtc_set_cursor_position,
2163         .show_cursor = nv_crtc_show_cursor,
2164         .hide_cursor = nv_crtc_hide_cursor,
2165         .load_cursor_image = nv_crtc_load_cursor_image,
2166         .gamma_set = nv_crtc_gamma_set,
2167 };
2168
2169 /* NV11 and up has support for alpha cursors. */
2170 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2171 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2172         .dpms = nv_crtc_dpms,
2173         .save = nv_crtc_save, /* XXX */
2174         .restore = nv_crtc_restore, /* XXX */
2175         .mode_fixup = nv_crtc_mode_fixup,
2176         .mode_set = nv_crtc_mode_set,
2177         .prepare = nv_crtc_prepare,
2178         .commit = nv_crtc_commit,
2179         .destroy = NULL, /* XXX */
2180         .lock = nv_crtc_lock,
2181         .unlock = nv_crtc_unlock,
2182         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2183         .set_cursor_position = nv_crtc_set_cursor_position,
2184         .show_cursor = nv_crtc_show_cursor,
2185         .hide_cursor = nv_crtc_hide_cursor,
2186         .load_cursor_argb = nv_crtc_load_cursor_argb,
2187         .gamma_set = nv_crtc_gamma_set,
2188 };
2189
2190
2191 void
2192 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2193 {
2194         NVPtr pNv = NVPTR(pScrn);
2195         xf86CrtcPtr crtc;
2196         NVCrtcPrivatePtr nv_crtc;
2197
2198         if (pNv->NVArch >= 0x11) {
2199                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2200         } else {
2201                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2202         }
2203         if (crtc == NULL)
2204                 return;
2205
2206         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2207         nv_crtc->crtc = crtc_num;
2208         nv_crtc->head = crtc_num;
2209
2210         crtc->driver_private = nv_crtc;
2211
2212         NVCrtcLockUnlock(crtc, FALSE);
2213 }
2214
2215 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2216 {
2217     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2218     int i;
2219     NVCrtcRegPtr regp;
2220
2221     regp = &state->crtc_reg[nv_crtc->head];
2222
2223     NVWriteMiscOut(crtc, regp->MiscOutReg);
2224
2225     for (i = 1; i < 5; i++)
2226       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2227
2228     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2229     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2230
2231     for (i = 0; i < 25; i++)
2232       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2233
2234     for (i = 0; i < 9; i++)
2235       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2236
2237     NVEnablePalette(crtc);
2238     for (i = 0; i < 21; i++)
2239       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2240     NVDisablePalette(crtc);
2241
2242 }
2243
2244 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2245 {
2246         /* TODO - implement this properly */
2247         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2248         ScrnInfoPtr pScrn = crtc->scrn;
2249         NVPtr pNv = NVPTR(pScrn);
2250
2251         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2252                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2253                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2254         }
2255 }
2256 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2257 {
2258     ScrnInfoPtr pScrn = crtc->scrn;
2259     NVPtr pNv = NVPTR(pScrn);
2260     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2261     NVCrtcRegPtr regp;
2262     int i;
2263
2264     regp = &state->crtc_reg[nv_crtc->head];
2265
2266     if(pNv->Architecture >= NV_ARCH_10) {
2267         if(pNv->twoHeads) {
2268            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2269         }
2270         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2271         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2272         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2273         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2274         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2275         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2276         nvWriteMC(pNv, 0x1588, 0);
2277
2278         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2279         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2280         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2281         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2282         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2283         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2284         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2285
2286         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2287
2288         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2289         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2290
2291         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2292         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2293         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2294         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2295         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2296         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2297         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2298         if (override) {
2299                 for (i = 0; i < 0x10; i++)
2300                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2301         }
2302         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2303         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2304     }
2305
2306     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2307     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2308     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2309     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2310     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2311     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2312     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2313     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2314     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2315     if(pNv->Architecture >= NV_ARCH_30) {
2316       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2317     }
2318
2319     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2320     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2321     nv_crtc_fix_nv40_hw_cursor(crtc);
2322     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2323     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2324
2325     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2326     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2327
2328     pNv->CurrentState = state;
2329 }
2330
2331 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2332 {
2333     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2334     int i;
2335     NVCrtcRegPtr regp;
2336
2337     regp = &state->crtc_reg[nv_crtc->head];
2338
2339     regp->MiscOutReg = NVReadMiscOut(crtc);
2340
2341     for (i = 0; i < 25; i++)
2342         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2343
2344     NVEnablePalette(crtc);
2345     for (i = 0; i < 21; i++)
2346         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2347     NVDisablePalette(crtc);
2348
2349     for (i = 0; i < 9; i++)
2350         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2351
2352     for (i = 1; i < 5; i++)
2353         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2354
2355 }
2356
2357 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2358 {
2359     ScrnInfoPtr pScrn = crtc->scrn;
2360     NVPtr pNv = NVPTR(pScrn);
2361     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2362     NVCrtcRegPtr regp;
2363     int i;
2364
2365     regp = &state->crtc_reg[nv_crtc->head];
2366
2367     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2368     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2369     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2370     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2371     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2372     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2373     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2374
2375     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2376     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2377     if(pNv->Architecture >= NV_ARCH_30) {
2378          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2379     }
2380     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2381     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2382     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2383     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2384
2385     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2386     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2387     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2388     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2389     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2390
2391         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2392
2393     if(pNv->Architecture >= NV_ARCH_10) {
2394         if(pNv->twoHeads) {
2395            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2396            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2397         }
2398         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2399
2400         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2401
2402         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2403         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2404         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2405         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2406         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2407         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2408         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2409         for (i = 0; i < 0x10; i++)
2410                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2411         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2412         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2413         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2414         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2415     }
2416 }
2417
2418 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2419 {
2420         ScrnInfoPtr pScrn = crtc->scrn;
2421         NVPtr pNv = NVPTR(pScrn);
2422         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2423         NVCrtcRegPtr regp;
2424         int i;
2425
2426         regp = &state->crtc_reg[nv_crtc->head];
2427
2428         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2429
2430         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2431         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2432         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2433         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2434
2435         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2436         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2437         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2438
2439         if (pNv->NVArch == 0x11) {
2440                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2441         } else if (pNv->twoHeads) {
2442                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2443         }
2444         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2445
2446         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2447
2448         for (i = 0; i < 7; i++) {
2449                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2450                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2451         }
2452
2453         for (i = 0; i < 7; i++) {
2454                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2455                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2456         }
2457
2458         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2459         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2460         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2461         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2462 }
2463
2464 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2465 {
2466         ScrnInfoPtr pScrn = crtc->scrn;
2467         NVPtr pNv = NVPTR(pScrn);
2468         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2469         NVCrtcRegPtr regp;
2470         int i;
2471
2472         regp = &state->crtc_reg[nv_crtc->head];
2473
2474         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2475
2476         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2477         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2478         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2479         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2480
2481         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2482         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2483         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2484
2485         if (pNv->NVArch == 0x11) {
2486                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2487         } else if (pNv->twoHeads) {
2488                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2489         }
2490         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2491
2492         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2493
2494         for (i = 0; i < 7; i++) {
2495                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2496                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2497         }
2498
2499         for (i = 0; i < 7; i++) {
2500                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2501                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2502         }
2503
2504         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2505         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2506         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2507         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2508 }
2509
2510 void
2511 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2512 {
2513         ScrnInfoPtr pScrn = crtc->scrn;
2514         NVPtr pNv = NVPTR(pScrn);
2515         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2516         NVFBLayout *pLayout = &pNv->CurrentLayout;
2517         CARD32 start = 0;
2518
2519         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2520
2521         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2522         start += pNv->FB->offset;
2523
2524         /* 30 bits addresses in 32 bits according to haiku */
2525         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2526
2527         /* set NV4/NV10 byte adress: (bit0 - 1) */
2528         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2529
2530         crtc->x = x;
2531         crtc->y = y;
2532 }
2533
2534 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2535 {
2536   ScrnInfoPtr pScrn = crtc->scrn;
2537   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2538   NVPtr pNv = NVPTR(pScrn);
2539   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2540
2541   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2542 }
2543
2544 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2545 {
2546   ScrnInfoPtr pScrn = crtc->scrn;
2547   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2548   NVPtr pNv = NVPTR(pScrn);
2549   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2550
2551   return NV_RD08(pDACReg, VGA_DAC_MASK);
2552 }
2553
2554 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2555 {
2556   ScrnInfoPtr pScrn = crtc->scrn;
2557   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2558   NVPtr pNv = NVPTR(pScrn);
2559   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2560
2561   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2562 }
2563
2564 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2565 {
2566   ScrnInfoPtr pScrn = crtc->scrn;
2567   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2568   NVPtr pNv = NVPTR(pScrn);
2569   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2570
2571   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2572 }
2573
2574 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2575 {
2576   ScrnInfoPtr pScrn = crtc->scrn;
2577   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2578   NVPtr pNv = NVPTR(pScrn);
2579   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2580
2581   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2582 }
2583
2584 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2585 {
2586   ScrnInfoPtr pScrn = crtc->scrn;
2587   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2588   NVPtr pNv = NVPTR(pScrn);
2589   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2590
2591   return NV_RD08(pDACReg, VGA_DAC_DATA);
2592 }
2593
2594 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2595 {
2596         int i;
2597         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2598         NVCrtcRegPtr regp;
2599         ScrnInfoPtr pScrn = crtc->scrn;
2600         NVPtr pNv = NVPTR(pScrn);
2601
2602         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2603
2604         NVCrtcSetOwner(crtc);
2605         NVCrtcWriteDacMask(crtc, 0xff);
2606         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2607
2608         for (i = 0; i<768; i++) {
2609                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2610         }
2611         NVDisablePalette(crtc);
2612 }
2613
2614 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2615 {
2616         unsigned char scrn;
2617
2618         NVCrtcSetOwner(crtc);
2619
2620         scrn = NVReadVgaSeq(crtc, 0x01);
2621         if (on) {
2622                 scrn &= ~0x20;
2623         } else {
2624                 scrn |= 0x20;
2625         }
2626
2627         NVVgaSeqReset(crtc, TRUE);
2628         NVWriteVgaSeq(crtc, 0x01, scrn);
2629         NVVgaSeqReset(crtc, FALSE);
2630 }
2631
2632 /*************************************************************************** \
2633 |*                                                                           *|
2634 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2635 |*                                                                           *|
2636 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2637 |*     international laws.  Users and possessors of this source code are     *|
2638 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2639 |*     use this code in individual and commercial software.                  *|
2640 |*                                                                           *|
2641 |*     Any use of this source code must include,  in the user documenta-     *|
2642 |*     tion and  internal comments to the code,  notices to the end user     *|
2643 |*     as follows:                                                           *|
2644 |*                                                                           *|
2645 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2646 |*                                                                           *|
2647 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2648 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2649 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2650 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2651 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2652 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2653 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2654 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2655 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2656 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2657 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2658 |*                                                                           *|
2659 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2660 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2661 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2662 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2663 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2664 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2665 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2666 |*     all U.S. Government End Users  acquire the source code  with only     *|
2667 |*     those rights set forth herein.                                        *|
2668 |*                                                                           *|
2669  \***************************************************************************/