git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #ifdef ENABLE_RANDR12
  35
  36 #include <assert.h>
  37 #include "xf86.h"
  38 #include "os.h"
  39 #include "mibank.h"
  40 #include "globals.h"
  41 #include "xf86.h"
  42 #include "xf86Priv.h"
  43 #include "xf86DDC.h"
  44 #include "mipointer.h"
  45 #include "windowstr.h"
  46 #include <randrstr.h>
  47 #include <X11/extensions/render.h>
  48
  49 #include "xf86Crtc.h"
  50 #include "nv_include.h"
  51
  52 #include "vgaHW.h"
  53
  54 #define CRTC_INDEX 0x3d4
  55 #define CRTC_DATA 0x3d5
  56 #define CRTC_IN_STAT_1 0x3da
  57
  58 #define WHITE_VALUE 0x3F
  59 #define BLACK_VALUE 0x00
  60 #define OVERSCAN_VALUE 0x01
  61
  62 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  66
  67 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD8 address)
  68 {
  69         ScrnInfoPtr pScrn = crtc->scrn;
  70         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  71         NVPtr pNv = NVPTR(pScrn);
  72
  73         if (nv_crtc->head == 1) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD8 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         if (nv_crtc->head == 1) {
  87                 NV_WR08(pNv->PVIO1, address, value);
  88         } else {
  89                 NV_WR08(pNv->PVIO0, address, value);
  90         }
  91 }
  92
  93 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  94 {
  95         ScrnInfoPtr pScrn = crtc->scrn;
  96         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  97         NVPtr pNv = NVPTR(pScrn);
  98
  99         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 100 }
 101
 102 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 103 {
 104         ScrnInfoPtr pScrn = crtc->scrn;
 105         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 106         NVPtr pNv = NVPTR(pScrn);
 107
 108         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 109 }
 110
 111 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 112 {
 113         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 114
 115         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 116         NV_WR08(pCRTCReg, CRTC_DATA, value);
 117 }
 118
 119 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 120 {
 121         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 122
 123         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 124         return NV_RD08(pCRTCReg, CRTC_DATA);
 125 }
 126
 127 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 128 {
 129         ScrnInfoPtr pScrn = crtc->scrn;
 130         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 131         NVPtr pNv = NVPTR(pScrn);
 132
 133         NVWriteVGA(pNv, nv_crtc->head, index, value);
 134 }
 135
 136 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 137 {
 138         ScrnInfoPtr pScrn = crtc->scrn;
 139         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 140         NVPtr pNv = NVPTR(pScrn);
 141
 142         return NVReadVGA(pNv, nv_crtc->head, index);
 143 }
 144
 145 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 146 {
 147         ScrnInfoPtr pScrn = crtc->scrn;
 148         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 149         NVPtr pNv = NVPTR(pScrn);
 150
 151         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 152         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 153 }
 154
 155 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 162         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 163 }
 164
 165 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 166 {
 167         ScrnInfoPtr pScrn = crtc->scrn;
 168         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 169         NVPtr pNv = NVPTR(pScrn);
 170
 171         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 172         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 173 }
 174
 175 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 176 {
 177         ScrnInfoPtr pScrn = crtc->scrn;
 178         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 179         NVPtr pNv = NVPTR(pScrn);
 180
 181         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 182         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 183 }
 184
 185
 186 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 187 {
 188   ScrnInfoPtr pScrn = crtc->scrn;
 189   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 190   NVPtr pNv = NVPTR(pScrn);
 191   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 192
 193   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 194   if (nv_crtc->paletteEnabled)
 195     index &= ~0x20;
 196   else
 197     index |= 0x20;
 198   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 199   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 200 }
 201
 202 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 203 {
 204   ScrnInfoPtr pScrn = crtc->scrn;
 205   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 206   NVPtr pNv = NVPTR(pScrn);
 207   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 208
 209   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 210   if (nv_crtc->paletteEnabled)
 211     index &= ~0x20;
 212   else
 213     index |= 0x20;
 214   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 215   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 216 }
 217
 218 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 219 {
 220         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 221         ScrnInfoPtr pScrn = crtc->scrn;
 222         NVPtr pNv = NVPTR(pScrn);
 223         /* Non standard beheaviour required by NV11 */
 224         if (pNv) {
 225                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 226                 ErrorF("pre-Owner: 0x%X\n", owner);
 227                 if (owner == 0x04) {
 228                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 229                         ErrorF("pbus84: 0x%X\n", pbus84);
 230                         pbus84 &= ~(1<<28);
 231                         ErrorF("pbus84: 0x%X\n", pbus84);
 232                         nvWriteMC(pNv, 0x1084, pbus84);
 233                 }
 234                 /* The blob never writes owner to pcio1, so should we */
 235                 if (pNv->NVArch == 0x11) {
 236                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 237                 }
 238                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 239                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 240                 ErrorF("post-Owner: 0x%X\n", owner);
 241         } else {
 242                 ErrorF("pNv pointer is NULL\n");
 243         }
 244 }
 245
 246 static void
 247 NVEnablePalette(xf86CrtcPtr crtc)
 248 {
 249   ScrnInfoPtr pScrn = crtc->scrn;
 250   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 251   NVPtr pNv = NVPTR(pScrn);
 252   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 253
 254   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 255   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 256   nv_crtc->paletteEnabled = TRUE;
 257 }
 258
 259 static void
 260 NVDisablePalette(xf86CrtcPtr crtc)
 261 {
 262   ScrnInfoPtr pScrn = crtc->scrn;
 263   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 264   NVPtr pNv = NVPTR(pScrn);
 265   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 266
 267   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 268   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 269   nv_crtc->paletteEnabled = FALSE;
 270 }
 271
 272 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 273 {
 274  ScrnInfoPtr pScrn = crtc->scrn;
 275   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 276   NVPtr pNv = NVPTR(pScrn);
 277   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 278
 279   NV_WR08(pCRTCReg, reg, value);
 280 }
 281
 282 /* perform a sequencer reset */
 283 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 284 {
 285   if (start)
 286     NVWriteVgaSeq(crtc, 0x00, 0x1);
 287   else
 288     NVWriteVgaSeq(crtc, 0x00, 0x3);
 289
 290 }
 291 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 292 {
 293   CARD8 tmp;
 294
 295   if (on) {
 296     tmp = NVReadVgaSeq(crtc, 0x1);
 297     NVVgaSeqReset(crtc, TRUE);
 298     NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 299
 300     NVEnablePalette(crtc);
 301   } else {
 302     /*
 303      * Reenable sequencer, then turn on screen.
 304      */
 305     tmp = NVReadVgaSeq(crtc, 0x1);
 306     NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20);     /* reenable display */
 307     NVVgaSeqReset(crtc, FALSE);
 308
 309     NVDisablePalette(crtc);
 310   }
 311 }
 312
 313 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 314 {
 315   CARD8 cr11;
 316
 317   NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 318   cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 319   if (Lock) cr11 |= 0x80;
 320   else cr11 &= ~0x80;
 321   NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 322 }
 323
 324 xf86OutputPtr
 325 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 326 {
 327         ScrnInfoPtr pScrn = crtc->scrn;
 328         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 329         int i;
 330         for (i = 0; i < xf86_config->num_output; i++) {
 331                 xf86OutputPtr output = xf86_config->output[i];
 332                 NVOutputPrivatePtr nv_output = output->driver_private;
 333
 334                 if (output->crtc == crtc) {
 335                         return output;
 336                 }
 337         }
 338 }
 339
 340 xf86CrtcPtr
 341 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 342 {
 343         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 344         int i;
 345
 346         for (i = 0; i < xf86_config->num_crtc; i++) {
 347                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 348                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 349                 if (nv_crtc->crtc == index)
 350                         return crtc;
 351         }
 352
 353         return NULL;
 354 }
 355
 356 /*
 357  * Calculate the Video Clock parameters for the PLL.
 358  */
 359 static void CalcVClock (
 360         int             clockIn,
 361         int             *clockOut,
 362         CARD32          *pllOut,
 363         NVPtr           pNv
 364 )
 365 {
 366         unsigned lowM, highM, highP;
 367         unsigned DeltaNew, DeltaOld;
 368         unsigned VClk, Freq;
 369         unsigned M, N, P;
 370
 371         /* M: PLL reference frequency postscaler divider */
 372         /* P: PLL VCO output postscaler divider */
 373         /* N: PLL VCO postscaler setting */
 374
 375         DeltaOld = 0xFFFFFFFF;
 376
 377         VClk = (unsigned)clockIn;
 378
 379         /* Taken from Haiku, after someone with an NV28 had an issue */
 380         switch(pNv->NVArch) {
 381                 case 0x28:
 382                         lowM = 1;
 383                         highP = 32;
 384                         if (VClk > 340000) {
 385                                 highM = 2;
 386                         } else if (VClk > 200000) {
 387                                 highM = 4;
 388                         } else if (VClk > 150000) {
 389                                 highM = 6;
 390                         } else {
 391                                 highM = 14;
 392                         }
 393                         break;
 394                 default:
 395                         lowM = 1;
 396                         highP = 16;
 397                         if (VClk > 340000) {
 398                                 highM = 2;
 399                         } else if (VClk > 250000) {
 400                                 highM = 6;
 401                         } else {
 402                                 highM = 14;
 403                         }
 404                         break;
 405         }
 406
 407         for (P = 0; P <= highP; P++) {
 408                 Freq = VClk << P;
 409                 if ((Freq >= 128000) && (Freq <= 350000)) {
 410                         for (M = lowM; M <= highM; M++) {
 411                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 412                                 if (N <= 255) {
 413                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 414                                         if (Freq > VClk) {
 415                                                 DeltaNew = Freq - VClk;
 416                                         } else {
 417                                                 DeltaNew = VClk - Freq;
 418                                         }
 419                                         if (DeltaNew < DeltaOld) {
 420                                                 *pllOut   = (P << 16) | (N << 8) | M;
 421                                                 *clockOut = Freq;
 422                                                 DeltaOld  = DeltaNew;
 423                                         }
 424                                 }
 425                         }
 426                 }
 427         }
 428 }
 429
 430 static void CalcVClock2Stage (
 431         int             clockIn,
 432         int             *clockOut,
 433         CARD32          *pllOut,
 434         CARD32          *pllBOut,
 435         NVPtr           pNv
 436 )
 437 {
 438         unsigned DeltaNew, DeltaOld;
 439         unsigned VClk, Freq;
 440         unsigned M, N, P;
 441         unsigned lowM, highM, highP;
 442
 443         DeltaOld = 0xFFFFFFFF;
 444
 445         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 446
 447         VClk = (unsigned)clockIn;
 448
 449         /* Taken from Haiku, after someone with an NV28 had an issue */
 450         switch(pNv->NVArch) {
 451                 case 0x28:
 452                         lowM = 1;
 453                         highP = 32;
 454                         if (VClk > 340000) {
 455                                 highM = 2;
 456                         } else if (VClk > 200000) {
 457                                 highM = 4;
 458                         } else if (VClk > 150000) {
 459                                 highM = 6;
 460                         } else {
 461                                 highM = 14;
 462                         }
 463                         break;
 464                 default:
 465                         lowM = 1;
 466                         highP = 16;
 467                         if (VClk > 340000) {
 468                                 highM = 2;
 469                         } else if (VClk > 250000) {
 470                                 highM = 6;
 471                         } else {
 472                                 highM = 14;
 473                         }
 474                         break;
 475         }
 476
 477         for (P = 0; P <= highP; P++) {
 478                 Freq = VClk << P;
 479                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 480                         for (M = lowM; M <= highM; M++) {
 481                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 482                                 if ((N >= 5) && (N <= 255)) {
 483                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 484                                         if (Freq > VClk) {
 485                                                 DeltaNew = Freq - VClk;
 486                                         } else {
 487                                                 DeltaNew = VClk - Freq;
 488                                         }
 489                                         if (DeltaNew < DeltaOld) {
 490                                                 *pllOut   = (P << 16) | (N << 8) | M;
 491                                                 *clockOut = Freq;
 492                                                 DeltaOld  = DeltaNew;
 493                                         }
 494                                 }
 495                         }
 496                 }
 497         }
 498 }
 499
 500 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 501 {
 502         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 503         if(pNv->twoHeads) {
 504                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 505         }
 506         if(pNv->twoStagePLL) {
 507                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 508                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 509         }
 510         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 511         /* Something is wrong with this, so let's leave it alone for the moment */
 512 #if 0
 513         /* This is almost a magic register */
 514         /* This seems to be strictly NV40 */
 515         if (pNv->Architecture == NV_ARCH_40) {
 516                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040 & ~(0x3 << 16));
 517                 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 518                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 519         }
 520 #endif
 521 }
 522
 523
 524 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 525 {
 526         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 527 #if 0
 528         if (pNv->Architecture == NV_ARCH_40) {
 529                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 530         }
 531 #endif
 532
 533         ErrorF("writing vpll %08X\n", state->vpll);
 534         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 535         if(pNv->twoHeads) {
 536                 ErrorF("writing vpll2 %08X\n", state->vpll2);
 537                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 538         }
 539         if(pNv->twoStagePLL) {
 540                 ErrorF("writing vpllB %08X\n", state->vpllB);
 541                 ErrorF("writing vpll2B %08X\n", state->vpll2B);
 542                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 543                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 544         }
 545 }
 546
 547 /*
 548  * Calculate extended mode parameters (SVGA) and save in a
 549  * mode state structure.
 550  */
 551 void nv_crtc_calc_state_ext(
 552         xf86CrtcPtr     crtc,
 553         int                     bpp,
 554         int                     DisplayWidth, /* Does this change after setting the mode? */
 555         int                     CrtcHDisplay,
 556         int                     CrtcVDisplay,
 557         int                     dotClock,
 558         int                     flags
 559 )
 560 {
 561         ScrnInfoPtr pScrn = crtc->scrn;
 562         int pixelDepth, VClk;
 563         CARD32 CursorStart;
 564         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 565         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 566         NVCrtcRegPtr regp;
 567         NVPtr pNv = NVPTR(pScrn);
 568         RIVA_HW_STATE *state;
 569         int num_crtc_enabled, i;
 570
 571         state = &pNv->ModeReg;
 572
 573         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 574
 575         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 576         NVOutputPrivatePtr nv_output = output->driver_private;
 577
 578         /*
 579          * Extended RIVA registers.
 580          */
 581         pixelDepth = (bpp + 1)/8;
 582         if(pNv->twoStagePLL)
 583                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 584         else
 585                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 586
 587         switch (pNv->Architecture) {
 588         case NV_ARCH_04:
 589                 nv4UpdateArbitrationSettings(VClk,
 590                                                 pixelDepth * 8,
 591                                                 &(state->arbitration0),
 592                                                 &(state->arbitration1),
 593                                                 pNv);
 594                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 595                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 596                 if (flags & V_DBLSCAN)
 597                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 598                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 599                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 600                 state->config   = 0x00001114;
 601                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 602                 break;
 603         case NV_ARCH_10:
 604         case NV_ARCH_20:
 605         case NV_ARCH_30:
 606         default:
 607                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 608                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 609                         state->arbitration0 = 128;
 610                         state->arbitration1 = 0x0480;
 611                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 612                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 613                         nForceUpdateArbitrationSettings(VClk,
 614                                                 pixelDepth * 8,
 615                                                 &(state->arbitration0),
 616                                                 &(state->arbitration1),
 617                                                 pNv);
 618                 } else if (pNv->Architecture < NV_ARCH_30) {
 619                         nv10UpdateArbitrationSettings(VClk,
 620                                                 pixelDepth * 8,
 621                                                 &(state->arbitration0),
 622                                                 &(state->arbitration1),
 623                                                 pNv);
 624                 } else {
 625                         nv30UpdateArbitrationSettings(pNv,
 626                                                 &(state->arbitration0),
 627                                                 &(state->arbitration1));
 628                 }
 629
 630                 CursorStart = pNv->Cursor->offset;
 631
 632                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 633                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 634                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 635
 636                 if (flags & V_DBLSCAN)
 637                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 638
 639                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 640                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 641                 break;
 642         }
 643
 644         /* okay do we have 2 CRTCs running ? */
 645         num_crtc_enabled = 0;
 646         for (i = 0; i < xf86_config->num_crtc; i++) {
 647                 if (xf86_config->crtc[i]->enabled) {
 648                         num_crtc_enabled++;
 649                 }
 650         }
 651
 652         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 653
 654         /* Something is wrong with this, so until it's proven to be needed, let's leave it alone */
 655 #if 0
 656         if (pNv->Architecture == NV_ARCH_40) {
 657                 /* Do not remove any present VPLL related bits, that can cause problems */
 658                 /* The meaning of this register is debatable */
 659                 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 660
 661                 /* Vclk ratio db1 is used whenever reg580 is modified for vpll activity */
 662                 if (!(pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2)) {
 663                         if (nv_crtc->crtc == 1) {
 664                                 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 665                                 state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 666                         } else {
 667                                 /* CRTC0 must always be active */
 668                                 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 669                         }
 670                 }
 671         }
 672 #endif
 673
 674         /* We've bound crtc's and ramdac's together */
 675         if (nv_crtc->crtc == 1) {
 676                 state->vpll2 = state->pll;
 677                 state->vpll2B = state->pllB;
 678                 if (pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2) {
 679                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 680                 } else {
 681                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 682                 }
 683                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_CRTC1;
 684         } else {
 685                 state->vpll = state->pll;
 686                 state->vpllB = state->pllB;
 687                 if (nv_output->type == OUTPUT_LVDS)
 688                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 689                 else
 690                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 691                 if (pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2) {
 692                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 693                 } else {
 694                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 695                 }
 696         }
 697
 698         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 699         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 700         if (pNv->Architecture >= NV_ARCH_30) {
 701                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 702         }
 703
 704         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 705         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 706 }
 707
 708 static void
 709 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 710 {
 711         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 712         ScrnInfoPtr pScrn = crtc->scrn;
 713         NVPtr pNv = NVPTR(pScrn);
 714         unsigned char seq1 = 0, crtc17 = 0;
 715         unsigned char crtc1A;
 716         int ret;
 717
 718         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
 719
 720         NVCrtcSetOwner(crtc);
 721
 722         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 723         switch(mode) {
 724                 case DPMSModeStandby:
 725                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 726                 seq1 = 0x20;
 727                 crtc17 = 0x80;
 728                 crtc1A |= 0x80;
 729                 break;
 730         case DPMSModeSuspend:
 731                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 732                 seq1 = 0x20;
 733                 crtc17 = 0x80;
 734                 crtc1A |= 0x40;
 735                 break;
 736         case DPMSModeOff:
 737                 /* Screen: Off; HSync: Off, VSync: Off */
 738                 seq1 = 0x20;
 739                 crtc17 = 0x00;
 740                 crtc1A |= 0xC0;
 741                 break;
 742         case DPMSModeOn:
 743         default:
 744                 /* Screen: On; HSync: On, VSync: On */
 745                 seq1 = 0x00;
 746                 crtc17 = 0x80;
 747                 break;
 748         }
 749
 750         NVVgaSeqReset(crtc, TRUE);
 751         /* Each head has it's own sequencer, so we can turn it off when we want */
 752         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
 753         NVWriteVgaSeq(crtc, 0x1, seq1);
 754         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
 755         usleep(10000);
 756         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
 757         NVVgaSeqReset(crtc, FALSE);
 758
 759         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
 760
 761         /* I hope this is the right place */
 762         if (crtc->enabled && mode == DPMSModeOn) {
 763                 pNv->crtc_active[nv_crtc->head] = TRUE;
 764         } else {
 765                 pNv->crtc_active[nv_crtc->head] = FALSE;
 766         }
 767
 768 #if 0
 769         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 770         NVOutputPrivatePtr nv_output = output->driver_private;
 771         if (!nv_output->valid_ramdac & RAMDAC_1) {
 772                 /* Assumption we are ramdac 0, currently the same as the crtc */
 773                 xf86CrtcPtr crtc2 = nv_find_crtc_by_index(pScrn, 1);
 774                 xf86OutputPtr output2 = NVGetOutputFromCRTC(crtc2);
 775                 NVOutputPrivatePtr nv_output2 = output2->driver_private;
 776                 /* Let's force them to crtc 0 if we are inactive */
 777                 if (pNv->crtc_active[0]) {
 778                         if (nv_output2->valid_ramdac & RAMDAC_1)
 779                                 output2->possible_crtcs |= (1<<1);
 780                 } else {
 781                         output2->possible_crtcs &= ~(1<<1);
 782                 }
 783         }
 784 #endif
 785 }
 786
 787 static Bool
 788 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 789                      DisplayModePtr adjusted_mode)
 790 {
 791         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 792         ScrnInfoPtr pScrn = crtc->scrn;
 793         NVPtr pNv = NVPTR(pScrn);
 794         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
 795
 796         return TRUE;
 797 }
 798
 799 static void
 800 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
 801 {
 802         ScrnInfoPtr pScrn = crtc->scrn;
 803         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 804         NVCrtcRegPtr regp;
 805         NVPtr pNv = NVPTR(pScrn);
 806         int depth = pScrn->depth;
 807         unsigned int i;
 808
 809         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 810
 811         /*
 812         * compute correct Hsync & Vsync polarity
 813         */
 814         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 815                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 816
 817                 regp->MiscOutReg = 0x23;
 818                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 819                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 820         } else {
 821                 int VDisplay = mode->VDisplay;
 822                 if (mode->Flags & V_DBLSCAN)
 823                         VDisplay *= 2;
 824                 if (mode->VScan > 1)
 825                         VDisplay *= mode->VScan;
 826                 if (VDisplay < 400) {
 827                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 828                 } else if (VDisplay < 480) {
 829                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 830                 } else if (VDisplay < 768) {
 831                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 832                 } else {
 833                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 834                 }
 835         }
 836
 837         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 838
 839         /*
 840         * Time Sequencer
 841         */
 842         if (depth == 4) {
 843                 regp->Sequencer[0] = 0x02;
 844         } else {
 845                 regp->Sequencer[0] = 0x00;
 846         }
 847         /* 0x20 disables the sequencer */
 848         if (mode->Flags & V_CLKDIV2) {
 849                 regp->Sequencer[1] = 0x29;
 850         } else {
 851                 regp->Sequencer[1] = 0x21;
 852         }
 853         if (depth == 1) {
 854                 regp->Sequencer[2] = 1 << BIT_PLANE;
 855         } else {
 856                 regp->Sequencer[2] = 0x0F;
 857                 regp->Sequencer[3] = 0x00;                     /* Font select */
 858         }
 859         if (depth < 8) {
 860                 regp->Sequencer[4] = 0x06;                             /* Misc */
 861         } else {
 862                 regp->Sequencer[4] = 0x0E;                             /* Misc */
 863         }
 864
 865         /*
 866         * CRTC Controller
 867         */
 868         regp->CRTC[0]  = (mode->CrtcHTotal >> 3) - 5;
 869         regp->CRTC[1]  = (mode->CrtcHDisplay >> 3) - 1;
 870         regp->CRTC[2]  = (mode->CrtcHBlankStart >> 3) - 1;
 871         regp->CRTC[3]  = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
 872         i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
 873         if (i < 0x80) {
 874                 regp->CRTC[3] |= i;
 875         }
 876         regp->CRTC[4]  = (mode->CrtcHSyncStart >> 3);
 877         regp->CRTC[5]  = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
 878         | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
 879         regp->CRTC[6]  = (mode->CrtcVTotal - 2) & 0xFF;
 880         regp->CRTC[7]  = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
 881                         | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
 882                         | ((mode->CrtcVSyncStart & 0x100) >> 6)
 883                         | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
 884                         | 0x10
 885                         | (((mode->CrtcVTotal - 2) & 0x200)   >> 4)
 886                         | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
 887                         | ((mode->CrtcVSyncStart & 0x200) >> 2);
 888         regp->CRTC[8]  = 0x00;
 889         regp->CRTC[9]  = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
 890         if (mode->Flags & V_DBLSCAN) {
 891                 regp->CRTC[9] |= 0x80;
 892         }
 893         if (mode->VScan >= 32) {
 894                 regp->CRTC[9] |= 0x1F;
 895         } else if (mode->VScan > 1) {
 896                 regp->CRTC[9] |= mode->VScan - 1;
 897         }
 898         regp->CRTC[10] = 0x00;
 899         regp->CRTC[11] = 0x00;
 900         regp->CRTC[12] = 0x00;
 901         regp->CRTC[13] = 0x00;
 902         regp->CRTC[14] = 0x00;
 903         regp->CRTC[15] = 0x00;
 904         regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
 905         regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
 906         regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
 907         regp->CRTC[19] = mode->CrtcHDisplay >> 4;  /* just a guess */
 908         regp->CRTC[20] = 0x00;
 909         regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
 910         regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
 911         /* 0x80 enables the sequencer, we don't want that */
 912         if (depth < 8) {
 913                 regp->CRTC[23] = 0xE3 & ~0x80;
 914         } else {
 915                 regp->CRTC[23] = 0xC3 & ~0x80;
 916         }
 917         regp->CRTC[24] = 0xFF;
 918
 919         /*
 920         * Theory resumes here....
 921         */
 922
 923         /*
 924         * Graphics Display Controller
 925         */
 926         regp->Graphics[0] = 0x00;
 927         regp->Graphics[1] = 0x00;
 928         regp->Graphics[2] = 0x00;
 929         regp->Graphics[3] = 0x00;
 930         if (depth == 1) {
 931                 regp->Graphics[4] = BIT_PLANE;
 932                 regp->Graphics[5] = 0x00;
 933         } else {
 934                 regp->Graphics[4] = 0x00;
 935                 if (depth == 4) {
 936                         regp->Graphics[5] = 0x02;
 937                 } else {
 938                         regp->Graphics[5] = 0x40;
 939                 }
 940         }
 941         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
 942         regp->Graphics[7] = 0x0F;
 943         regp->Graphics[8] = 0xFF;
 944
 945         if (depth == 1) {
 946                 /* Initialise the Mono map according to which bit-plane gets used */
 947
 948                 Bool flipPixels = xf86GetFlipPixels();
 949
 950                 for (i=0; i<16; i++) {
 951                         if (((i & (1 << BIT_PLANE)) != 0) != flipPixels) {
 952                                 regp->Attribute[i] = WHITE_VALUE;
 953                         } else {
 954                                 regp->Attribute[i] = BLACK_VALUE;
 955                         }
 956                 }
 957
 958         } else {
 959                 regp->Attribute[0]  = 0x00; /* standard colormap translation */
 960                 regp->Attribute[1]  = 0x01;
 961                 regp->Attribute[2]  = 0x02;
 962                 regp->Attribute[3]  = 0x03;
 963                 regp->Attribute[4]  = 0x04;
 964                 regp->Attribute[5]  = 0x05;
 965                 regp->Attribute[6]  = 0x06;
 966                 regp->Attribute[7]  = 0x07;
 967                 regp->Attribute[8]  = 0x08;
 968                 regp->Attribute[9]  = 0x09;
 969                 regp->Attribute[10] = 0x0A;
 970                 regp->Attribute[11] = 0x0B;
 971                 regp->Attribute[12] = 0x0C;
 972                 regp->Attribute[13] = 0x0D;
 973                 regp->Attribute[14] = 0x0E;
 974                 regp->Attribute[15] = 0x0F;
 975                 if (depth == 4) {
 976                         regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
 977                 } else {
 978                         regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
 979                 }
 980                 if (depth > 4) {
 981                         regp->Attribute[17] = 0xff;
 982                 }
 983                 /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
 984         }
 985         regp->Attribute[18] = 0x0F;
 986         regp->Attribute[19] = 0x00;
 987         regp->Attribute[20] = 0x00;
 988 }
 989
 990 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
 991 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
 992
 993 /**
 994  * Sets up registers for the given mode/adjusted_mode pair.
 995  *
 996  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 997  *
 998  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 999  * be easily turned on/off after this.
1000  */
1001 static void
1002 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1003 {
1004         ScrnInfoPtr pScrn = crtc->scrn;
1005         NVPtr pNv = NVPTR(pScrn);
1006         NVRegPtr state = &pNv->ModeReg;
1007         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1008         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1009         NVFBLayout *pLayout = &pNv->CurrentLayout;
1010         NVCrtcRegPtr regp, savep;
1011         unsigned int i;
1012         uint32_t clock = adjusted_mode->Clock;
1013
1014         /* Happily borrowed from haiku driver, as an extra safety */
1015
1016         /* Make it multiples of 8 */
1017         mode->CrtcHDisplay &= ~7;
1018         mode->CrtcHSyncStart &= ~7;
1019         mode->CrtcHSyncEnd &= ~7;
1020         mode->CrtcHTotal &= ~7;
1021
1022         /* Horizontal stuff */
1023
1024         /* Time for some mode mangling */
1025         /* We only have 9 bits to store most of this information (mask 0x3f) */
1026         if (mode->CrtcHDisplay > MAX_H_VALUE(-2))
1027                 mode->CrtcHDisplay = MAX_H_VALUE(-2);
1028
1029         if (mode->CrtcHSyncStart > MAX_H_VALUE(-1))
1030                 mode->CrtcHSyncStart = MAX_H_VALUE(-1);
1031
1032         if  (mode->CrtcHSyncEnd > MAX_H_VALUE(0))
1033                 mode->CrtcHSyncEnd = MAX_H_VALUE(0);
1034
1035         if (mode->CrtcHTotal > MAX_H_VALUE(5))
1036                 mode->CrtcHTotal = MAX_H_VALUE(5);
1037
1038         /* Make room for a sync pulse if there is not enough room */
1039         if (mode->CrtcHTotal < mode->CrtcHSyncEnd + 0x50)
1040                 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x50;
1041
1042         /* Too large sync pulse? */
1043         if (mode->CrtcHTotal > mode->CrtcHSyncEnd + 0x3f8)
1044                 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x3f8;
1045
1046         /* Is the sync pulse outside the screen? */
1047         if (mode->CrtcHSyncEnd > mode->CrtcHTotal - 8)
1048                 mode->CrtcHSyncEnd = mode->CrtcHTotal - 8;
1049
1050         if (mode->CrtcHSyncStart < mode->CrtcHDisplay + 8)
1051                 mode->CrtcHSyncStart = mode->CrtcHDisplay + 8;
1052
1053         /* We've only got 5 bits to store the sync stuff */
1054         if (mode->CrtcHSyncEnd > mode->CrtcHSyncStart + (0x1f << 3))
1055                 mode->CrtcHSyncEnd = mode->CrtcHSyncStart + (0x1f << 3);
1056
1057         /* Vertical stuff */
1058
1059         /* We've only got 12 bits for this stuff */
1060         if (mode->CrtcVDisplay > MAX_V_VALUE(-2))
1061                 mode->CrtcVDisplay = MAX_V_VALUE(-2);
1062
1063         if (mode->CrtcVSyncStart > MAX_V_VALUE(-1))
1064                 mode->CrtcVSyncStart = MAX_V_VALUE(-1);
1065
1066         if  (mode->CrtcVSyncEnd > MAX_V_VALUE(0))
1067                 mode->CrtcVSyncEnd = MAX_V_VALUE(0);
1068
1069         if (mode->CrtcVTotal > MAX_V_VALUE(5))
1070                 mode->CrtcVTotal = MAX_V_VALUE(5);
1071
1072         /* Make room for a sync pulse if there is not enough room */
1073         if (mode->CrtcVTotal < mode->CrtcVSyncEnd + 0x3)
1074                 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0x3;
1075
1076         /* Too large sync pulse? */
1077         if (mode->CrtcVTotal > mode->CrtcVSyncEnd + 0xff)
1078                 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0xff;
1079
1080         /* Is the sync pulse outside the screen? */
1081         if (mode->CrtcVSyncEnd > mode->CrtcVTotal - 1)
1082                 mode->CrtcVSyncEnd = mode->CrtcVTotal - 1;
1083
1084         if (mode->CrtcVSyncStart < mode->CrtcVDisplay + 1)
1085                 mode->CrtcVSyncStart = mode->CrtcVDisplay + 1;
1086
1087         /* We've only got 4 bits to store the sync stuff */
1088         if (mode->CrtcVSyncEnd > mode->CrtcVSyncStart + (0x0f << 0))
1089                 mode->CrtcVSyncEnd = mode->CrtcVSyncStart + (0x0f << 0);
1090
1091         int horizDisplay        = (mode->CrtcHDisplay >> 3) - 1;
1092         int horizStart          = (mode->CrtcHSyncStart >> 3);
1093         /* The reason for this offset is completelt unknown, but important to keep analog screen alligned */
1094         int horizEnd            = (mode->CrtcHSyncEnd >> 3) + 4;
1095         int horizTotal          = (mode->CrtcHTotal >> 3) - 5;
1096         int horizBlankStart     = horizDisplay;
1097         int horizBlankEnd       = horizTotal + 4;
1098         int vertDisplay         = mode->CrtcVDisplay - 1;
1099         int vertStart           = mode->CrtcVSyncStart;
1100         int vertEnd             = mode->CrtcVSyncEnd;
1101         int vertTotal           = mode->CrtcVTotal - 2;
1102         int vertBlankStart      = vertDisplay;
1103         int vertBlankEnd        = vertTotal + 1;
1104         int lineComp            = mode->CrtcVDisplay;
1105
1106         Bool is_fp = FALSE;
1107
1108         xf86OutputPtr  output;
1109         NVOutputPrivatePtr nv_output;
1110         for (i = 0; i < xf86_config->num_output; i++) {
1111                 output = xf86_config->output[i];
1112                 nv_output = output->driver_private;
1113
1114                 if (output->crtc == crtc) {
1115                         if ((nv_output->type == OUTPUT_LVDS) ||
1116                                 (nv_output->type == OUTPUT_TMDS)) {
1117
1118                                 is_fp = TRUE;
1119                                 break;
1120                         }
1121                 }
1122         }
1123
1124         ErrorF("Mode clock: %d\n", clock);
1125
1126         ErrorF("crtc: Pre-sync workaround\n");
1127         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1128         if (is_fp) {
1129                 vertStart = vertTotal - 3;
1130                 vertEnd = vertTotal - 2;
1131                 vertBlankStart = vertStart;
1132                 horizStart = horizTotal - 5;
1133                 horizEnd = horizTotal - 2;
1134                 horizBlankEnd = horizTotal + 4;
1135                 if (pNv->overlayAdaptor) {
1136                         /* This reportedly works around Xv some overlay bandwidth problems*/
1137                         horizTotal += 2;
1138                 }
1139         }
1140         ErrorF("crtc: Post-sync workaround\n");
1141
1142         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1143         ErrorF("horizStart: 0x%X \n", horizStart);
1144         ErrorF("horizEnd: 0x%X \n", horizEnd);
1145         ErrorF("horizTotal: 0x%X \n", horizTotal);
1146         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1147         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1148         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1149         ErrorF("vertStart: 0x%X \n", vertStart);
1150         ErrorF("vertEnd: 0x%X \n", vertEnd);
1151         ErrorF("vertTotal: 0x%X \n", vertTotal);
1152         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1153         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1154
1155         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1156         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1157
1158         if(mode->Flags & V_INTERLACE)
1159                 vertTotal |= 1;
1160
1161         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1162         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1163         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1164         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1165                                 | SetBit(7);
1166         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1167         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1168                                 | SetBitField(horizEnd,4:0,4:0);
1169         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1170         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1171                                 | SetBitField(vertDisplay,8:8,1:1)
1172                                 | SetBitField(vertStart,8:8,2:2)
1173                                 | SetBitField(vertBlankStart,8:8,3:3)
1174                                 | SetBitField(lineComp,8:8,4:4)
1175                                 | SetBitField(vertTotal,9:9,5:5)
1176                                 | SetBitField(vertDisplay,9:9,6:6)
1177                                 | SetBitField(vertStart,9:9,7:7);
1178         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1179                                 | SetBitField(lineComp,9:9,6:6)
1180                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1181         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1182         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1183         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1184         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1185         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1186         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1187         /* Not an extended register */
1188         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = lineComp & 0xff;
1189
1190         regp->Attribute[0x10] = 0x01;
1191         /* Blob sets this for normal monitors as well */
1192         regp->Attribute[0x11] = 0x00;
1193
1194         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1195                                 | SetBitField(vertBlankStart,10:10,3:3)
1196                                 | SetBitField(vertStart,10:10,2:2)
1197                                 | SetBitField(vertDisplay,10:10,1:1)
1198                                 | SetBitField(vertTotal,10:10,0:0);
1199
1200         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1201                                 | SetBitField(horizDisplay,8:8,1:1)
1202                                 | SetBitField(horizBlankStart,8:8,2:2)
1203                                 | SetBitField(horizStart,8:8,3:3);
1204
1205         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1206                                 | SetBitField(vertDisplay,11:11,2:2)
1207                                 | SetBitField(vertStart,11:11,4:4)
1208                                 | SetBitField(vertBlankStart,11:11,6:6);
1209
1210         if(mode->Flags & V_INTERLACE) {
1211                 horizTotal = (horizTotal >> 1) & ~1;
1212                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1213                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1214         } else {
1215                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1216         }
1217
1218         /* bit2 = 0 -> fine pitched crtc granularity */
1219         /* The rest disables double buffering on CRTC access */
1220         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfb;
1221
1222         /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1223         if (nv_crtc->head == 0) {
1224                 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1225         }
1226
1227         if (is_fp) {
1228                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1229         }
1230
1231         /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1232         if (is_fp) {
1233                 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1234         } else {
1235                 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1236         }
1237
1238         /*
1239         * Initialize DAC palette.
1240         */
1241         if(pLayout->bitsPerPixel != 8 ) {
1242                 for (i = 0; i < 256; i++) {
1243                         regp->DAC[i*3]     = i;
1244                         regp->DAC[(i*3)+1] = i;
1245                         regp->DAC[(i*3)+2] = i;
1246                 }
1247         }
1248
1249         /*
1250         * Calculate the extended registers.
1251         */
1252
1253         if(pLayout->depth < 24) {
1254                 i = pLayout->depth;
1255         } else {
1256                 i = 32;
1257         }
1258
1259         if(pNv->Architecture >= NV_ARCH_10) {
1260                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1261         }
1262
1263         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1264         nv_crtc_calc_state_ext(crtc,
1265                                 i,
1266                                 pScrn->displayWidth,
1267                                 mode->CrtcHDisplay,
1268                                 mode->CrtcVDisplay,
1269                                 clock,
1270                                 mode->Flags);
1271
1272         /* Enable slaved mode */
1273         if (is_fp) {
1274                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1275         }
1276
1277         /* What is the meaning of this register? */
1278         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1279         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1];
1280
1281         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1282         /* But what are those special conditions? */
1283         if (pNv->Architecture <= NV_ARCH_30) {
1284                 if (is_fp) {
1285                         if(nv_crtc->head == 1) {
1286                                 regp->head |= NV_CRTC_FSEL_FPP1;
1287                         } else if (pNv->twoHeads) {
1288                                 regp->head |= NV_CRTC_FSEL_FPP2;
1289                         }
1290                 }
1291         }
1292
1293         /* In some situations I2C is also enabled on head 1, even when head 1 is not used */
1294         /* Seems to be in "crosswired" tmds situations as far as i can tell (only one known case) */
1295         if (nv_crtc->head == 0) {
1296                 regp->head |= NV_CRTC_FSEL_I2C;
1297                 if (pNv->overlayAdaptor) {
1298                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1299                 }
1300         }
1301
1302         regp->cursorConfig = 0x00000100;
1303         if(mode->Flags & V_DBLSCAN)
1304                 regp->cursorConfig |= (1 << 4);
1305         if(pNv->alphaCursor) {
1306                 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11) {
1307                         regp->cursorConfig |= 0x04011000;
1308                 } else {
1309                         regp->cursorConfig |= 0x14011000;
1310                 }
1311         } else {
1312                 regp->cursorConfig |= 0x02000000;
1313         }
1314
1315         /* Unblock some timings */
1316         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1317         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1318
1319         /* 0x20 seems to be enabled and 0x14 disabled */
1320         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1321
1322         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1323         /* 0x11 is LVDS? */
1324         if (is_fp) {
1325                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1326         } else {
1327                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1328         }
1329
1330         /* These values seem to vary */
1331         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1332
1333         /* 0x80 seems to be used very often, if not always */
1334         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1335
1336         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1337         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1338
1339         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1340         //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1341         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1342
1343         regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1344
1345         /* bit0: Seems to be mostly used on crtc1 */
1346         /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1347         /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1348         /* This is likely to be incomplete */
1349         /* This is a very strange register, changed very often by the blob */
1350         regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1351
1352         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1353         if (nv_crtc->head == 1) {
1354                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1355         } else {
1356                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1357         }
1358
1359         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1360         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1361
1362         regp->unk830 = mode->CrtcVDisplay - 3;
1363         regp->unk834 = mode->CrtcVDisplay - 1;
1364
1365         /* This is what the blob does */
1366         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1367
1368         /* Never ever modify gpio, unless you know very well what you're doing */
1369         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1370 }
1371
1372 /**
1373  * Sets up registers for the given mode/adjusted_mode pair.
1374  *
1375  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1376  *
1377  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1378  * be easily turned on/off after this.
1379  */
1380 static void
1381 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1382                  DisplayModePtr adjusted_mode,
1383                  int x, int y)
1384 {
1385         ScrnInfoPtr pScrn = crtc->scrn;
1386         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1387         NVPtr pNv = NVPTR(pScrn);
1388
1389         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1390
1391     xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1392     xf86PrintModeline(pScrn->scrnIndex, mode);
1393     NVCrtcSetOwner(crtc);
1394
1395     nv_crtc_mode_set_vga(crtc, mode);
1396     nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1397
1398     NVVgaProtect(crtc, TRUE);
1399     nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1400     nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1401     nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1402
1403     NVVgaProtect(crtc, FALSE);
1404     //    NVCrtcLockUnlock(crtc, 1);
1405
1406     NVCrtcSetBase(crtc, x, y);
1407
1408 #if X_BYTE_ORDER == X_BIG_ENDIAN
1409     /* turn on LFB swapping */
1410     {
1411         unsigned char tmp;
1412
1413         tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1414         tmp |= (1 << 7);
1415         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1416     }
1417 #endif
1418
1419 }
1420
1421 void nv_crtc_save(xf86CrtcPtr crtc)
1422 {
1423     ScrnInfoPtr pScrn = crtc->scrn;
1424     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1425     NVPtr pNv = NVPTR(pScrn);
1426
1427         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1428
1429     NVCrtcSetOwner(crtc);
1430     nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1431     nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1432     nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1433 }
1434
1435 void nv_crtc_restore(xf86CrtcPtr crtc)
1436 {
1437     ScrnInfoPtr pScrn = crtc->scrn;
1438     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1439     NVPtr pNv = NVPTR(pScrn);
1440
1441         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1442
1443     NVCrtcSetOwner(crtc);
1444     nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1445     nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1446     nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1447     nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1448 }
1449
1450 void nv_crtc_prepare(xf86CrtcPtr crtc)
1451 {
1452         ScrnInfoPtr pScrn = crtc->scrn;
1453         NVPtr pNv = NVPTR(pScrn);
1454         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1455
1456         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1457
1458         crtc->funcs->dpms(crtc, DPMSModeOff);
1459
1460         /* Sync the engine before adjust mode */
1461         if (pNv->EXADriverPtr) {
1462                 exaMarkSync(pScrn->pScreen);
1463                 exaWaitSync(pScrn->pScreen);
1464         }
1465 }
1466
1467 void nv_crtc_commit(xf86CrtcPtr crtc)
1468 {
1469         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1470         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1471         ScrnInfoPtr pScrn = crtc->scrn;
1472         NVPtr pNv = NVPTR(pScrn);
1473
1474         crtc->funcs->dpms (crtc, DPMSModeOn);
1475         if (crtc->scrn->pScreen != NULL)
1476                 xf86_reload_cursors (crtc->scrn->pScreen);
1477 }
1478
1479 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1480 {
1481         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1482         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1483
1484         return FALSE;
1485 }
1486
1487 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1488 {
1489         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1490         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1491 }
1492
1493 /* NV04-NV10 doesn't support alpha cursors */
1494 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1495         .dpms = nv_crtc_dpms,
1496         .save = nv_crtc_save, /* XXX */
1497         .restore = nv_crtc_restore, /* XXX */
1498         .mode_fixup = nv_crtc_mode_fixup,
1499         .mode_set = nv_crtc_mode_set,
1500         .prepare = nv_crtc_prepare,
1501         .commit = nv_crtc_commit,
1502         .destroy = NULL, /* XXX */
1503         .lock = nv_crtc_lock,
1504         .unlock = nv_crtc_unlock,
1505         .set_cursor_colors = nv_crtc_set_cursor_colors,
1506         .set_cursor_position = nv_crtc_set_cursor_position,
1507         .show_cursor = nv_crtc_show_cursor,
1508         .hide_cursor = nv_crtc_hide_cursor,
1509         .load_cursor_image = nv_crtc_load_cursor_image,
1510 };
1511
1512 /* NV11 and up has support for alpha cursors. */
1513 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1514 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1515         .dpms = nv_crtc_dpms,
1516         .save = nv_crtc_save, /* XXX */
1517         .restore = nv_crtc_restore, /* XXX */
1518         .mode_fixup = nv_crtc_mode_fixup,
1519         .mode_set = nv_crtc_mode_set,
1520         .prepare = nv_crtc_prepare,
1521         .commit = nv_crtc_commit,
1522         .destroy = NULL, /* XXX */
1523         .lock = nv_crtc_lock,
1524         .unlock = nv_crtc_unlock,
1525         .set_cursor_colors = nv_crtc_set_cursor_colors,
1526         .set_cursor_position = nv_crtc_set_cursor_position,
1527         .show_cursor = nv_crtc_show_cursor,
1528         .hide_cursor = nv_crtc_hide_cursor,
1529         .load_cursor_argb = nv_crtc_load_cursor_argb,
1530 };
1531
1532
1533 void
1534 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1535 {
1536         NVPtr pNv = NVPTR(pScrn);
1537         xf86CrtcPtr crtc;
1538         NVCrtcPrivatePtr nv_crtc;
1539
1540         if (pNv->NVArch >= 0x11) {
1541                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
1542         } else {
1543                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
1544         }
1545         if (crtc == NULL)
1546                 return;
1547
1548         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1549         nv_crtc->crtc = crtc_num;
1550         nv_crtc->head = crtc_num;
1551
1552         crtc->driver_private = nv_crtc;
1553
1554         NVCrtcLockUnlock(crtc, 0);
1555 }
1556
1557 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1558 {
1559     ScrnInfoPtr pScrn = crtc->scrn;
1560     NVPtr pNv = NVPTR(pScrn);
1561     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1562     int i, j;
1563     CARD32 temp;
1564     NVCrtcRegPtr regp;
1565
1566     regp = &state->crtc_reg[nv_crtc->head];
1567
1568     NVWriteMiscOut(crtc, regp->MiscOutReg);
1569
1570     for (i = 1; i < 5; i++)
1571       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
1572
1573     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1574     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
1575
1576     for (i = 0; i < 25; i++)
1577       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
1578
1579     for (i = 0; i < 9; i++)
1580       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
1581
1582     NVEnablePalette(crtc);
1583     for (i = 0; i < 21; i++)
1584       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
1585     NVDisablePalette(crtc);
1586
1587 }
1588
1589 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
1590 {
1591   /* TODO - implement this properly */
1592   ScrnInfoPtr pScrn = crtc->scrn;
1593   NVPtr pNv = NVPTR(pScrn);
1594
1595   if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
1596     volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1597     nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1598   }
1599
1600 }
1601 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1602 {
1603     ScrnInfoPtr pScrn = crtc->scrn;
1604     NVPtr pNv = NVPTR(pScrn);
1605     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1606     int i, j;
1607     CARD32 temp;
1608     NVCrtcRegPtr regp;
1609
1610     regp = &state->crtc_reg[nv_crtc->head];
1611
1612     if(pNv->Architecture >= NV_ARCH_10) {
1613         if(pNv->twoHeads) {
1614            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
1615         }
1616         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1617         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1618         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1619         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1620         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1621         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1622         nvWriteMC(pNv, 0x1588, 0);
1623
1624         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, 0xff);
1625         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1626         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1627         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
1628         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
1629         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
1630         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
1631         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
1632
1633         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1634         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1635
1636         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1637         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1638         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
1639         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1640         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1641         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
1642         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
1643         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
1644         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1645         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1646     }
1647
1648     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1649     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1650     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1651     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1652     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1653     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1654     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1655     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1656     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1657     if(pNv->Architecture >= NV_ARCH_30) {
1658       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1659     }
1660
1661     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1662     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1663     nv_crtc_fix_nv40_hw_cursor(crtc);
1664     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1665     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1666
1667     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
1668     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1669
1670     pNv->CurrentState = state;
1671 }
1672
1673 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1674 {
1675     ScrnInfoPtr pScrn = crtc->scrn;
1676     NVPtr pNv = NVPTR(pScrn);
1677     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1678     int i;
1679     NVCrtcRegPtr regp;
1680
1681     regp = &state->crtc_reg[nv_crtc->head];
1682
1683     regp->MiscOutReg = NVReadMiscOut(crtc);
1684
1685     for (i = 0; i < 25; i++)
1686         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
1687
1688     NVEnablePalette(crtc);
1689     for (i = 0; i < 21; i++)
1690         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
1691     NVDisablePalette(crtc);
1692
1693     for (i = 0; i < 9; i++)
1694         regp->Graphics[i] = NVReadVgaGr(crtc, i);
1695
1696     for (i = 1; i < 5; i++)
1697         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
1698
1699 }
1700
1701 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1702 {
1703     ScrnInfoPtr pScrn = crtc->scrn;
1704     NVPtr pNv = NVPTR(pScrn);
1705     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1706     NVCrtcRegPtr regp;
1707     int i;
1708
1709     regp = &state->crtc_reg[nv_crtc->head];
1710
1711     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
1712     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
1713     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
1714     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
1715     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
1716     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
1717     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
1718
1719     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
1720     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
1721     if(pNv->Architecture >= NV_ARCH_30) {
1722          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
1723     }
1724     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
1725     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
1726     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
1727     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
1728
1729     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
1730     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
1731     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
1732     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
1733     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
1734
1735     if(pNv->Architecture >= NV_ARCH_10) {
1736         if(pNv->twoHeads) {
1737            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
1738            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
1739         }
1740         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
1741
1742         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
1743
1744         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
1745         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
1746         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
1747         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
1748         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
1749         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
1750         regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
1751         regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
1752         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
1753         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
1754         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
1755         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
1756     }
1757 }
1758
1759 void
1760 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
1761 {
1762         ScrnInfoPtr pScrn = crtc->scrn;
1763         NVPtr pNv = NVPTR(pScrn);
1764         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1765         NVFBLayout *pLayout = &pNv->CurrentLayout;
1766         CARD32 start = 0;
1767
1768         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
1769
1770         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
1771         start += pNv->FB->offset;
1772
1773         /* 30 bits addresses in 32 bits according to haiku */
1774         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
1775
1776         /* set NV4/NV10 byte adress: (bit0 - 1) */
1777         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
1778
1779         crtc->x = x;
1780         crtc->y = y;
1781 }
1782
1783 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
1784 {
1785   ScrnInfoPtr pScrn = crtc->scrn;
1786   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1787   NVPtr pNv = NVPTR(pScrn);
1788   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1789
1790   NV_WR08(pDACReg, VGA_DAC_MASK, value);
1791 }
1792
1793 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
1794 {
1795   ScrnInfoPtr pScrn = crtc->scrn;
1796   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1797   NVPtr pNv = NVPTR(pScrn);
1798   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1799
1800   return NV_RD08(pDACReg, VGA_DAC_MASK);
1801 }
1802
1803 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
1804 {
1805   ScrnInfoPtr pScrn = crtc->scrn;
1806   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1807   NVPtr pNv = NVPTR(pScrn);
1808   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1809
1810   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
1811 }
1812
1813 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
1814 {
1815   ScrnInfoPtr pScrn = crtc->scrn;
1816   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1817   NVPtr pNv = NVPTR(pScrn);
1818   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1819
1820   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
1821 }
1822
1823 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
1824 {
1825   ScrnInfoPtr pScrn = crtc->scrn;
1826   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1827   NVPtr pNv = NVPTR(pScrn);
1828   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1829
1830   NV_WR08(pDACReg, VGA_DAC_DATA, value);
1831 }
1832
1833 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
1834 {
1835   ScrnInfoPtr pScrn = crtc->scrn;
1836   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1837   NVPtr pNv = NVPTR(pScrn);
1838   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1839
1840   return NV_RD08(pDACReg, VGA_DAC_DATA);
1841 }
1842
1843 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
1844 {
1845   int i;
1846   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1847   NVCrtcRegPtr regp;
1848   ScrnInfoPtr pScrn = crtc->scrn;
1849   NVPtr pNv = NVPTR(pScrn);
1850
1851   regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1852
1853   NVCrtcSetOwner(crtc);
1854   NVCrtcWriteDacMask(crtc, 0xff);
1855   NVCrtcWriteDacWriteAddr(crtc, 0x00);
1856
1857   for (i = 0; i<768; i++) {
1858     NVCrtcWriteDacData(crtc, regp->DAC[i]);
1859   }
1860   NVDisablePalette(crtc);
1861 }
1862
1863 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
1864 {
1865     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1866     unsigned char scrn;
1867
1868     NVCrtcSetOwner(crtc);
1869
1870     scrn = NVReadVgaSeq(crtc, 0x01);
1871     if (on) {
1872         scrn &= ~0x20;
1873     } else {
1874         scrn |= 0x20;
1875     }
1876
1877     NVVgaSeqReset(crtc, TRUE);
1878     NVWriteVgaSeq(crtc, 0x01, scrn);
1879     NVVgaSeqReset(crtc, FALSE);
1880 }
1881
1882 #endif /* ENABLE_RANDR12 */
1883
1884 /*************************************************************************** \
1885 |*                                                                           *|
1886 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
1887 |*                                                                           *|
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1889 |*     international laws.  Users and possessors of this source code are     *|
1890 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
1891 |*     use this code in individual and commercial software.                  *|
1892 |*                                                                           *|
1893 |*     Any use of this source code must include,  in the user documenta-     *|
1894 |*     tion and  internal comments to the code,  notices to the end user     *|
1895 |*     as follows:                                                           *|
1896 |*                                                                           *|
1897 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
1898 |*                                                                           *|
1899 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
1900 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
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1907 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
1908 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
1909 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
1910 |*                                                                           *|
1911 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
1912 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
1913 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
1914 |*     computer  software  documentation,"  as such  terms  are  used in     *|
1915 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
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1917 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
1918 |*     all U.S. Government End Users  acquire the source code  with only     *|
1919 |*     those rights set forth herein.                                        *|
1920 |*                                                                           *|
1921  \***************************************************************************/