2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
41 #include "mipointer.h"
42 #include "windowstr.h"
44 #include <X11/extensions/render.h>
47 #include "nv_include.h"
51 #define CRTC_INDEX 0x3d4
52 #define CRTC_DATA 0x3d5
53 #define CRTC_IN_STAT_1 0x3da
55 #define WHITE_VALUE 0x3F
56 #define BLACK_VALUE 0x00
57 #define OVERSCAN_VALUE 0x01
59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
66 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
68 ScrnInfoPtr pScrn = crtc->scrn;
69 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
70 NVPtr pNv = NVPTR(pScrn);
72 /* Only NV4x have two pvio ranges */
73 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
74 return NV_RD08(pNv->PVIO1, address);
76 return NV_RD08(pNv->PVIO0, address);
80 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
82 ScrnInfoPtr pScrn = crtc->scrn;
83 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
84 NVPtr pNv = NVPTR(pScrn);
86 /* Only NV4x have two pvio ranges */
87 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
88 NV_WR08(pNv->PVIO1, address, value);
90 NV_WR08(pNv->PVIO0, address, value);
94 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
96 #ifdef NOUVEAU_MODESET_TRACE
97 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
98 ErrorF("NVWriteMiscOut: value: 0x%X head: %d\n", value, nv_crtc->head);
100 NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
103 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
105 return NVReadPVIO(crtc, VGA_MISC_OUT_R);
108 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
110 volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
112 #ifdef NOUVEAU_MODESET_TRACE
113 ErrorF("NVWriteVGA: index: 0x%X data: 0x%X head: %d\n", index, value, head);
116 NV_WR08(pCRTCReg, CRTC_INDEX, index);
117 NV_WR08(pCRTCReg, CRTC_DATA, value);
120 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
122 volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
124 NV_WR08(pCRTCReg, CRTC_INDEX, index);
125 return NV_RD08(pCRTCReg, CRTC_DATA);
128 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
129 * I suspect they in fact do nothing, but are merely a way to carry useful
130 * per-head variables around
134 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
135 * 0x02 dcb entry's "or" value (or 00 for inactive)
136 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
137 * 0x08 or 0x09 pxclk in MHz
138 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT strap
139 * high nibble for xlat strap value
142 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
144 NVWriteVGA(pNv, head, 0x57, index);
145 NVWriteVGA(pNv, head, 0x58, value);
148 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
150 NVWriteVGA(pNv, head, 0x57, index);
151 return NVReadVGA(pNv, head, 0x58);
154 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
156 ScrnInfoPtr pScrn = crtc->scrn;
157 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
158 NVPtr pNv = NVPTR(pScrn);
160 NVWriteVGA(pNv, nv_crtc->head, index, value);
163 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
165 ScrnInfoPtr pScrn = crtc->scrn;
166 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
167 NVPtr pNv = NVPTR(pScrn);
169 return NVReadVGA(pNv, nv_crtc->head, index);
172 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
174 #ifdef NOUVEAU_MODESET_TRACE
175 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
176 ErrorF("NVWriteVgaSeq: index: 0x%X value: 0x%x head %d\n", index, value, nv_crtc->head);
178 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
179 NVWritePVIO(crtc, VGA_SEQ_DATA, value);
182 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
184 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
185 return NVReadPVIO(crtc, VGA_SEQ_DATA);
188 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
190 #ifdef NOUVEAU_MODESET_TRACE
191 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
192 ErrorF("NVWriteVgaGr: index: 0x%X value: 0x%x head %d\n", index, value, nv_crtc->head);
194 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
195 NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
198 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
200 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
201 return NVReadPVIO(crtc, VGA_GRAPH_DATA);
205 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
207 ScrnInfoPtr pScrn = crtc->scrn;
208 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
209 NVPtr pNv = NVPTR(pScrn);
210 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
212 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
213 if (nv_crtc->paletteEnabled)
217 #ifdef NOUVEAU_MODESET_TRACE
218 ErrorF("NVWriteVgaAttr: index: 0x%X value: 0x%X head: %d\n", index, value, nv_crtc->head);
220 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
221 NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
224 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
226 ScrnInfoPtr pScrn = crtc->scrn;
227 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
228 NVPtr pNv = NVPTR(pScrn);
229 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
231 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
232 if (nv_crtc->paletteEnabled)
236 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
237 return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
240 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
242 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
243 ScrnInfoPtr pScrn = crtc->scrn;
244 NVPtr pNv = NVPTR(pScrn);
245 /* Non standard beheaviour required by NV11 */
247 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
248 ErrorF("pre-Owner: 0x%X\n", owner);
250 uint32_t pbus84 = nvReadMC(pNv, 0x1084);
251 ErrorF("pbus84: 0x%X\n", pbus84);
253 ErrorF("pbus84: 0x%X\n", pbus84);
254 nvWriteMC(pNv, 0x1084, pbus84);
256 /* The blob never writes owner to pcio1, so should we */
257 if (pNv->NVArch == 0x11) {
258 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
260 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
261 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
262 ErrorF("post-Owner: 0x%X\n", owner);
264 ErrorF("pNv pointer is NULL\n");
269 NVEnablePalette(xf86CrtcPtr crtc)
271 ScrnInfoPtr pScrn = crtc->scrn;
272 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
273 NVPtr pNv = NVPTR(pScrn);
274 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
276 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
277 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
278 nv_crtc->paletteEnabled = TRUE;
282 NVDisablePalette(xf86CrtcPtr crtc)
284 ScrnInfoPtr pScrn = crtc->scrn;
285 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
286 NVPtr pNv = NVPTR(pScrn);
287 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
289 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
290 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
291 nv_crtc->paletteEnabled = FALSE;
294 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
296 ScrnInfoPtr pScrn = crtc->scrn;
297 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
298 NVPtr pNv = NVPTR(pScrn);
299 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
301 NV_WR08(pCRTCReg, reg, value);
304 /* perform a sequencer reset */
305 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
308 NVWriteVgaSeq(crtc, 0x00, 0x1);
310 NVWriteVgaSeq(crtc, 0x00, 0x3);
313 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
318 tmp = NVReadVgaSeq(crtc, 0x1);
319 NVVgaSeqReset(crtc, TRUE);
320 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
322 NVEnablePalette(crtc);
325 * Reenable sequencer, then turn on screen.
327 tmp = NVReadVgaSeq(crtc, 0x1);
328 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
329 NVVgaSeqReset(crtc, FALSE);
331 NVDisablePalette(crtc);
335 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
337 NVPtr pNv = NVPTR(crtc->scrn);
341 NVCrtcSetOwner(crtc);
343 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
344 cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
345 if (Lock) cr11 |= 0x80;
347 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
351 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
353 ScrnInfoPtr pScrn = crtc->scrn;
354 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
356 for (i = 0; i < xf86_config->num_output; i++) {
357 xf86OutputPtr output = xf86_config->output[i];
359 if (output->crtc == crtc) {
368 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
370 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
373 for (i = 0; i < xf86_config->num_crtc; i++) {
374 xf86CrtcPtr crtc = xf86_config->crtc[i];
375 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
376 if (nv_crtc->head == index)
384 * Calculate the Video Clock parameters for the PLL.
386 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
389 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
391 uint32_t clock, M, N, P;
392 uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
393 uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
395 uint32_t refClk = pNv->CrystalFreqKHz;
398 minVCOInputFreq = pll_lim->vco1.min_inputfreq;
399 minVCOFreq = pll_lim->vco1.minfreq;
400 maxVCOFreq = pll_lim->vco1.maxfreq;
401 minM = pll_lim->vco1.min_m;
402 maxM = pll_lim->vco1.max_m;
403 minN = pll_lim->vco1.min_n;
404 maxN = pll_lim->vco1.max_n;
408 /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
409 / Choose a post divider in such a way to achieve this.
410 / The G8x nv driver does something similar but they they derive a minP and maxP. That
411 / doesn't seem required as you get so many matching clocks that you don't enter a second
412 / iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
413 / some rare corner cases.
415 for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
420 /* Calculate the m and n values. There are a lot of values which give the same speed;
421 / We choose the speed for which the difference with the request speed is as small as possible.
423 for (M=minM; M<=maxM; M++)
425 /* The VCO has a minimum input frequency */
426 if ((refClk/M) < minVCOInputFreq)
429 for (N=minN; N<=maxN; N++)
431 /* Calculate the frequency generated by VCO1 */
432 clock = (int)(refClk * N / (float)M);
434 /* Verify if the clock lies within the output limits of VCO1 */
435 if (clock < minVCOFreq)
437 else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
441 delta = abs((int)(clockIn - clock));
442 /* When the difference is 0 or less than .5% accept the speed */
443 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
451 /* When the new difference is smaller than the old one, use this one */
452 if (delta < bestDelta)
464 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
466 uint32_t clock1, clock2, M, M2, N, N2, P;
467 uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
468 uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
469 uint32_t VCO2Freq, maxClock;
470 uint32_t refClk = pNv->CrystalFreqKHz;
473 minVCOInputFreq = pll_lim->vco1.min_inputfreq;
474 minVCOFreq = pll_lim->vco1.minfreq;
475 maxVCOFreq = pll_lim->vco1.maxfreq;
476 minM = pll_lim->vco1.min_m;
477 maxM = pll_lim->vco1.max_m;
478 minN = pll_lim->vco1.min_n;
479 maxN = pll_lim->vco1.max_n;
481 minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
482 maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
483 minVCO2Freq = pll_lim->vco2.minfreq;
484 maxVCO2Freq = pll_lim->vco2.maxfreq;
485 minM2 = pll_lim->vco2.min_m;
486 maxM2 = pll_lim->vco2.max_m;
487 minN2 = pll_lim->vco2.min_n;
488 maxN2 = pll_lim->vco2.max_n;
492 maxClock = maxVCO2Freq;
493 /* If the requested clock is behind the bios limits, try it anyway */
494 if (clockIn > maxVCO2Freq)
495 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
497 /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
498 / Choose a post divider in such a way to achieve this.
499 / The G8x nv driver does something similar but they they derive a minP and maxP. That
500 / doesn't seem required as you get so many matching clocks that you don't enter a second
501 / iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
502 / some rare corner cases.
504 for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
509 /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
510 / and a cascade mode of two VCOs. This second mode is in general used for relatively high
511 / frequencies. The loop below calculates the divider and multiplier ratios for the cascade
512 / mode. The code takes into account limits defined in the video bios.
514 for (M=minM; M<=maxM; M++)
516 /* The VCO has a minimum input frequency */
517 if ((refClk/M) < minVCOInputFreq)
520 for (N=minN; N<=maxN; N++)
522 /* Calculate the frequency generated by VCO1 */
523 clock1 = (int)(refClk * N / (float)M);
524 /* Verify if the clock lies within the output limits of VCO1 */
525 if ( (clock1 < minVCOFreq) )
527 else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
530 for (M2=minM2; M2<=maxM2; M2++)
532 /* The clock fed to the second VCO needs to lie within a certain input range */
533 if (clock1 / M2 < minVCO2InputFreq)
535 else if (clock1 / M2 > maxVCO2InputFreq)
538 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
539 if( (N2 < minN2) || (N2 > maxN2) )
542 /* The clock before being fed to the post-divider needs to lie within a certain range.
543 / Further there are some limits on N2/M2.
545 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
546 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
549 /* The post-divider delays the 'high' clock to create a low clock if requested.
550 / This post-divider exists because the VCOs can only generate frequencies within
551 / a limited frequency range. This range has been tuned to lie around half of its max
552 / input frequency. It tries to calculate all clocks (including lower ones) around this
553 / 'center' frequency.
556 delta = abs((int)(clockIn - clock2));
558 /* When the difference is 0 or less than .5% accept the speed */
559 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
569 /* When the new difference is smaller than the old one, use this one */
570 if (delta < bestDelta)
584 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
586 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
587 /* They are only valid for NV4x, appearantly reordered for NV5x */
588 /* gpu pll: 0x4000 + 0x4004
589 * unknown pll: 0x4008 + 0x400c
590 * vpll1: 0x4010 + 0x4014
591 * vpll2: 0x4018 + 0x401c
592 * unknown pll: 0x4020 + 0x4024
593 * unknown pll: 0x4038 + 0x403c
594 * Some of the unknown's are probably memory pll's.
595 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
596 * 1 and 2 refer to the registers of each pair. There is only one post divider.
597 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
598 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
599 * bit8: A switch that turns of the second divider and multiplier off.
600 * bit12: Also a switch, i haven't seen it yet.
601 * bit16-19: p-divider
602 * but 28-31: Something related to the mode that is used (see bit8).
603 * 2) bit0-7: m-divider (a)
604 * bit8-15: n-multiplier (a)
605 * bit16-23: m-divider (b)
606 * bit24-31: n-multiplier (b)
609 /* Modifying the gpu pll for example requires:
610 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
611 * This is not needed for the vpll's which have their own bits.
617 uint32_t requested_clock,
618 uint32_t *given_clock,
626 NVPtr pNv = NVPTR(pScrn);
627 struct pll_lims pll_lim;
628 /* We have 2 mulitpliers, 2 dividers and one post divider */
629 /* Note that p is only 3 bits */
630 uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
631 uint32_t special_bits = 0;
634 if (!get_pll_limits_plltype(pScrn, VPLL1, &pll_lim))
637 if (!get_pll_limits_plltype(pScrn, VPLL2, &pll_lim))
640 if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
642 /* Turn the second set of divider and multiplier off */
643 /* Bogus data, the same nvidia uses */
646 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
647 } else { /* dual VCO */
649 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
652 /* Are this all (relevant) G70 cards? */
653 if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
654 /* This is a big guess, but should be reasonable until we can narrow it down. */
662 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
663 *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
664 /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
665 *pll_b = NV31_RAMDAC_ENABLE_VCO2 | (n2_best << 8) | (m2_best << 0);
669 *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
671 *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
675 *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
677 *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
682 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
684 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
688 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
690 state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
691 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
692 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
693 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
694 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
695 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
696 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
697 state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
700 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
702 ScrnInfoPtr pScrn = crtc->scrn;
703 NVPtr pNv = NVPTR(pScrn);
704 uint32_t fp_debug_0[2];
706 fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
707 fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
709 /* The TMDS_PLL switch is on the actual ramdac */
710 if (state->crosswired) {
713 ErrorF("Crosswired pll state load\n");
719 if (state->vpll2_b && state->vpll_changed[1]) {
720 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
721 fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
723 /* Wait for the situation to stabilise */
726 uint32_t reg_c040 = pNv->misc_info.reg_c040;
727 /* for vpll2 change bits 18 and 19 are disabled */
728 reg_c040 &= ~(0x3 << 18);
729 nvWriteMC(pNv, 0xc040, reg_c040);
731 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
732 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
734 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
735 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
737 ErrorF("writing pllsel %08X\n", state->pllsel);
738 /* Don't turn vpll1 off. */
739 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
741 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
742 ErrorF("writing reg580 %08X\n", state->reg580);
744 /* We need to wait a while */
746 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
748 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
750 /* Wait for the situation to stabilise */
754 if (state->vpll1_b && state->vpll_changed[0]) {
755 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
756 fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
758 /* Wait for the situation to stabilise */
761 uint32_t reg_c040 = pNv->misc_info.reg_c040;
762 /* for vpll2 change bits 16 and 17 are disabled */
763 reg_c040 &= ~(0x3 << 16);
764 nvWriteMC(pNv, 0xc040, reg_c040);
766 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
767 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
769 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
770 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
772 ErrorF("writing pllsel %08X\n", state->pllsel);
773 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
775 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
776 ErrorF("writing reg580 %08X\n", state->reg580);
778 /* We need to wait a while */
780 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
782 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
784 /* Wait for the situation to stabilise */
788 ErrorF("writing sel_clk %08X\n", state->sel_clk);
789 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
791 ErrorF("writing reg594 %08X\n", state->reg594);
792 nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
794 /* All clocks have been set at this point. */
795 state->vpll_changed[0] = FALSE;
796 state->vpll_changed[1] = FALSE;
799 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
801 state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
803 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
805 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
806 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
807 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
809 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
810 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
814 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
816 /* This sequence is important, the NV28 is very sensitive in this area. */
817 /* Keep pllsel last and sel_clk first. */
818 ErrorF("writing sel_clk %08X\n", state->sel_clk);
819 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
821 if (state->vpll2_a && state->vpll_changed[1]) {
823 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
824 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
826 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
827 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
828 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
832 if (state->vpll1_a && state->vpll_changed[0]) {
833 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
834 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
835 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
836 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
837 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
841 ErrorF("writing pllsel %08X\n", state->pllsel);
842 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
844 /* All clocks have been set at this point. */
845 state->vpll_changed[0] = FALSE;
846 state->vpll_changed[1] = FALSE;
849 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
850 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
852 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
855 * Calculate extended mode parameters (SVGA) and save in a
856 * mode state structure.
857 * State is not specific to a single crtc, but shared.
859 void nv_crtc_calc_state_ext(
863 int DisplayWidth, /* Does this change after setting the mode? */
870 ScrnInfoPtr pScrn = crtc->scrn;
871 uint32_t pixelDepth, VClk = 0;
872 uint32_t CursorStart;
873 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
874 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
876 NVPtr pNv = NVPTR(pScrn);
877 RIVA_HW_STATE *state;
878 int num_crtc_enabled, i;
879 uint32_t old_clock_a = 0, old_clock_b = 0;
881 state = &pNv->ModeReg;
883 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
885 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
886 NVOutputPrivatePtr nv_output = NULL;
889 nv_output = output->driver_private;
890 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
894 /* Store old clock. */
895 if (nv_crtc->head == 1) {
896 old_clock_a = state->vpll2_a;
897 old_clock_b = state->vpll2_b;
899 old_clock_a = state->vpll1_a;
900 old_clock_b = state->vpll1_b;
904 * Extended RIVA registers.
906 /* This is pitch related, not mode related. */
907 pixelDepth = (bpp + 1)/8;
908 if (pNv->Architecture == NV_ARCH_40) {
909 /* Does register 0x580 already have a value? */
910 if (!state->reg580) {
911 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
913 if (nv_crtc->head == 1) {
914 CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
916 CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
918 } else if (pNv->twoStagePLL) {
920 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
921 if (pNv->NVArch == 0x30) {
922 /* See nvregisters.xml for details. */
923 state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
925 state->pll = log2P << 16 | NM1;
926 state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
930 VClk = getMNP_single(pScrn, dotClock, &NM, &log2P);
931 state->pll = log2P << 16 | NM;
934 if (pNv->Architecture < NV_ARCH_40) {
935 if (nv_crtc->head == 1) {
936 state->vpll2_a = state->pll;
937 state->vpll2_b = state->pllB;
939 state->vpll1_a = state->pll;
940 state->vpll1_b = state->pllB;
944 /* always reset vpll, just to be sure. */
945 state->vpll_changed[nv_crtc->head] = TRUE;
947 switch (pNv->Architecture) {
949 nv4UpdateArbitrationSettings(VClk,
951 &(state->arbitration0),
952 &(state->arbitration1),
954 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
955 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
956 if (flags & V_DBLSCAN)
957 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
958 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
959 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
960 state->config = 0x00001114;
961 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
967 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
968 ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
969 state->arbitration0 = 128;
970 state->arbitration1 = 0x0480;
971 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
972 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
973 nForceUpdateArbitrationSettings(VClk,
975 &(state->arbitration0),
976 &(state->arbitration1),
978 } else if (pNv->Architecture < NV_ARCH_30) {
979 nv10UpdateArbitrationSettings(VClk,
981 &(state->arbitration0),
982 &(state->arbitration1),
985 nv30UpdateArbitrationSettings(pNv,
986 &(state->arbitration0),
987 &(state->arbitration1));
990 if (nv_crtc->head == 1) {
991 CursorStart = pNv->Cursor2->offset;
993 CursorStart = pNv->Cursor->offset;
996 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
997 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
998 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
999 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1001 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1002 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1003 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1006 if (flags & V_DBLSCAN)
1007 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1009 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1010 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1014 if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* is this also true of 720x400 consoles? */
1016 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = 0xBD;
1018 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = 0x3D; /* Why the difference? */
1022 /* okay do we have 2 CRTCs running ? */
1023 num_crtc_enabled = 0;
1024 for (i = 0; i < xf86_config->num_crtc; i++) {
1025 if (xf86_config->crtc[i]->enabled) {
1030 ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1032 /* The main stuff seems to be valid for NV3x also. */
1033 if (pNv->Architecture >= NV_ARCH_30) {
1034 /* This register is only used on the primary ramdac */
1035 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1037 if (!state->sel_clk)
1038 state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1040 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1041 /* Only wipe when are a relevant (digital) output. */
1042 state->sel_clk &= ~(0xf << 16);
1043 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1044 /* Even with two dvi, this should not conflict. */
1045 if (crossed_clocks) {
1046 state->sel_clk |= (0x1 << 16);
1048 state->sel_clk |= (0x4 << 16);
1052 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1053 * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1054 * This is all based on default settings found in mmio-traces.
1055 * The blob never changes these, as it doesn't run unusual output configurations.
1056 * It seems to prefer situations that avoid changing these bits (for a good reason?).
1057 * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1062 * bit 0 NVClk spread spectrum on/off
1063 * bit 2 MemClk spread spectrum on/off
1064 * bit 4 PixClk1 spread spectrum on/off
1065 * bit 6 PixClk2 spread spectrum on/off
1068 * what causes setting of bits not obvious but:
1069 * bits 4&5 relate to headA
1070 * bits 6&7 relate to headB
1072 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1073 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1074 if (pNv->Architecture == NV_ARCH_40) {
1075 for (i = 0; i < 4; i++) {
1076 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1077 if (var == 0x1 || var == 0x4) {
1078 state->sel_clk &= ~(0xf << 4*i);
1079 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1080 if (crossed_clocks) {
1081 state->sel_clk |= (0x4 << 4*i);
1083 state->sel_clk |= (0x1 << 4*i);
1085 break; /* This should only occur once. */
1088 /* Based on NV31M. */
1089 } else if (pNv->Architecture == NV_ARCH_30) {
1090 for (i = 0; i < 4; i++) {
1091 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1092 if (var == 0x4 || var == 0x5) {
1093 state->sel_clk &= ~(0xf << 4*i);
1094 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1095 if (crossed_clocks) {
1096 state->sel_clk |= (0x4 << 4*i);
1098 state->sel_clk |= (0x5 << 4*i);
1100 break; /* This should only occur once. */
1106 /* Are we crosswired? */
1107 if (output && nv_crtc->head != nv_output->preferred_output) {
1108 state->crosswired = TRUE;
1110 state->crosswired = FALSE;
1113 if (nv_crtc->head == 1) {
1114 if (state->db1_ratio[1])
1115 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1116 } else if (nv_crtc->head == 0) {
1117 if (state->db1_ratio[0])
1118 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1121 /* Do NV1x/NV2x cards need anything in sel_clk? */
1122 state->sel_clk = 0x0;
1123 state->crosswired = FALSE;
1126 /* The NV40 seems to have more similarities to NV3x than other cards. */
1127 if (pNv->NVArch < 0x41) {
1128 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1129 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1132 if (nv_crtc->head == 1) {
1133 if (!state->db1_ratio[1]) {
1134 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1136 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1138 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1140 if (!state->db1_ratio[0]) {
1141 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1143 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1145 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1148 /* The blob uses this always, so let's do the same */
1149 if (pNv->Architecture == NV_ARCH_40) {
1150 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1153 /* The primary output resource doesn't seem to care */
1154 if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1155 /* non-zero values are for analog, don't know about tv-out and the likes */
1156 if (output && nv_output->type != OUTPUT_ANALOG) {
1157 state->reg594 = 0x0;
1158 } else if (output) {
1159 /* Are we a flexible output? */
1160 if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1161 state->reg594 = 0x1;
1162 pNv->restricted_mode = FALSE;
1164 state->reg594 = 0x0;
1165 pNv->restricted_mode = TRUE;
1168 /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1169 /* bit 16-19 are bits that are set on some G70 cards */
1170 /* Those bits are also set to the 3rd OUTPUT register */
1171 if (nv_crtc->head == 1) {
1172 state->reg594 |= 0x100;
1177 regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1178 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1179 if (pNv->Architecture >= NV_ARCH_30) {
1180 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1183 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1184 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1185 } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1186 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1187 } else { /* framebuffer can be larger than crtc scanout area. */
1188 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1190 regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1194 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1196 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1198 ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1200 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1203 nv_crtc->last_dpms = mode;
1205 ScrnInfoPtr pScrn = crtc->scrn;
1206 NVPtr pNv = NVPTR(pScrn);
1207 unsigned char seq1 = 0, crtc17 = 0;
1208 unsigned char crtc1A;
1211 NVCrtcSetOwner(crtc);
1213 crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1215 case DPMSModeStandby:
1216 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1221 case DPMSModeSuspend:
1222 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1228 /* Screen: Off; HSync: Off, VSync: Off */
1235 /* Screen: On; HSync: On, VSync: On */
1241 NVVgaSeqReset(crtc, TRUE);
1242 /* Each head has it's own sequencer, so we can turn it off when we want */
1243 seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1244 NVWriteVgaSeq(crtc, 0x1, seq1);
1245 crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1247 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1248 NVVgaSeqReset(crtc, FALSE);
1250 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1252 /* I hope this is the right place */
1253 if (crtc->enabled && mode == DPMSModeOn) {
1254 pNv->crtc_active[nv_crtc->head] = TRUE;
1256 pNv->crtc_active[nv_crtc->head] = FALSE;
1261 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1262 DisplayModePtr adjusted_mode)
1264 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1265 ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1271 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1273 ScrnInfoPtr pScrn = crtc->scrn;
1274 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1276 NVPtr pNv = NVPTR(pScrn);
1277 NVFBLayout *pLayout = &pNv->CurrentLayout;
1278 int depth = pScrn->depth;
1280 /* This is pitch/memory size related. */
1281 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1282 depth = pNv->console_mode[nv_crtc->head].bpp;
1284 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1286 /* Calculate our timings */
1287 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
1288 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
1289 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
1290 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
1291 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
1292 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
1293 int vertDisplay = mode->CrtcVDisplay - 1;
1294 int vertStart = mode->CrtcVSyncStart - 1;
1295 int vertEnd = mode->CrtcVSyncEnd - 1;
1296 int vertTotal = mode->CrtcVTotal - 2;
1297 int vertBlankStart = mode->CrtcVDisplay - 1;
1298 int vertBlankEnd = mode->CrtcVTotal - 1;
1302 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1303 NVOutputPrivatePtr nv_output = NULL;
1305 nv_output = output->driver_private;
1307 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1311 ErrorF("Mode clock: %d\n", mode->Clock);
1312 ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1314 /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1316 vertStart = vertTotal - 3;
1317 vertEnd = vertTotal - 2;
1318 vertBlankStart = vertStart;
1319 horizStart = horizTotal - 5;
1320 horizEnd = horizTotal - 2;
1321 horizBlankEnd = horizTotal + 4;
1322 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1323 /* This reportedly works around Xv some overlay bandwidth problems*/
1328 if (mode->Flags & V_INTERLACE)
1331 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1332 ErrorF("horizStart: 0x%X \n", horizStart);
1333 ErrorF("horizEnd: 0x%X \n", horizEnd);
1334 ErrorF("horizTotal: 0x%X \n", horizTotal);
1335 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1336 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1337 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1338 ErrorF("vertStart: 0x%X \n", vertStart);
1339 ErrorF("vertEnd: 0x%X \n", vertEnd);
1340 ErrorF("vertTotal: 0x%X \n", vertTotal);
1341 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1342 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1345 * compute correct Hsync & Vsync polarity
1347 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1348 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1350 regp->MiscOutReg = 0x23;
1351 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1352 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1354 int VDisplay = mode->VDisplay;
1355 if (mode->Flags & V_DBLSCAN)
1357 if (mode->VScan > 1)
1358 VDisplay *= mode->VScan;
1359 if (VDisplay < 400) {
1360 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
1361 } else if (VDisplay < 480) {
1362 regp->MiscOutReg = 0x63; /* -hsync +vsync */
1363 } else if (VDisplay < 768) {
1364 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
1366 regp->MiscOutReg = 0x23; /* +hsync +vsync */
1370 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1375 regp->Sequencer[0] = 0x00;
1376 /* 0x20 disables the sequencer */
1377 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1378 if (mode->HDisplay == 720) {
1379 regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1381 regp->Sequencer[1] = 0x20;
1384 if (mode->Flags & V_CLKDIV2) {
1385 regp->Sequencer[1] = 0x29;
1387 regp->Sequencer[1] = 0x21;
1390 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1391 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1393 regp->Sequencer[2] = 0x0F;
1395 regp->Sequencer[3] = 0x00; /* Font select */
1396 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1397 regp->Sequencer[4] = 0x02;
1399 regp->Sequencer[4] = 0x0E; /* Misc */
1405 regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
1406 regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
1407 regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
1408 regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
1410 regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
1411 regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
1412 | SetBitField(horizEnd,4:0,4:0);
1413 regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
1414 regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
1415 | SetBitField(vertDisplay,8:8,1:1)
1416 | SetBitField(vertStart,8:8,2:2)
1417 | SetBitField(vertBlankStart,8:8,3:3)
1419 | SetBitField(vertTotal,9:9,5:5)
1420 | SetBitField(vertDisplay,9:9,6:6)
1421 | SetBitField(vertStart,9:9,7:7);
1422 regp->CRTC[NV_VGA_CRTCX_PRROWSCN] = 0x00;
1423 regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
1425 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1426 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1427 if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1428 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1429 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1431 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1432 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1434 regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1435 regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1436 regp->CRTC[0xe] = 0x00;
1437 regp->CRTC[0xf] = 0x00;
1438 regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1439 /* What is the meaning of bit5, it is empty in the vga spec. */
1440 regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1441 (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1442 regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1443 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1444 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1445 } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1446 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1447 } else { /* framebuffer can be larger than crtc scanout area. */
1448 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1450 if (depth == 4) { /* How can these values be calculated? */
1451 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1453 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1455 regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1456 regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1457 /* 0x80 enables the sequencer, we don't want that */
1458 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1459 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1460 } else if (depth < 8) {
1461 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1463 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1465 regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1468 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1471 regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1472 | SetBitField(vertBlankStart,10:10,3:3)
1473 | SetBitField(vertStart,10:10,2:2)
1474 | SetBitField(vertDisplay,10:10,1:1)
1475 | SetBitField(vertTotal,10:10,0:0);
1477 regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1478 | SetBitField(horizDisplay,8:8,1:1)
1479 | SetBitField(horizBlankStart,8:8,2:2)
1480 | SetBitField(horizStart,8:8,3:3);
1482 regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1483 | SetBitField(vertDisplay,11:11,2:2)
1484 | SetBitField(vertStart,11:11,4:4)
1485 | SetBitField(vertBlankStart,11:11,6:6);
1487 if(mode->Flags & V_INTERLACE) {
1488 horizTotal = (horizTotal >> 1) & ~1;
1489 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1490 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1492 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
1496 * Theory resumes here....
1500 * Graphics Display Controller
1502 regp->Graphics[0] = 0x00;
1503 regp->Graphics[1] = 0x00;
1504 regp->Graphics[2] = 0x00;
1505 regp->Graphics[3] = 0x00;
1506 regp->Graphics[4] = 0x00;
1507 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1508 regp->Graphics[5] = 0x10;
1509 regp->Graphics[6] = 0x0E; /* map 32k mem */
1510 regp->Graphics[7] = 0x00;
1512 regp->Graphics[5] = 0x40; /* 256 color mode */
1513 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1514 regp->Graphics[7] = 0x0F;
1516 regp->Graphics[8] = 0xFF;
1518 /* I ditched the mono stuff */
1519 regp->Attribute[0] = 0x00; /* standard colormap translation */
1520 regp->Attribute[1] = 0x01;
1521 regp->Attribute[2] = 0x02;
1522 regp->Attribute[3] = 0x03;
1523 regp->Attribute[4] = 0x04;
1524 regp->Attribute[5] = 0x05;
1525 regp->Attribute[6] = 0x06;
1526 regp->Attribute[7] = 0x07;
1527 regp->Attribute[8] = 0x08;
1528 regp->Attribute[9] = 0x09;
1529 regp->Attribute[10] = 0x0A;
1530 regp->Attribute[11] = 0x0B;
1531 regp->Attribute[12] = 0x0C;
1532 regp->Attribute[13] = 0x0D;
1533 regp->Attribute[14] = 0x0E;
1534 regp->Attribute[15] = 0x0F;
1535 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1536 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1538 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1541 regp->Attribute[17] = 0x00;
1542 regp->Attribute[18] = 0x0F; /* enable all color planes */
1543 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1544 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1546 regp->Attribute[19] = 0x00;
1548 regp->Attribute[20] = 0x00;
1551 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1552 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1555 * Sets up registers for the given mode/adjusted_mode pair.
1557 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1559 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1560 * be easily turned on/off after this.
1563 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1565 ScrnInfoPtr pScrn = crtc->scrn;
1566 NVPtr pNv = NVPTR(pScrn);
1567 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1568 NVFBLayout *pLayout = &pNv->CurrentLayout;
1569 NVCrtcRegPtr regp, savep;
1572 Bool is_lvds = FALSE;
1574 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1575 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1577 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1578 NVOutputPrivatePtr nv_output = NULL;
1580 nv_output = output->driver_private;
1582 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1585 if (nv_output->type == OUTPUT_LVDS)
1589 /* Registers not directly related to the (s)vga mode */
1591 /* bit2 = 0 -> fine pitched crtc granularity */
1592 /* The rest disables double buffering on CRTC access */
1593 regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1595 if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1596 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1597 if (nv_crtc->head == 0) {
1598 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1602 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1603 if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1604 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1608 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1609 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1612 /* Sometimes 0x10 is used, what is this? */
1613 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1614 /* Some kind of tmds switch for older cards */
1615 if (pNv->Architecture < NV_ARCH_40) {
1616 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1620 * Initialize DAC palette.
1621 * Will only be written when depth != 8.
1623 for (i = 0; i < 256; i++) {
1625 regp->DAC[(i*3)+1] = i;
1626 regp->DAC[(i*3)+2] = i;
1630 * Calculate the extended registers.
1633 if (pLayout->depth < 24) {
1634 depth = pLayout->depth;
1639 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1640 /* bpp is pitch related. */
1641 depth = pNv->console_mode[nv_crtc->head].bpp;
1644 /* What is the meaning of this register? */
1645 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1646 regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1648 /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1649 /* But what are those special conditions? */
1650 if (pNv->Architecture <= NV_ARCH_30) {
1652 if(nv_crtc->head == 1) {
1653 regp->head |= NV_CRTC_FSEL_FPP1;
1654 } else if (pNv->twoHeads) {
1655 regp->head |= NV_CRTC_FSEL_FPP2;
1659 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1660 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1661 regp->head |= NV_CRTC_FSEL_FPP2;
1665 /* Except for rare conditions I2C is enabled on the primary crtc */
1666 if (nv_crtc->head == 0) {
1667 if (pNv->overlayAdaptor) {
1668 regp->head |= NV_CRTC_FSEL_OVERLAY;
1670 regp->head |= NV_CRTC_FSEL_I2C;
1673 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1674 /* This fixes my cursor corruption issue */
1675 regp->cursorConfig = 0x0;
1676 if(mode->Flags & V_DBLSCAN)
1677 regp->cursorConfig |= (1 << 4);
1678 if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1679 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1680 regp->cursorConfig |= 0x14011000;
1682 regp->cursorConfig |= 0x02000000;
1685 /* Unblock some timings */
1686 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1687 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1689 /* What is the purpose of this register? */
1690 /* 0x14 may be disabled? */
1691 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1693 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1695 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1697 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1699 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1702 /* These values seem to vary */
1703 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1704 regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1706 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1707 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1709 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1712 /* Some cards have 0x41 instead of 0x1 (for crtc 0), what is the meaning of that? */
1713 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1715 if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1716 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1718 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1719 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1721 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1722 if (nv_crtc->head == 1) {
1723 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1725 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1730 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1731 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1733 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1737 regp->unk830 = mode->CrtcVDisplay - 3;
1738 regp->unk834 = mode->CrtcVDisplay - 1;
1742 /* This is what the blob does */
1743 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1745 /* Never ever modify gpio, unless you know very well what you're doing */
1746 regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1748 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1749 regp->config = 0x0; /* VGA mode */
1751 regp->config = 0x2; /* HSYNC mode */
1754 /* Some misc regs */
1755 regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1756 if (pNv->Architecture == NV_ARCH_40) {
1757 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1758 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1762 * Calculate the state that is common to all crtc's (stored in the state struct).
1764 ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1765 nv_crtc_calc_state_ext(crtc,
1768 pScrn->displayWidth,
1771 adjusted_mode->Clock,
1774 /* Enable slaved mode */
1776 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1781 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1783 ScrnInfoPtr pScrn = crtc->scrn;
1784 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1785 NVCrtcRegPtr regp, savep;
1786 NVPtr pNv = NVPTR(pScrn);
1787 NVFBLayout *pLayout = &pNv->CurrentLayout;
1789 Bool is_lvds = FALSE;
1790 float aspect_ratio, panel_ratio;
1791 uint32_t h_scale, v_scale;
1793 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1794 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1796 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1797 NVOutputPrivatePtr nv_output = NULL;
1799 nv_output = output->driver_private;
1801 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1804 if (nv_output->type == OUTPUT_LVDS)
1809 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1810 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1811 /* This is what the blob does. */
1812 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1813 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1814 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1815 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1816 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1818 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1819 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1820 /* This is what the blob does. */
1821 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1822 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1823 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1824 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1825 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1827 /* Quirks, maybe move them somewere else? */
1829 switch(pNv->NVArch) {
1830 case 0x46: /* 7300GO */
1831 /* Only native mode needed, is there some logic to this? */
1832 if (mode->HDisplay == 1280 && mode->VDisplay == 800) {
1833 regp->fp_horiz_regs[REG_DISP_CRTC] = 0x4c6;
1841 ErrorF("Horizontal:\n");
1842 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1843 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1844 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1845 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1846 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1847 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1848 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1850 ErrorF("Vertical:\n");
1851 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1852 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1853 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1854 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1855 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1856 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1857 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1861 * bit0: positive vsync
1862 * bit4: positive hsync
1863 * bit8: enable center mode
1864 * bit9: enable native mode
1865 * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1866 * bit26: a bit sometimes seen on some g70 cards
1867 * bit28: fp display enable bit
1868 * bit31: set for dual link LVDS
1869 * nv10reg contains a few more things, but i don't quite get what it all means.
1872 if (pNv->Architecture >= NV_ARCH_30)
1873 regp->fp_control[nv_crtc->head] = 0x00100000;
1875 regp->fp_control[nv_crtc->head] = 0x00000000;
1877 /* Deal with vsync/hsync polarity */
1878 /* LVDS screens do set this, but modes with +ve syncs are very rare */
1880 if (adjusted_mode->Flags & V_PVSYNC)
1881 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1882 if (adjusted_mode->Flags & V_PHSYNC)
1883 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1885 /* The blob doesn't always do this, but often */
1886 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1887 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1891 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1892 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1893 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1894 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1895 /* This is also true for panel scaling, so we must put the panel scale check first */
1896 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1897 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1898 else /* gpu needs to scale */
1899 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1902 if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1903 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1905 /* If the special bit exists, it exists on both ramdacs */
1906 regp->fp_control[nv_crtc->head] |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1909 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1911 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1913 Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1914 if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1915 regp->fp_control[nv_crtc->head] |= (8 << 28);
1918 ErrorF("Pre-panel scaling\n");
1919 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1920 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1921 ErrorF("panel_ratio=%f\n", panel_ratio);
1922 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1923 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1924 /* Scale factors is the so called 20.12 format, taken from Haiku */
1925 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1926 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1927 ErrorF("h_scale=%d\n", h_scale);
1928 ErrorF("v_scale=%d\n", v_scale);
1930 /* This can override HTOTAL and VTOTAL */
1933 /* We want automatic scaling */
1936 regp->fp_hvalid_start = 0;
1937 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1939 regp->fp_vvalid_start = 0;
1940 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1942 /* 0 = panel scaling */
1943 if (nv_output->scaling_mode == SCALE_PANEL) {
1944 ErrorF("Flat panel is doing the scaling.\n");
1946 ErrorF("GPU is doing the scaling.\n");
1948 if (nv_output->scaling_mode == SCALE_ASPECT) {
1949 /* GPU scaling happens automaticly at a ratio of 1.33 */
1950 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1951 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1954 ErrorF("Scaling resolution on a widescreen panel\n");
1956 /* Scaling in both directions needs to the same */
1959 /* Set a new horizontal scale factor and enable testmode (bit12) */
1960 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1962 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1963 regp->fp_hvalid_start = diff/2;
1964 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1967 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1968 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1971 ErrorF("Scaling resolution on a portrait panel\n");
1973 /* Scaling in both directions needs to the same */
1976 /* Set a new vertical scale factor and enable testmode (bit28) */
1977 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1979 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1980 regp->fp_vvalid_start = diff/2;
1981 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1986 ErrorF("Post-panel scaling\n");
1989 if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
1990 regp->debug_1 = 0x08000800;
1993 if (pNv->Architecture >= NV_ARCH_10) {
1994 /* Bios and blob don't seem to do anything (else) */
1995 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1996 regp->nv10_cursync = (1<<25);
1998 regp->nv10_cursync = 0;
2001 /* These are the common blob values, minus a few fp specific bit's */
2002 /* Let's keep the TMDS pll and fpclock running in all situations */
2003 regp->debug_0[nv_crtc->head] = 0x1101100;
2005 if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2006 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2007 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2008 } else if (is_fp) { /* no_scale mode, so we must center it */
2011 diff = nv_output->fpWidth - mode->HDisplay;
2012 regp->fp_hvalid_start = diff/2;
2013 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2015 diff = nv_output->fpHeight - mode->VDisplay;
2016 regp->fp_vvalid_start = diff/2;
2017 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2020 /* Is this crtc bound or output bound? */
2021 /* Does the bios TMDS script try to change this sometimes? */
2023 /* I am not completely certain, but seems to be set only for dfp's */
2024 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2028 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2030 /* Flatpanel support needs at least a NV10 */
2031 if (pNv->twoHeads) {
2032 /* The blob does this differently. */
2033 /* TODO: Find out what precisely and why. */
2034 /* Let's not destroy any bits that were already present. */
2035 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2036 if (pNv->NVArch == 0x11) {
2037 regp->dither = savep->dither | 0x00010000;
2039 regp->dither = savep->dither | 0x00000001;
2042 regp->dither = savep->dither;
2047 /* This is mode related, not pitch. */
2048 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2049 depth = pNv->console_mode[nv_crtc->head].depth;
2051 depth = pLayout->depth;
2056 regp->general = 0x00000100;
2060 regp->general = 0x00100100;
2066 regp->general = 0x00101100;
2070 if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2071 regp->general |= 0x30; /* enable palette mode */
2074 if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2075 /* PIPE_LONG mode, something to do with the size of the cursor? */
2076 regp->general |= (1<<29);
2079 /* Some values the blob sets */
2080 /* This may apply to the real ramdac that is being used (for crosswired situations) */
2081 /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2082 regp->unk_a20 = 0x0;
2083 regp->unk_a24 = 0xfffff;
2084 regp->unk_a34 = 0x1;
2086 if (pNv->twoHeads) {
2087 /* Do we also "own" the other register pair? */
2088 /* If we own neither, they will just be ignored at load time. */
2089 uint8_t other_head = (~nv_crtc->head) & 1;
2090 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2091 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2092 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2093 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2094 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2095 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2096 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2098 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2105 * Sets up registers for the given mode/adjusted_mode pair.
2107 * The clocks, CRTCs and outputs attached to this CRTC must be off.
2109 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2110 * be easily turned on/off after this.
2113 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2114 DisplayModePtr adjusted_mode,
2117 ScrnInfoPtr pScrn = crtc->scrn;
2118 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2119 NVPtr pNv = NVPTR(pScrn);
2120 NVFBLayout *pLayout = &pNv->CurrentLayout;
2122 ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2124 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2125 xf86PrintModeline(pScrn->scrnIndex, mode);
2127 NVCrtcSetOwner(crtc);
2129 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2130 nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2131 nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2133 NVVgaProtect(crtc, TRUE);
2134 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2135 nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2136 if (pLayout->depth > 8)
2137 NVCrtcLoadPalette(crtc);
2138 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2139 if (pNv->Architecture == NV_ARCH_40) {
2140 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2142 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2145 NVVgaProtect(crtc, FALSE);
2147 NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2149 #if X_BYTE_ORDER == X_BIG_ENDIAN
2150 /* turn on LFB swapping */
2154 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2156 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2161 /* This functions generates data that is not saved, but still is needed. */
2162 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2164 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2165 ScrnInfoPtr pScrn = crtc->scrn;
2166 NVPtr pNv = NVPTR(pScrn);
2168 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2170 /* It's a good idea to also save a default palette on shutdown. */
2171 for (i = 0; i < 256; i++) {
2173 regp->DAC[(i*3)+1] = i;
2174 regp->DAC[(i*3)+2] = i;
2177 /* Noticed that reading this variable is problematic on one card. */
2178 if (pNv->NVArch == 0x11)
2179 state->sel_clk = 0x0;
2182 void nv_crtc_save(xf86CrtcPtr crtc)
2184 ScrnInfoPtr pScrn = crtc->scrn;
2185 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2186 NVPtr pNv = NVPTR(pScrn);
2188 ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2190 /* We just came back from terminal, so unlock */
2191 NVCrtcLockUnlock(crtc, FALSE);
2194 NVCrtcSetOwner(crtc);
2195 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2196 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2197 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2198 if (pNv->Architecture == NV_ARCH_40) {
2199 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2201 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2205 void nv_crtc_restore(xf86CrtcPtr crtc)
2207 ScrnInfoPtr pScrn = crtc->scrn;
2208 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2209 NVPtr pNv = NVPTR(pScrn);
2210 RIVA_HW_STATE *state;
2213 state = &pNv->SavedReg;
2214 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2216 ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2219 NVCrtcSetOwner(crtc);
2221 /* Just to be safe */
2222 NVCrtcLockUnlock(crtc, FALSE);
2224 NVVgaProtect(crtc, TRUE);
2225 nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2226 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2227 nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2228 if (savep->general & 0x30) /* Palette mode */
2229 NVCrtcLoadPalette(crtc);
2230 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2232 /* Force restoring vpll. */
2233 state->vpll_changed[nv_crtc->head] = TRUE;
2235 if (pNv->Architecture == NV_ARCH_40) {
2236 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2238 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2241 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2242 NVVgaProtect(crtc, FALSE);
2244 nv_crtc->last_dpms = NV_DPMS_CLEARED;
2248 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2250 ScrnInfoPtr pScrn = crtc->scrn;
2251 NVPtr pNv = NVPTR(pScrn);
2253 if (pNv->twoHeads) {
2256 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2261 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2265 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2269 void nv_crtc_prepare(xf86CrtcPtr crtc)
2271 ScrnInfoPtr pScrn = crtc->scrn;
2272 NVPtr pNv = NVPTR(pScrn);
2273 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2275 ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2278 NVCrtcLockUnlock(crtc, 0);
2280 NVResetCrtcConfig(crtc, FALSE);
2282 crtc->funcs->dpms(crtc, DPMSModeOff);
2284 /* Sync the engine before adjust mode */
2285 if (pNv->EXADriverPtr) {
2286 exaMarkSync(pScrn->pScreen);
2287 exaWaitSync(pScrn->pScreen);
2290 NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2292 /* Some more preperation. */
2293 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2294 if (pNv->Architecture == NV_ARCH_40) {
2295 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2296 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2300 void nv_crtc_commit(xf86CrtcPtr crtc)
2302 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2303 ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2305 crtc->funcs->dpms (crtc, DPMSModeOn);
2307 if (crtc->scrn->pScreen != NULL)
2308 xf86_reload_cursors (crtc->scrn->pScreen);
2310 NVResetCrtcConfig(crtc, TRUE);
2313 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2315 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2316 ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2321 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2323 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2324 ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2328 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2331 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2332 ScrnInfoPtr pScrn = crtc->scrn;
2333 NVPtr pNv = NVPTR(pScrn);
2337 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2339 switch (pNv->CurrentLayout.depth) {
2342 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2343 for (i = 0; i < 32; i++) {
2344 for (j = 0; j < 8; j++) {
2345 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2346 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2347 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2353 /* First deal with the 5 bit colors */
2354 for (i = 0; i < 32; i++) {
2355 for (j = 0; j < 8; j++) {
2356 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2357 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2360 /* Now deal with the 6 bit color */
2361 for (i = 0; i < 64; i++) {
2362 for (j = 0; j < 4; j++) {
2363 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2369 for (i = 0; i < 256; i++) {
2370 regp->DAC[i * 3] = red[i] >> 8;
2371 regp->DAC[(i * 3) + 1] = green[i] >> 8;
2372 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2377 NVCrtcLoadPalette(crtc);
2381 * Allocates memory for a locked-in-framebuffer shadow of the given
2382 * width and height for this CRTC's rotated shadow framebuffer.
2386 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2388 ErrorF("nv_crtc_shadow_allocate is called\n");
2389 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2390 ScrnInfoPtr pScrn = crtc->scrn;
2391 #if !NOUVEAU_EXA_PIXMAPS
2392 ScreenPtr pScreen = pScrn->pScreen;
2393 #endif /* !NOUVEAU_EXA_PIXMAPS */
2394 NVPtr pNv = NVPTR(pScrn);
2397 unsigned long rotate_pitch;
2398 int size, align = 64;
2400 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2401 size = rotate_pitch * height;
2403 assert(nv_crtc->shadow == NULL);
2404 #if NOUVEAU_EXA_PIXMAPS
2405 if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2406 align, size, &nv_crtc->shadow)) {
2407 ErrorF("Failed to allocate memory for shadow buffer!\n");
2411 if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2412 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2413 "Failed to map shadow buffer.\n");
2417 offset = nv_crtc->shadow->map;
2419 nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2420 if (nv_crtc->shadow == NULL) {
2421 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2422 "Couldn't allocate shadow memory for rotated CRTC\n");
2425 offset = pNv->FB->map + nv_crtc->shadow->offset;
2426 #endif /* NOUVEAU_EXA_PIXMAPS */
2432 * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2435 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2437 ErrorF("nv_crtc_shadow_create is called\n");
2438 ScrnInfoPtr pScrn = crtc->scrn;
2439 #if NOUVEAU_EXA_PIXMAPS
2440 ScreenPtr pScreen = pScrn->pScreen;
2441 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2442 #endif /* NOUVEAU_EXA_PIXMAPS */
2443 unsigned long rotate_pitch;
2444 PixmapPtr rotate_pixmap;
2445 #if NOUVEAU_EXA_PIXMAPS
2446 struct nouveau_pixmap *nvpix;
2447 #endif /* NOUVEAU_EXA_PIXMAPS */
2450 data = crtc->funcs->shadow_allocate (crtc, width, height);
2452 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2454 #if NOUVEAU_EXA_PIXMAPS
2455 /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2456 rotate_pixmap = pScreen->CreatePixmap(pScreen,
2459 #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2464 #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2466 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2469 pScrn->bitsPerPixel,
2472 #endif /* NOUVEAU_EXA_PIXMAPS */
2474 if (rotate_pixmap == NULL) {
2475 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2476 "Couldn't allocate shadow pixmap for rotated CRTC\n");
2479 #if NOUVEAU_EXA_PIXMAPS
2480 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2482 ErrorF("No shadow private, stage 1\n");
2484 nvpix->bo = nv_crtc->shadow;
2485 nvpix->mapped = TRUE;
2488 /* Modify the pixmap to actually be the one we need. */
2489 pScreen->ModifyPixmapHeader(rotate_pixmap,
2493 pScrn->bitsPerPixel,
2497 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2498 if (!nvpix || !nvpix->bo)
2499 ErrorF("No shadow private, stage 2\n");
2500 #endif /* NOUVEAU_EXA_PIXMAPS */
2502 return rotate_pixmap;
2506 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2508 ErrorF("nv_crtc_shadow_destroy is called\n");
2509 ScrnInfoPtr pScrn = crtc->scrn;
2510 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2511 ScreenPtr pScreen = pScrn->pScreen;
2513 if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2514 pScreen->DestroyPixmap(rotate_pixmap);
2517 #if !NOUVEAU_EXA_PIXMAPS
2518 if (data && nv_crtc->shadow) {
2519 exaOffscreenFree(pScreen, nv_crtc->shadow);
2521 #endif /* !NOUVEAU_EXA_PIXMAPS */
2523 nv_crtc->shadow = NULL;
2526 /* NV04-NV10 doesn't support alpha cursors */
2527 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2528 .dpms = nv_crtc_dpms,
2529 .save = nv_crtc_save, /* XXX */
2530 .restore = nv_crtc_restore, /* XXX */
2531 .mode_fixup = nv_crtc_mode_fixup,
2532 .mode_set = nv_crtc_mode_set,
2533 .prepare = nv_crtc_prepare,
2534 .commit = nv_crtc_commit,
2535 .destroy = NULL, /* XXX */
2536 .lock = nv_crtc_lock,
2537 .unlock = nv_crtc_unlock,
2538 .set_cursor_colors = nv_crtc_set_cursor_colors,
2539 .set_cursor_position = nv_crtc_set_cursor_position,
2540 .show_cursor = nv_crtc_show_cursor,
2541 .hide_cursor = nv_crtc_hide_cursor,
2542 .load_cursor_image = nv_crtc_load_cursor_image,
2543 .gamma_set = nv_crtc_gamma_set,
2544 .shadow_create = nv_crtc_shadow_create,
2545 .shadow_allocate = nv_crtc_shadow_allocate,
2546 .shadow_destroy = nv_crtc_shadow_destroy,
2549 /* NV11 and up has support for alpha cursors. */
2550 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2551 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2552 .dpms = nv_crtc_dpms,
2553 .save = nv_crtc_save, /* XXX */
2554 .restore = nv_crtc_restore, /* XXX */
2555 .mode_fixup = nv_crtc_mode_fixup,
2556 .mode_set = nv_crtc_mode_set,
2557 .prepare = nv_crtc_prepare,
2558 .commit = nv_crtc_commit,
2559 .destroy = NULL, /* XXX */
2560 .lock = nv_crtc_lock,
2561 .unlock = nv_crtc_unlock,
2562 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2563 .set_cursor_position = nv_crtc_set_cursor_position,
2564 .show_cursor = nv_crtc_show_cursor,
2565 .hide_cursor = nv_crtc_hide_cursor,
2566 .load_cursor_argb = nv_crtc_load_cursor_argb,
2567 .gamma_set = nv_crtc_gamma_set,
2568 .shadow_create = nv_crtc_shadow_create,
2569 .shadow_allocate = nv_crtc_shadow_allocate,
2570 .shadow_destroy = nv_crtc_shadow_destroy,
2575 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2577 NVPtr pNv = NVPTR(pScrn);
2579 NVCrtcPrivatePtr nv_crtc;
2581 if (pNv->NVArch >= 0x11) {
2582 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2584 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2589 nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2590 nv_crtc->head = crtc_num;
2591 nv_crtc->last_dpms = NV_DPMS_CLEARED;
2592 pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2594 crtc->driver_private = nv_crtc;
2596 NVCrtcLockUnlock(crtc, FALSE);
2599 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2601 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2605 regp = &state->crtc_reg[nv_crtc->head];
2607 NVWriteMiscOut(crtc, regp->MiscOutReg);
2609 for (i = 1; i < 5; i++)
2610 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2612 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2613 NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2615 for (i = 0; i < 25; i++)
2616 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2618 for (i = 0; i < 9; i++)
2619 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2621 NVEnablePalette(crtc);
2622 for (i = 0; i < 21; i++)
2623 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2625 NVDisablePalette(crtc);
2628 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2630 /* TODO - implement this properly */
2631 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2632 ScrnInfoPtr pScrn = crtc->scrn;
2633 NVPtr pNv = NVPTR(pScrn);
2635 if (pNv->Architecture == NV_ARCH_40) { /* HW bug */
2636 volatile uint32_t curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2637 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2640 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2642 ScrnInfoPtr pScrn = crtc->scrn;
2643 NVPtr pNv = NVPTR(pScrn);
2644 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2648 regp = &state->crtc_reg[nv_crtc->head];
2650 if (pNv->Architecture >= NV_ARCH_10) {
2651 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2652 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2653 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2654 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2655 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2656 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2657 nvWriteMC(pNv, 0x1588, 0);
2659 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2660 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2661 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2662 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2663 if (pNv->Architecture == NV_ARCH_40) {
2664 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2665 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2668 if (pNv->Architecture == NV_ARCH_40) {
2669 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2670 if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2671 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2673 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2678 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2679 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2681 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2682 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2683 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2684 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2685 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2686 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2687 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2688 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2689 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2690 if (pNv->Architecture >= NV_ARCH_30)
2691 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2693 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2694 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2695 nv_crtc_fix_nv40_hw_cursor(crtc);
2696 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2697 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2699 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2700 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2701 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2702 if (pNv->Architecture >= NV_ARCH_10) {
2703 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2704 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2705 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2706 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2707 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2709 /* NV11 and NV20 stop at 0x52. */
2710 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2712 for (i = 0; i < 0x10; i++)
2713 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2715 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2716 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2718 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2720 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2721 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2724 /* Setting 1 on this value gives you interrupts for every vblank period. */
2725 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2726 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2728 pNv->CurrentState = state;
2731 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2733 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2737 regp = &state->crtc_reg[nv_crtc->head];
2739 regp->MiscOutReg = NVReadMiscOut(crtc);
2741 for (i = 0; i < 25; i++)
2742 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2744 NVEnablePalette(crtc);
2745 for (i = 0; i < 21; i++)
2746 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2747 NVDisablePalette(crtc);
2749 for (i = 0; i < 9; i++)
2750 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2752 for (i = 1; i < 5; i++)
2753 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2756 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2758 ScrnInfoPtr pScrn = crtc->scrn;
2759 NVPtr pNv = NVPTR(pScrn);
2760 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2764 regp = &state->crtc_reg[nv_crtc->head];
2766 regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2767 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2768 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2769 regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2770 regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2771 regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2772 regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2774 regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2775 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2776 regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2777 if (pNv->Architecture >= NV_ARCH_30)
2778 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2779 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2780 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2781 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2782 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2784 if (pNv->Architecture >= NV_ARCH_10) {
2785 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2786 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2787 if (pNv->Architecture == NV_ARCH_40) {
2788 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2789 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2791 if (pNv->twoHeads) {
2792 regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2793 regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2795 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2798 regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2799 regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2801 regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2802 regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2803 regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2804 if (pNv->Architecture >= NV_ARCH_10) {
2805 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2806 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2807 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2808 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2809 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2811 /* NV11 and NV20 don't have this, they stop at 0x52. */
2812 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2813 for (i = 0; i < 0x10; i++)
2814 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2816 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2817 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2818 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2820 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2821 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2825 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2827 ScrnInfoPtr pScrn = crtc->scrn;
2828 NVPtr pNv = NVPTR(pScrn);
2829 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2833 regp = &state->crtc_reg[nv_crtc->head];
2835 regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2837 regp->fp_control[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2838 regp->debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2840 if (pNv->twoHeads) {
2841 regp->fp_control[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2842 regp->debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2844 regp->debug_1 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2845 regp->debug_2 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2847 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2848 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2849 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2852 if (pNv->NVArch == 0x11) {
2853 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2854 } else if (pNv->twoHeads) {
2855 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2857 if (pNv->Architecture >= NV_ARCH_10)
2858 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2860 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2862 for (i = 0; i < 7; i++) {
2863 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2864 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2867 for (i = 0; i < 7; i++) {
2868 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2869 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2872 regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2873 regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2874 regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2875 regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2878 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2880 ScrnInfoPtr pScrn = crtc->scrn;
2881 NVPtr pNv = NVPTR(pScrn);
2882 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2886 regp = &state->crtc_reg[nv_crtc->head];
2888 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2890 if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2891 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2892 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2894 if (pNv->twoHeads) {
2895 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2896 nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2897 nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2899 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2900 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2901 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2902 uint32_t reg890 = nvReadRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_890);
2903 nvWriteRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_89C, reg890);
2906 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2907 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2908 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2911 if (pNv->NVArch == 0x11) {
2912 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2913 } else if (pNv->twoHeads) {
2914 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2916 if (pNv->Architecture >= NV_ARCH_10)
2917 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2919 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2921 for (i = 0; i < 7; i++) {
2922 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2923 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2926 for (i = 0; i < 7; i++) {
2927 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2928 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2931 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2932 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2933 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2934 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2938 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2940 ScrnInfoPtr pScrn = crtc->scrn;
2941 NVPtr pNv = NVPTR(pScrn);
2942 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2943 NVFBLayout *pLayout = &pNv->CurrentLayout;
2946 ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2949 start = pNv->console_mode[nv_crtc->head].fb_start;
2951 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2952 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2953 #if NOUVEAU_EXA_PIXMAPS
2954 start = nv_crtc->shadow->offset;
2956 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2959 start += pNv->FB->offset;
2963 /* 30 bits addresses in 32 bits according to haiku */
2964 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2966 /* set NV4/NV10 byte adress: (bit0 - 1) */
2967 NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2973 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
2975 ScrnInfoPtr pScrn = crtc->scrn;
2976 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2977 NVPtr pNv = NVPTR(pScrn);
2978 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2980 NV_WR08(pDACReg, VGA_DAC_MASK, value);
2983 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
2985 ScrnInfoPtr pScrn = crtc->scrn;
2986 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2987 NVPtr pNv = NVPTR(pScrn);
2988 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2990 return NV_RD08(pDACReg, VGA_DAC_MASK);
2993 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
2995 ScrnInfoPtr pScrn = crtc->scrn;
2996 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2997 NVPtr pNv = NVPTR(pScrn);
2998 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3000 NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
3003 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
3005 ScrnInfoPtr pScrn = crtc->scrn;
3006 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3007 NVPtr pNv = NVPTR(pScrn);
3008 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3010 NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
3013 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
3015 ScrnInfoPtr pScrn = crtc->scrn;
3016 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3017 NVPtr pNv = NVPTR(pScrn);
3018 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3020 NV_WR08(pDACReg, VGA_DAC_DATA, value);
3023 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
3025 ScrnInfoPtr pScrn = crtc->scrn;
3026 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3027 NVPtr pNv = NVPTR(pScrn);
3028 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3030 return NV_RD08(pDACReg, VGA_DAC_DATA);
3033 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
3036 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3038 ScrnInfoPtr pScrn = crtc->scrn;
3039 NVPtr pNv = NVPTR(pScrn);
3041 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
3044 NVCrtcSetOwner(crtc);
3045 NVCrtcWriteDacMask(crtc, 0xff);
3046 NVCrtcWriteDacWriteAddr(crtc, 0x00);
3048 for (i = 0; i<768; i++) {
3049 NVCrtcWriteDacData(crtc, regp->DAC[i]);
3051 NVDisablePalette(crtc);
3055 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3057 NVPtr pNv = NVPTR(crtc->scrn);
3061 NVCrtcSetOwner(crtc);
3063 scrn = NVReadVgaSeq(crtc, 0x01);
3070 NVVgaSeqReset(crtc, TRUE);
3071 NVWriteVgaSeq(crtc, 0x01, scrn);
3072 NVVgaSeqReset(crtc, FALSE);
3075 /* Reset a mode after a drastic output resource change for example. */
3076 void NVCrtcModeFix(xf86CrtcPtr crtc)
3078 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3084 if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3087 DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3088 uint8_t dpms_mode = nv_crtc->last_dpms;
3090 /* Set the crtc mode again. */
3091 crtc->funcs->dpms(crtc, DPMSModeOff);
3092 need_unlock = crtc->funcs->lock(crtc);
3093 crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3094 crtc->funcs->prepare(crtc);
3095 crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3096 crtc->funcs->commit(crtc);
3098 crtc->funcs->unlock(crtc);
3099 crtc->funcs->dpms(crtc, dpms_mode);
3102 xfree(adjusted_mode);
3105 /*************************************************************************** \
3107 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
3109 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
3110 |* international laws. Users and possessors of this source code are *|
3111 |* hereby granted a nonexclusive, royalty-free copyright license to *|
3112 |* use this code in individual and commercial software. *|
3114 |* Any use of this source code must include, in the user documenta- *|
3115 |* tion and internal comments to the code, notices to the end user *|
3118 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
3120 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
3121 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
3122 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
3123 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
3124 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
3125 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
3126 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
3127 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
3128 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
3129 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
3130 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
3132 |* U.S. Government End Users. This source code is a "commercial *|
3133 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
3134 |* consisting of "commercial computer software" and "commercial *|
3135 |* computer software documentation," as such terms are used in *|
3136 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
3137 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
3138 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
3139 |* all U.S. Government End Users acquire the source code with only *|
3140 |* those rights set forth herein. *|
3142 \***************************************************************************/