2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
44 #include "mipointer.h"
45 #include "windowstr.h"
47 #include <X11/extensions/render.h>
50 #include "nv_include.h"
54 #define CRTC_INDEX 0x3d4
55 #define CRTC_DATA 0x3d5
56 #define CRTC_IN_STAT_1 0x3da
58 #define WHITE_VALUE 0x3F
59 #define BLACK_VALUE 0x00
60 #define OVERSCAN_VALUE 0x01
62 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
63 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
64 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
65 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
67 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
69 ScrnInfoPtr pScrn = crtc->scrn;
70 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
71 NVPtr pNv = NVPTR(pScrn);
73 if (nv_crtc->head == 1) {
74 return NV_RD08(pNv->PVIO1, address);
76 return NV_RD08(pNv->PVIO0, address);
80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
82 ScrnInfoPtr pScrn = crtc->scrn;
83 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
84 NVPtr pNv = NVPTR(pScrn);
86 if (nv_crtc->head == 1) {
87 NV_WR08(pNv->PVIO1, address, value);
89 NV_WR08(pNv->PVIO0, address, value);
93 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
95 NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
98 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
100 return NVReadPVIO(crtc, VGA_MISC_OUT_R);
103 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
105 volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
107 NV_WR08(pCRTCReg, CRTC_INDEX, index);
108 NV_WR08(pCRTCReg, CRTC_DATA, value);
111 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
113 volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
115 NV_WR08(pCRTCReg, CRTC_INDEX, index);
116 return NV_RD08(pCRTCReg, CRTC_DATA);
119 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
121 ScrnInfoPtr pScrn = crtc->scrn;
122 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
123 NVPtr pNv = NVPTR(pScrn);
125 NVWriteVGA(pNv, nv_crtc->head, index, value);
128 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
130 ScrnInfoPtr pScrn = crtc->scrn;
131 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
132 NVPtr pNv = NVPTR(pScrn);
134 return NVReadVGA(pNv, nv_crtc->head, index);
137 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
139 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
140 NVWritePVIO(crtc, VGA_SEQ_DATA, value);
143 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
145 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
146 return NVReadPVIO(crtc, VGA_SEQ_DATA);
149 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
151 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
152 NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
155 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
157 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
158 return NVReadPVIO(crtc, VGA_GRAPH_DATA);
162 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
164 ScrnInfoPtr pScrn = crtc->scrn;
165 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
166 NVPtr pNv = NVPTR(pScrn);
167 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
169 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
170 if (nv_crtc->paletteEnabled)
174 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
175 NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
178 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
180 ScrnInfoPtr pScrn = crtc->scrn;
181 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
182 NVPtr pNv = NVPTR(pScrn);
183 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
185 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
186 if (nv_crtc->paletteEnabled)
190 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
191 return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
194 void NVCrtcSetOwner(xf86CrtcPtr crtc)
196 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
197 ScrnInfoPtr pScrn = crtc->scrn;
198 NVPtr pNv = NVPTR(pScrn);
199 /* Non standard beheaviour required by NV11 */
201 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
202 ErrorF("pre-Owner: 0x%X\n", owner);
204 uint32_t pbus84 = nvReadMC(pNv, 0x1084);
205 ErrorF("pbus84: 0x%X\n", pbus84);
207 ErrorF("pbus84: 0x%X\n", pbus84);
208 nvWriteMC(pNv, 0x1084, pbus84);
210 /* The blob never writes owner to pcio1, so should we */
211 if (pNv->NVArch == 0x11) {
212 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
214 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
215 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
216 ErrorF("post-Owner: 0x%X\n", owner);
218 ErrorF("pNv pointer is NULL\n");
223 NVEnablePalette(xf86CrtcPtr crtc)
225 ScrnInfoPtr pScrn = crtc->scrn;
226 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
227 NVPtr pNv = NVPTR(pScrn);
228 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
230 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
231 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
232 nv_crtc->paletteEnabled = TRUE;
236 NVDisablePalette(xf86CrtcPtr crtc)
238 ScrnInfoPtr pScrn = crtc->scrn;
239 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
240 NVPtr pNv = NVPTR(pScrn);
241 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
243 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
244 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
245 nv_crtc->paletteEnabled = FALSE;
248 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
250 ScrnInfoPtr pScrn = crtc->scrn;
251 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
252 NVPtr pNv = NVPTR(pScrn);
253 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
255 NV_WR08(pCRTCReg, reg, value);
258 /* perform a sequencer reset */
259 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
262 NVWriteVgaSeq(crtc, 0x00, 0x1);
264 NVWriteVgaSeq(crtc, 0x00, 0x3);
267 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
272 tmp = NVReadVgaSeq(crtc, 0x1);
273 NVVgaSeqReset(crtc, TRUE);
274 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
276 NVEnablePalette(crtc);
279 * Reenable sequencer, then turn on screen.
281 tmp = NVReadVgaSeq(crtc, 0x1);
282 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
283 NVVgaSeqReset(crtc, FALSE);
285 NVDisablePalette(crtc);
289 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
293 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
294 cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
295 if (Lock) cr11 |= 0x80;
297 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
301 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
303 ScrnInfoPtr pScrn = crtc->scrn;
304 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
306 for (i = 0; i < xf86_config->num_output; i++) {
307 xf86OutputPtr output = xf86_config->output[i];
309 if (output->crtc == crtc) {
318 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
320 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
323 for (i = 0; i < xf86_config->num_crtc; i++) {
324 xf86CrtcPtr crtc = xf86_config->crtc[i];
325 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
326 if (nv_crtc->crtc == index)
334 * Calculate the Video Clock parameters for the PLL.
336 static void CalcVClock (
343 unsigned lowM, highM, highP;
344 unsigned DeltaNew, DeltaOld;
348 /* M: PLL reference frequency postscaler divider */
349 /* P: PLL VCO output postscaler divider */
350 /* N: PLL VCO postscaler setting */
352 DeltaOld = 0xFFFFFFFF;
354 VClk = (unsigned)clockIn;
356 /* Taken from Haiku, after someone with an NV28 had an issue */
357 switch(pNv->NVArch) {
363 } else if (VClk > 200000) {
365 } else if (VClk > 150000) {
376 } else if (VClk > 250000) {
384 for (P = 0; P <= highP; P++) {
386 if ((Freq >= 128000) && (Freq <= 350000)) {
387 for (M = lowM; M <= highM; M++) {
388 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
390 Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
392 DeltaNew = Freq - VClk;
394 DeltaNew = VClk - Freq;
396 if (DeltaNew < DeltaOld) {
397 *pllOut = (P << 16) | (N << 8) | M;
407 static void CalcVClock2Stage (
415 unsigned DeltaNew, DeltaOld;
418 unsigned lowM, highM, highP;
420 DeltaOld = 0xFFFFFFFF;
422 *pllBOut = 0x80000401; /* fixed at x4 for now */
424 VClk = (unsigned)clockIn;
426 /* Taken from Haiku, after someone with an NV28 had an issue */
427 switch(pNv->NVArch) {
433 } else if (VClk > 200000) {
435 } else if (VClk > 150000) {
446 } else if (VClk > 250000) {
454 for (P = 0; P <= highP; P++) {
456 if ((Freq >= 400000) && (Freq <= 1000000)) {
457 for (M = lowM; M <= highM; M++) {
458 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
459 if ((N >= 5) && (N <= 255)) {
460 Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
462 DeltaNew = Freq - VClk;
464 DeltaNew = VClk - Freq;
466 if (DeltaNew < DeltaOld) {
467 *pllOut = (P << 16) | (N << 8) | M;
477 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
479 state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
481 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
483 if(pNv->twoStagePLL) {
484 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
485 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
487 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
488 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
489 /* This seems to be strictly NV40 */
490 if (pNv->Architecture == NV_ARCH_40) {
491 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
496 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
498 CARD32 fp_debug_0[2];
500 fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
501 fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
503 /* The TMDS_PLL switch is on the actual ramdac */
504 if (state->crosswired) {
507 ErrorF("Crosswired pll state load\n");
514 if (pNv->Architecture == NV_ARCH_40) {
515 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
516 fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
518 /* Wait for the situation to stabilise */
521 CARD32 reg_c040 = pNv->misc_info.reg_c040;
522 /* for vpll2 change bits 18 and 19 are disabled */
523 reg_c040 &= ~(0x3 << 18);
524 nvWriteMC(pNv, 0xc040, reg_c040);
528 ErrorF("writing vpll2 %08X\n", state->vpll2);
529 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
531 if(pNv->twoStagePLL) {
532 ErrorF("writing vpll2B %08X\n", state->vpll2B);
533 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
536 ErrorF("writing pllsel %08X\n", state->pllsel);
537 /* Let's keep the primary vpll off */
538 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
540 if (pNv->Architecture == NV_ARCH_40) {
541 uint32_t reg580 = state->reg580;
542 /* Let's keep vpll1 off for the moment */
543 if (!(pNv->misc_info.ramdac_0_reg_580 & NV_RAMDAC_580_VPLL1_ACTIVE))
544 reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
545 ErrorF("writing reg580 %08X\n", reg580);
546 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, reg580);
547 /* We need to wait a while */
549 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
551 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
553 /* Wait for the situation to stabilise */
558 if (pNv->Architecture == NV_ARCH_40) {
559 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
560 fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
562 /* Wait for the situation to stabilise */
565 CARD32 reg_c040 = pNv->misc_info.reg_c040;
566 /* for vpll1 change bits 16 and 17 are disabled */
567 reg_c040 &= ~(0x3 << 16);
568 nvWriteMC(pNv, 0xc040, reg_c040);
571 ErrorF("writing vpll %08X\n", state->vpll);
572 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
573 if(pNv->twoStagePLL) {
574 ErrorF("writing vpllB %08X\n", state->vpllB);
575 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
578 ErrorF("writing pllsel %08X\n", state->pllsel);
579 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
581 if (pNv->Architecture == NV_ARCH_40) {
582 ErrorF("writing reg580 %08X\n", state->reg580);
583 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
584 /* We need to wait a while */
586 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
588 /* This register is only written after the last clock is set */
589 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
591 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
593 /* Wait for the situation to stabilise */
599 * Calculate extended mode parameters (SVGA) and save in a
600 * mode state structure.
602 void nv_crtc_calc_state_ext(
605 int DisplayWidth, /* Does this change after setting the mode? */
612 ScrnInfoPtr pScrn = crtc->scrn;
613 int pixelDepth, VClk = 0;
615 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
616 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
618 NVPtr pNv = NVPTR(pScrn);
619 RIVA_HW_STATE *state;
620 int num_crtc_enabled, i;
622 state = &pNv->ModeReg;
624 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
626 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
627 NVOutputPrivatePtr nv_output = output->driver_private;
630 * Extended RIVA registers.
632 pixelDepth = (bpp + 1)/8;
634 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
636 CalcVClock(dotClock, &VClk, &state->pll, pNv);
638 switch (pNv->Architecture) {
640 nv4UpdateArbitrationSettings(VClk,
642 &(state->arbitration0),
643 &(state->arbitration1),
645 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
646 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
647 if (flags & V_DBLSCAN)
648 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
649 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
650 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
651 state->config = 0x00001114;
652 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
658 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
659 ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
660 state->arbitration0 = 128;
661 state->arbitration1 = 0x0480;
662 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
663 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
664 nForceUpdateArbitrationSettings(VClk,
666 &(state->arbitration0),
667 &(state->arbitration1),
669 } else if (pNv->Architecture < NV_ARCH_30) {
670 nv10UpdateArbitrationSettings(VClk,
672 &(state->arbitration0),
673 &(state->arbitration1),
676 nv30UpdateArbitrationSettings(pNv,
677 &(state->arbitration0),
678 &(state->arbitration1));
681 CursorStart = pNv->Cursor->offset;
683 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
684 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
685 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
687 if (flags & V_DBLSCAN)
688 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
690 state->config = nvReadFB(pNv, NV_PFB_CFG0);
691 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
695 /* okay do we have 2 CRTCs running ? */
696 num_crtc_enabled = 0;
697 for (i = 0; i < xf86_config->num_crtc; i++) {
698 if (xf86_config->crtc[i]->enabled) {
703 ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
705 if (pNv->Architecture == NV_ARCH_40) {
706 /* This register is only used on the primary ramdac */
707 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
708 /* Assumption CRTC1 will overwrite the CRTC0 value */
709 /* Also make sure we don't set both bits */
710 state->sel_clk = (pNv->misc_info.sel_clk & ~(0xf << 16)) | (1 << 18);
711 /* Are we a TMDS running on head 0(=ramdac 0), but native to ramdac 1? */
712 if (nv_crtc->head == 0 && nv_output->type == OUTPUT_TMDS && nv_output->valid_ramdac & RAMDAC_1) {
713 state->sel_clk = (pNv->misc_info.sel_clk & ~(0xf << 16)) | (1 << 16);
714 state->crosswired = TRUE;
715 } else if (nv_crtc->head == 0) {
716 state->crosswired = FALSE;
719 /* Do not remove any present VPLL related bits, that can cause problems */
720 /* The meaning of this register is debatable */
722 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
724 Bool vpll1_ok = TRUE;
725 Bool vpll2_ok = TRUE;
727 /* For lack of a better name */
728 int magic_factor = (pNv->misc_info.sel_clk & (0xf << 8)) >> 8;
730 /* A common situation on G70 cards, many seem to prefer DB1 vclk ratio */
731 if ((state->reg580 & 0xff) == 0x3d) {
732 switch(magic_factor) {
747 /* Vclk ratio DB1 is used whenever reg580 is modified for vpll activity */
748 if (!(pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2)) {
749 if (nv_crtc->head == 1 && vpll2_ok) {
750 state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
751 } else if (nv_crtc->head == 0 && vpll1_ok) {
752 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
757 /* We've bound crtc's and ramdac's together */
758 if (nv_crtc->crtc == 1) {
759 state->vpll2 = state->pll;
760 state->vpll2B = state->pllB;
761 if (pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2) {
762 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
764 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
766 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
768 state->vpll = state->pll;
769 state->vpllB = state->pllB;
770 if (nv_output->type == OUTPUT_LVDS)
771 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
773 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
774 if (pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2) {
775 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
777 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
781 /* The purpose is unknown */
782 if (pNv->Architecture == NV_ARCH_40)
783 state->pllsel |= (1 << 2);
785 regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
786 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
787 if (pNv->Architecture >= NV_ARCH_30) {
788 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
791 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
792 regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
796 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
798 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
799 ScrnInfoPtr pScrn = crtc->scrn;
800 NVPtr pNv = NVPTR(pScrn);
801 unsigned char seq1 = 0, crtc17 = 0;
802 unsigned char crtc1A;
804 ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
806 NVCrtcSetOwner(crtc);
808 crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
810 case DPMSModeStandby:
811 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
816 case DPMSModeSuspend:
817 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
823 /* Screen: Off; HSync: Off, VSync: Off */
830 /* Screen: On; HSync: On, VSync: On */
836 NVVgaSeqReset(crtc, TRUE);
837 /* Each head has it's own sequencer, so we can turn it off when we want */
838 seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
839 NVWriteVgaSeq(crtc, 0x1, seq1);
840 crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
842 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
843 NVVgaSeqReset(crtc, FALSE);
845 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
847 /* I hope this is the right place */
848 if (crtc->enabled && mode == DPMSModeOn) {
849 pNv->crtc_active[nv_crtc->head] = TRUE;
851 pNv->crtc_active[nv_crtc->head] = FALSE;
856 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
857 DisplayModePtr adjusted_mode)
859 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
860 ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
866 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
868 ScrnInfoPtr pScrn = crtc->scrn;
869 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
871 NVPtr pNv = NVPTR(pScrn);
872 int depth = pScrn->depth;
875 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
878 * compute correct Hsync & Vsync polarity
880 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
881 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
883 regp->MiscOutReg = 0x23;
884 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
885 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
887 int VDisplay = mode->VDisplay;
888 if (mode->Flags & V_DBLSCAN)
891 VDisplay *= mode->VScan;
892 if (VDisplay < 400) {
893 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
894 } else if (VDisplay < 480) {
895 regp->MiscOutReg = 0x63; /* -hsync +vsync */
896 } else if (VDisplay < 768) {
897 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
899 regp->MiscOutReg = 0x23; /* +hsync +vsync */
903 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
909 regp->Sequencer[0] = 0x02;
911 regp->Sequencer[0] = 0x00;
913 /* 0x20 disables the sequencer */
914 if (mode->Flags & V_CLKDIV2) {
915 regp->Sequencer[1] = 0x29;
917 regp->Sequencer[1] = 0x21;
920 regp->Sequencer[2] = 1 << BIT_PLANE;
922 regp->Sequencer[2] = 0x0F;
923 regp->Sequencer[3] = 0x00; /* Font select */
926 regp->Sequencer[4] = 0x06; /* Misc */
928 regp->Sequencer[4] = 0x0E; /* Misc */
934 regp->CRTC[0] = (mode->CrtcHTotal >> 3) - 5;
935 regp->CRTC[1] = (mode->CrtcHDisplay >> 3) - 1;
936 regp->CRTC[2] = (mode->CrtcHBlankStart >> 3) - 1;
937 regp->CRTC[3] = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
938 i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
942 regp->CRTC[4] = (mode->CrtcHSyncStart >> 3);
943 regp->CRTC[5] = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
944 | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
945 regp->CRTC[6] = (mode->CrtcVTotal - 2) & 0xFF;
946 regp->CRTC[7] = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
947 | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
948 | ((mode->CrtcVSyncStart & 0x100) >> 6)
949 | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
951 | (((mode->CrtcVTotal - 2) & 0x200) >> 4)
952 | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
953 | ((mode->CrtcVSyncStart & 0x200) >> 2);
954 regp->CRTC[8] = 0x00;
955 regp->CRTC[9] = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
956 if (mode->Flags & V_DBLSCAN) {
957 regp->CRTC[9] |= 0x80;
959 if (mode->VScan >= 32) {
960 regp->CRTC[9] |= 0x1F;
961 } else if (mode->VScan > 1) {
962 regp->CRTC[9] |= mode->VScan - 1;
964 regp->CRTC[10] = 0x00;
965 regp->CRTC[11] = 0x00;
966 regp->CRTC[12] = 0x00;
967 regp->CRTC[13] = 0x00;
968 regp->CRTC[14] = 0x00;
969 regp->CRTC[15] = 0x00;
970 regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
971 regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
972 regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
973 regp->CRTC[19] = mode->CrtcHDisplay >> 4; /* just a guess */
974 regp->CRTC[20] = 0x00;
975 regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
976 regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
977 /* 0x80 enables the sequencer, we don't want that */
979 regp->CRTC[23] = 0xE3 & ~0x80;
981 regp->CRTC[23] = 0xC3 & ~0x80;
983 regp->CRTC[24] = 0xFF;
986 * Theory resumes here....
990 * Graphics Display Controller
992 regp->Graphics[0] = 0x00;
993 regp->Graphics[1] = 0x00;
994 regp->Graphics[2] = 0x00;
995 regp->Graphics[3] = 0x00;
997 regp->Graphics[4] = BIT_PLANE;
998 regp->Graphics[5] = 0x00;
1000 regp->Graphics[4] = 0x00;
1002 regp->Graphics[5] = 0x02;
1004 regp->Graphics[5] = 0x40;
1007 regp->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
1008 regp->Graphics[7] = 0x0F;
1009 regp->Graphics[8] = 0xFF;
1012 /* Initialise the Mono map according to which bit-plane gets used */
1014 Bool flipPixels = xf86GetFlipPixels();
1016 for (i=0; i<16; i++) {
1017 if (((i & (1 << BIT_PLANE)) != 0) != flipPixels) {
1018 regp->Attribute[i] = WHITE_VALUE;
1020 regp->Attribute[i] = BLACK_VALUE;
1025 regp->Attribute[0] = 0x00; /* standard colormap translation */
1026 regp->Attribute[1] = 0x01;
1027 regp->Attribute[2] = 0x02;
1028 regp->Attribute[3] = 0x03;
1029 regp->Attribute[4] = 0x04;
1030 regp->Attribute[5] = 0x05;
1031 regp->Attribute[6] = 0x06;
1032 regp->Attribute[7] = 0x07;
1033 regp->Attribute[8] = 0x08;
1034 regp->Attribute[9] = 0x09;
1035 regp->Attribute[10] = 0x0A;
1036 regp->Attribute[11] = 0x0B;
1037 regp->Attribute[12] = 0x0C;
1038 regp->Attribute[13] = 0x0D;
1039 regp->Attribute[14] = 0x0E;
1040 regp->Attribute[15] = 0x0F;
1042 regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
1044 regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
1047 regp->Attribute[17] = 0xff;
1049 /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
1051 regp->Attribute[18] = 0x0F;
1052 regp->Attribute[19] = 0x00;
1053 regp->Attribute[20] = 0x00;
1056 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1057 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1060 * Sets up registers for the given mode/adjusted_mode pair.
1062 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1064 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1065 * be easily turned on/off after this.
1068 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1070 ScrnInfoPtr pScrn = crtc->scrn;
1071 NVPtr pNv = NVPTR(pScrn);
1072 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1073 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1074 NVFBLayout *pLayout = &pNv->CurrentLayout;
1075 NVCrtcRegPtr regp, savep;
1077 uint32_t clock = adjusted_mode->Clock;
1079 /* Happily borrowed from haiku driver, as an extra safety */
1081 /* Make it multiples of 8 */
1082 mode->CrtcHDisplay &= ~7;
1083 mode->CrtcHSyncStart &= ~7;
1084 mode->CrtcHSyncEnd &= ~7;
1085 mode->CrtcHTotal &= ~7;
1087 /* Horizontal stuff */
1089 /* Time for some mode mangling */
1090 /* We only have 9 bits to store most of this information (mask 0x3f) */
1091 if (mode->CrtcHDisplay > MAX_H_VALUE(-2))
1092 mode->CrtcHDisplay = MAX_H_VALUE(-2);
1094 if (mode->CrtcHSyncStart > MAX_H_VALUE(-1))
1095 mode->CrtcHSyncStart = MAX_H_VALUE(-1);
1097 if (mode->CrtcHSyncEnd > MAX_H_VALUE(0))
1098 mode->CrtcHSyncEnd = MAX_H_VALUE(0);
1100 if (mode->CrtcHTotal > MAX_H_VALUE(5))
1101 mode->CrtcHTotal = MAX_H_VALUE(5);
1103 /* Make room for a sync pulse if there is not enough room */
1104 if (mode->CrtcHTotal < mode->CrtcHSyncEnd + 0x50)
1105 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x50;
1107 /* Too large sync pulse? */
1108 if (mode->CrtcHTotal > mode->CrtcHSyncEnd + 0x3f8)
1109 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x3f8;
1111 /* Is the sync pulse outside the screen? */
1112 if (mode->CrtcHSyncEnd > mode->CrtcHTotal - 8)
1113 mode->CrtcHSyncEnd = mode->CrtcHTotal - 8;
1115 if (mode->CrtcHSyncStart < mode->CrtcHDisplay + 8)
1116 mode->CrtcHSyncStart = mode->CrtcHDisplay + 8;
1118 /* We've only got 5 bits to store the sync stuff */
1119 if (mode->CrtcHSyncEnd > mode->CrtcHSyncStart + (0x1f << 3))
1120 mode->CrtcHSyncEnd = mode->CrtcHSyncStart + (0x1f << 3);
1122 /* Vertical stuff */
1124 /* We've only got 12 bits for this stuff */
1125 if (mode->CrtcVDisplay > MAX_V_VALUE(-2))
1126 mode->CrtcVDisplay = MAX_V_VALUE(-2);
1128 if (mode->CrtcVSyncStart > MAX_V_VALUE(-1))
1129 mode->CrtcVSyncStart = MAX_V_VALUE(-1);
1131 if (mode->CrtcVSyncEnd > MAX_V_VALUE(0))
1132 mode->CrtcVSyncEnd = MAX_V_VALUE(0);
1134 if (mode->CrtcVTotal > MAX_V_VALUE(5))
1135 mode->CrtcVTotal = MAX_V_VALUE(5);
1137 /* Make room for a sync pulse if there is not enough room */
1138 if (mode->CrtcVTotal < mode->CrtcVSyncEnd + 0x3)
1139 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0x3;
1141 /* Too large sync pulse? */
1142 if (mode->CrtcVTotal > mode->CrtcVSyncEnd + 0xff)
1143 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0xff;
1145 /* Is the sync pulse outside the screen? */
1146 if (mode->CrtcVSyncEnd > mode->CrtcVTotal - 1)
1147 mode->CrtcVSyncEnd = mode->CrtcVTotal - 1;
1149 if (mode->CrtcVSyncStart < mode->CrtcVDisplay + 1)
1150 mode->CrtcVSyncStart = mode->CrtcVDisplay + 1;
1152 /* We've only got 4 bits to store the sync stuff */
1153 if (mode->CrtcVSyncEnd > mode->CrtcVSyncStart + (0x0f << 0))
1154 mode->CrtcVSyncEnd = mode->CrtcVSyncStart + (0x0f << 0);
1156 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
1157 int horizStart = (mode->CrtcHSyncStart >> 3);
1158 /* The reason for this offset is completelt unknown, but important to keep analog screen alligned */
1159 int horizEnd = (mode->CrtcHSyncEnd >> 3) + 4;
1160 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
1161 int horizBlankStart = horizDisplay;
1162 int horizBlankEnd = horizTotal + 4;
1163 int vertDisplay = mode->CrtcVDisplay - 1;
1164 int vertStart = mode->CrtcVSyncStart;
1165 int vertEnd = mode->CrtcVSyncEnd;
1166 int vertTotal = mode->CrtcVTotal - 2;
1167 int vertBlankStart = vertDisplay;
1168 int vertBlankEnd = vertTotal + 1;
1169 int lineComp = mode->CrtcVDisplay;
1173 xf86OutputPtr output;
1174 NVOutputPrivatePtr nv_output;
1175 for (i = 0; i < xf86_config->num_output; i++) {
1176 output = xf86_config->output[i];
1177 nv_output = output->driver_private;
1179 if (output->crtc == crtc) {
1180 if ((nv_output->type == OUTPUT_LVDS) ||
1181 (nv_output->type == OUTPUT_TMDS)) {
1189 ErrorF("Mode clock: %d\n", clock);
1191 ErrorF("crtc: Pre-sync workaround\n");
1192 /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1194 vertStart = vertTotal - 3;
1195 vertEnd = vertTotal - 2;
1196 vertBlankStart = vertStart;
1197 horizStart = horizTotal - 5;
1198 horizEnd = horizTotal - 2;
1199 horizBlankEnd = horizTotal + 4;
1200 if (pNv->overlayAdaptor) {
1201 /* This reportedly works around Xv some overlay bandwidth problems*/
1205 ErrorF("crtc: Post-sync workaround\n");
1207 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1208 ErrorF("horizStart: 0x%X \n", horizStart);
1209 ErrorF("horizEnd: 0x%X \n", horizEnd);
1210 ErrorF("horizTotal: 0x%X \n", horizTotal);
1211 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1212 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1213 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1214 ErrorF("vertStart: 0x%X \n", vertStart);
1215 ErrorF("vertEnd: 0x%X \n", vertEnd);
1216 ErrorF("vertTotal: 0x%X \n", vertTotal);
1217 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1218 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1220 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1221 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1223 if(mode->Flags & V_INTERLACE)
1226 regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
1227 regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
1228 regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
1229 regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
1231 regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
1232 regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
1233 | SetBitField(horizEnd,4:0,4:0);
1234 regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
1235 regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
1236 | SetBitField(vertDisplay,8:8,1:1)
1237 | SetBitField(vertStart,8:8,2:2)
1238 | SetBitField(vertBlankStart,8:8,3:3)
1239 | SetBitField(lineComp,8:8,4:4)
1240 | SetBitField(vertTotal,9:9,5:5)
1241 | SetBitField(vertDisplay,9:9,6:6)
1242 | SetBitField(vertStart,9:9,7:7);
1243 regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
1244 | SetBitField(lineComp,9:9,6:6)
1245 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1246 regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1247 regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1248 regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1249 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1250 regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1251 regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1252 /* Not an extended register */
1253 regp->CRTC[NV_VGA_CRTCX_LINECOMP] = lineComp & 0xff;
1255 regp->Attribute[0x10] = 0x01;
1256 /* Blob sets this for normal monitors as well */
1257 regp->Attribute[0x11] = 0x00;
1259 regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1260 | SetBitField(vertBlankStart,10:10,3:3)
1261 | SetBitField(vertStart,10:10,2:2)
1262 | SetBitField(vertDisplay,10:10,1:1)
1263 | SetBitField(vertTotal,10:10,0:0);
1265 regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1266 | SetBitField(horizDisplay,8:8,1:1)
1267 | SetBitField(horizBlankStart,8:8,2:2)
1268 | SetBitField(horizStart,8:8,3:3);
1270 regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1271 | SetBitField(vertDisplay,11:11,2:2)
1272 | SetBitField(vertStart,11:11,4:4)
1273 | SetBitField(vertBlankStart,11:11,6:6);
1275 if(mode->Flags & V_INTERLACE) {
1276 horizTotal = (horizTotal >> 1) & ~1;
1277 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1278 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1280 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
1283 /* bit2 = 0 -> fine pitched crtc granularity */
1284 /* The rest disables double buffering on CRTC access */
1285 regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfb;
1287 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1288 if (nv_crtc->head == 0) {
1289 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1293 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1296 /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1298 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1300 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1304 * Initialize DAC palette.
1306 if(pLayout->bitsPerPixel != 8 ) {
1307 for (i = 0; i < 256; i++) {
1309 regp->DAC[(i*3)+1] = i;
1310 regp->DAC[(i*3)+2] = i;
1315 * Calculate the extended registers.
1318 if(pLayout->depth < 24) {
1324 if(pNv->Architecture >= NV_ARCH_10) {
1325 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1328 ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1329 nv_crtc_calc_state_ext(crtc,
1331 pScrn->displayWidth,
1337 /* Enable slaved mode */
1339 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1342 /* What is the meaning of this register? */
1343 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1344 regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1];
1346 /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1347 /* But what are those special conditions? */
1348 if (pNv->Architecture <= NV_ARCH_30) {
1350 if(nv_crtc->head == 1) {
1351 regp->head |= NV_CRTC_FSEL_FPP1;
1352 } else if (pNv->twoHeads) {
1353 regp->head |= NV_CRTC_FSEL_FPP2;
1357 /* This is observed on some g70 cards, non-flatpanel's too */
1358 if (nv_crtc->head == 1) {
1359 regp->head |= NV_CRTC_FSEL_FPP2;
1363 if (nv_crtc->head == 0) {
1364 if (pNv->overlayAdaptor) {
1365 regp->head |= NV_CRTC_FSEL_OVERLAY;
1369 /* I'm hoping that enabling this on both heads gives the best of both worlds */
1370 /* Bad things happen when you only enable it on head 1 and disable that head */
1371 regp->head |= NV_CRTC_FSEL_I2C;
1373 regp->cursorConfig = 0x00000100;
1374 if(mode->Flags & V_DBLSCAN)
1375 regp->cursorConfig |= (1 << 4);
1376 if(pNv->alphaCursor) {
1377 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11) {
1378 regp->cursorConfig |= 0x04011000;
1380 regp->cursorConfig |= 0x14011000;
1383 regp->cursorConfig |= 0x02000000;
1386 /* Unblock some timings */
1387 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1388 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1390 /* 0x20 seems to be enabled and 0x14 disabled */
1391 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1393 /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1396 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1398 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1401 /* These values seem to vary */
1402 regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1404 /* 0x80 seems to be used very often, if not always */
1405 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1407 /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1408 regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1410 /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1411 //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1412 regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1414 regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1416 /* bit0: Seems to be mostly used on crtc1 */
1417 /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1418 /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1419 /* This is likely to be incomplete */
1420 /* This is a very strange register, changed very often by the blob */
1421 regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1423 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1424 if (nv_crtc->head == 1) {
1425 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1427 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1430 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1431 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1433 regp->unk830 = mode->CrtcVDisplay - 3;
1434 regp->unk834 = mode->CrtcVDisplay - 1;
1436 /* This is what the blob does */
1437 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1439 /* Never ever modify gpio, unless you know very well what you're doing */
1440 regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1444 * Sets up registers for the given mode/adjusted_mode pair.
1446 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1448 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1449 * be easily turned on/off after this.
1452 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1453 DisplayModePtr adjusted_mode,
1456 ScrnInfoPtr pScrn = crtc->scrn;
1457 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1458 NVPtr pNv = NVPTR(pScrn);
1460 ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1462 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1463 xf86PrintModeline(pScrn->scrnIndex, mode);
1464 NVCrtcSetOwner(crtc);
1466 nv_crtc_mode_set_vga(crtc, mode);
1467 nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1469 NVVgaProtect(crtc, TRUE);
1470 nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1471 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1472 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1474 NVVgaProtect(crtc, FALSE);
1475 // NVCrtcLockUnlock(crtc, 1);
1477 NVCrtcSetBase(crtc, x, y);
1479 #if X_BYTE_ORDER == X_BIG_ENDIAN
1480 /* turn on LFB swapping */
1484 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1486 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1492 void nv_crtc_save(xf86CrtcPtr crtc)
1494 ScrnInfoPtr pScrn = crtc->scrn;
1495 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1496 NVPtr pNv = NVPTR(pScrn);
1498 ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1500 NVCrtcSetOwner(crtc);
1501 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1502 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1503 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1506 void nv_crtc_restore(xf86CrtcPtr crtc)
1508 ScrnInfoPtr pScrn = crtc->scrn;
1509 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1510 NVPtr pNv = NVPTR(pScrn);
1512 ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1514 NVCrtcSetOwner(crtc);
1515 nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1516 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1517 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1518 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1521 void nv_crtc_prepare(xf86CrtcPtr crtc)
1523 ScrnInfoPtr pScrn = crtc->scrn;
1524 NVPtr pNv = NVPTR(pScrn);
1525 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1527 ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1529 crtc->funcs->dpms(crtc, DPMSModeOff);
1531 /* Sync the engine before adjust mode */
1532 if (pNv->EXADriverPtr) {
1533 exaMarkSync(pScrn->pScreen);
1534 exaWaitSync(pScrn->pScreen);
1538 void nv_crtc_commit(xf86CrtcPtr crtc)
1540 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1541 ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1543 crtc->funcs->dpms (crtc, DPMSModeOn);
1544 if (crtc->scrn->pScreen != NULL)
1545 xf86_reload_cursors (crtc->scrn->pScreen);
1548 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1550 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1551 ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1556 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1558 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1559 ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1562 /* NV04-NV10 doesn't support alpha cursors */
1563 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1564 .dpms = nv_crtc_dpms,
1565 .save = nv_crtc_save, /* XXX */
1566 .restore = nv_crtc_restore, /* XXX */
1567 .mode_fixup = nv_crtc_mode_fixup,
1568 .mode_set = nv_crtc_mode_set,
1569 .prepare = nv_crtc_prepare,
1570 .commit = nv_crtc_commit,
1571 .destroy = NULL, /* XXX */
1572 .lock = nv_crtc_lock,
1573 .unlock = nv_crtc_unlock,
1574 .set_cursor_colors = nv_crtc_set_cursor_colors,
1575 .set_cursor_position = nv_crtc_set_cursor_position,
1576 .show_cursor = nv_crtc_show_cursor,
1577 .hide_cursor = nv_crtc_hide_cursor,
1578 .load_cursor_image = nv_crtc_load_cursor_image,
1581 /* NV11 and up has support for alpha cursors. */
1582 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1583 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1584 .dpms = nv_crtc_dpms,
1585 .save = nv_crtc_save, /* XXX */
1586 .restore = nv_crtc_restore, /* XXX */
1587 .mode_fixup = nv_crtc_mode_fixup,
1588 .mode_set = nv_crtc_mode_set,
1589 .prepare = nv_crtc_prepare,
1590 .commit = nv_crtc_commit,
1591 .destroy = NULL, /* XXX */
1592 .lock = nv_crtc_lock,
1593 .unlock = nv_crtc_unlock,
1594 .set_cursor_colors = nv_crtc_set_cursor_colors,
1595 .set_cursor_position = nv_crtc_set_cursor_position,
1596 .show_cursor = nv_crtc_show_cursor,
1597 .hide_cursor = nv_crtc_hide_cursor,
1598 .load_cursor_argb = nv_crtc_load_cursor_argb,
1603 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1605 NVPtr pNv = NVPTR(pScrn);
1607 NVCrtcPrivatePtr nv_crtc;
1609 if (pNv->NVArch >= 0x11) {
1610 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
1612 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
1617 nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1618 nv_crtc->crtc = crtc_num;
1619 nv_crtc->head = crtc_num;
1621 crtc->driver_private = nv_crtc;
1623 NVCrtcLockUnlock(crtc, 0);
1626 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1628 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1632 regp = &state->crtc_reg[nv_crtc->head];
1634 NVWriteMiscOut(crtc, regp->MiscOutReg);
1636 for (i = 1; i < 5; i++)
1637 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
1639 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1640 NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
1642 for (i = 0; i < 25; i++)
1643 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
1645 for (i = 0; i < 9; i++)
1646 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
1648 NVEnablePalette(crtc);
1649 for (i = 0; i < 21; i++)
1650 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
1651 NVDisablePalette(crtc);
1655 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
1657 /* TODO - implement this properly */
1658 ScrnInfoPtr pScrn = crtc->scrn;
1659 NVPtr pNv = NVPTR(pScrn);
1661 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
1662 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1663 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1667 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1669 ScrnInfoPtr pScrn = crtc->scrn;
1670 NVPtr pNv = NVPTR(pScrn);
1671 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1674 regp = &state->crtc_reg[nv_crtc->head];
1676 if(pNv->Architecture >= NV_ARCH_10) {
1678 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
1680 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1681 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1682 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1683 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1684 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1685 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1686 nvWriteMC(pNv, 0x1588, 0);
1688 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, 0xff);
1689 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1690 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1691 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
1692 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
1693 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
1694 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
1695 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
1697 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1698 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1700 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1701 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1702 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
1703 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1704 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1705 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
1706 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
1707 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
1708 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1709 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1712 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1713 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1714 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1715 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1716 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1717 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1718 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1719 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1720 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1721 if(pNv->Architecture >= NV_ARCH_30) {
1722 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1725 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1726 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1727 nv_crtc_fix_nv40_hw_cursor(crtc);
1728 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1729 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1731 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
1732 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1734 pNv->CurrentState = state;
1737 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1739 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1743 regp = &state->crtc_reg[nv_crtc->head];
1745 regp->MiscOutReg = NVReadMiscOut(crtc);
1747 for (i = 0; i < 25; i++)
1748 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
1750 NVEnablePalette(crtc);
1751 for (i = 0; i < 21; i++)
1752 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
1753 NVDisablePalette(crtc);
1755 for (i = 0; i < 9; i++)
1756 regp->Graphics[i] = NVReadVgaGr(crtc, i);
1758 for (i = 1; i < 5; i++)
1759 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
1763 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1765 ScrnInfoPtr pScrn = crtc->scrn;
1766 NVPtr pNv = NVPTR(pScrn);
1767 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1770 regp = &state->crtc_reg[nv_crtc->head];
1772 regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
1773 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
1774 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
1775 regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
1776 regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
1777 regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
1778 regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
1780 regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
1781 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
1782 if(pNv->Architecture >= NV_ARCH_30) {
1783 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
1785 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
1786 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
1787 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
1788 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
1790 regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
1791 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
1792 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
1793 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
1794 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
1796 if(pNv->Architecture >= NV_ARCH_10) {
1798 regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
1799 regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
1801 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
1803 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
1805 regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
1806 regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
1807 regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
1808 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
1809 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
1810 regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
1811 regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
1812 regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
1813 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
1814 regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
1815 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
1816 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
1821 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
1823 ScrnInfoPtr pScrn = crtc->scrn;
1824 NVPtr pNv = NVPTR(pScrn);
1825 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1826 NVFBLayout *pLayout = &pNv->CurrentLayout;
1829 ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
1831 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
1832 start += pNv->FB->offset;
1834 /* 30 bits addresses in 32 bits according to haiku */
1835 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
1837 /* set NV4/NV10 byte adress: (bit0 - 1) */
1838 NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
1844 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
1846 ScrnInfoPtr pScrn = crtc->scrn;
1847 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1848 NVPtr pNv = NVPTR(pScrn);
1849 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1851 NV_WR08(pDACReg, VGA_DAC_MASK, value);
1854 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
1856 ScrnInfoPtr pScrn = crtc->scrn;
1857 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1858 NVPtr pNv = NVPTR(pScrn);
1859 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1861 return NV_RD08(pDACReg, VGA_DAC_MASK);
1864 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
1866 ScrnInfoPtr pScrn = crtc->scrn;
1867 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1868 NVPtr pNv = NVPTR(pScrn);
1869 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1871 NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
1874 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
1876 ScrnInfoPtr pScrn = crtc->scrn;
1877 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1878 NVPtr pNv = NVPTR(pScrn);
1879 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1881 NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
1884 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
1886 ScrnInfoPtr pScrn = crtc->scrn;
1887 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1888 NVPtr pNv = NVPTR(pScrn);
1889 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1891 NV_WR08(pDACReg, VGA_DAC_DATA, value);
1894 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
1896 ScrnInfoPtr pScrn = crtc->scrn;
1897 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1898 NVPtr pNv = NVPTR(pScrn);
1899 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1901 return NV_RD08(pDACReg, VGA_DAC_DATA);
1904 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
1907 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1909 ScrnInfoPtr pScrn = crtc->scrn;
1910 NVPtr pNv = NVPTR(pScrn);
1912 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1914 NVCrtcSetOwner(crtc);
1915 NVCrtcWriteDacMask(crtc, 0xff);
1916 NVCrtcWriteDacWriteAddr(crtc, 0x00);
1918 for (i = 0; i<768; i++) {
1919 NVCrtcWriteDacData(crtc, regp->DAC[i]);
1921 NVDisablePalette(crtc);
1924 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
1928 NVCrtcSetOwner(crtc);
1930 scrn = NVReadVgaSeq(crtc, 0x01);
1937 NVVgaSeqReset(crtc, TRUE);
1938 NVWriteVgaSeq(crtc, 0x01, scrn);
1939 NVVgaSeqReset(crtc, FALSE);
1942 #endif /* ENABLE_RANDR12 */
1944 /*************************************************************************** \
1946 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
1948 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
1949 |* international laws. Users and possessors of this source code are *|
1950 |* hereby granted a nonexclusive, royalty-free copyright license to *|
1951 |* use this code in individual and commercial software. *|
1953 |* Any use of this source code must include, in the user documenta- *|
1954 |* tion and internal comments to the code, notices to the end user *|
1957 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
1959 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
1960 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
1961 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
1962 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
1963 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
1964 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
1965 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
1966 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
1967 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
1968 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
1969 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
1971 |* U.S. Government End Users. This source code is a "commercial *|
1972 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
1973 |* consisting of "commercial computer software" and "commercial *|
1974 |* computer software documentation," as such terms are used in *|
1975 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
1976 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
1977 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
1978 |* all U.S. Government End Users acquire the source code with only *|
1979 |* those rights set forth herein. *|
1981 \***************************************************************************/