2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
40 #include "mipointer.h"
41 #include "windowstr.h"
43 #include <X11/extensions/render.h>
46 #include "nv_include.h"
48 const char *OutputType[] = {
57 const char *MonTypeName[7] = {
68 * TMDS registers are indirect 8 bit registers.
69 * Reading is straightforward, writing a bit odd.
70 * Reading: Write adress (+write protect bit, do not forget this), then read value.
71 * Writing: Write adress (+write protect bit), write value, write adress again and write it again (+write protect bit).
74 void NVWriteTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg, CARD32 val)
76 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
77 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
79 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA, val & 0xff);
81 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL, tmds_reg & 0xff);
82 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
83 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
86 CARD8 NVReadTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg)
88 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
89 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
91 return (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA) & 0xff);
94 /* Two register sets exist, one (the one below) is barely used, so i'm lacking a good name */
96 void NVWriteTMDS2(NVPtr pNv, int ramdac, CARD32 tmds_reg, CARD32 val)
98 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2,
99 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE);
101 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA_2, val & 0xff);
103 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2, tmds_reg & 0xff);
104 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2,
105 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE);
108 CARD8 NVReadTMDS2(NVPtr pNv, int ramdac, CARD32 tmds_reg)
110 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2,
111 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE);
113 return (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA_2) & 0xff);
116 void NVOutputWriteTMDS(xf86OutputPtr output, CARD32 tmds_reg, CARD32 val)
118 NVOutputPrivatePtr nv_output = output->driver_private;
119 ScrnInfoPtr pScrn = output->scrn;
120 NVPtr pNv = NVPTR(pScrn);
122 /* We must write to the "bus" of the output */
123 NVWriteTMDS(pNv, nv_output->preferred_crtc, tmds_reg, val);
126 CARD8 NVOutputReadTMDS(xf86OutputPtr output, CARD32 tmds_reg)
128 NVOutputPrivatePtr nv_output = output->driver_private;
129 ScrnInfoPtr pScrn = output->scrn;
130 NVPtr pNv = NVPTR(pScrn);
132 /* We must read from the "bus" of the output */
133 return NVReadTMDS(pNv, nv_output->preferred_crtc, tmds_reg);
136 void NVOutputWriteTMDS2(xf86OutputPtr output, CARD32 tmds_reg, CARD32 val)
138 NVOutputPrivatePtr nv_output = output->driver_private;
139 ScrnInfoPtr pScrn = output->scrn;
140 NVPtr pNv = NVPTR(pScrn);
142 /* We must write to the "bus" of the output */
143 NVWriteTMDS2(pNv, nv_output->preferred_crtc, tmds_reg, val);
146 CARD8 NVOutputReadTMDS2(xf86OutputPtr output, CARD32 tmds_reg)
148 NVOutputPrivatePtr nv_output = output->driver_private;
149 ScrnInfoPtr pScrn = output->scrn;
150 NVPtr pNv = NVPTR(pScrn);
152 /* We must read from the "bus" of the output */
153 return NVReadTMDS2(pNv, nv_output->preferred_crtc, tmds_reg);
156 void NVOutputWriteRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg, CARD32 val)
158 NVOutputPrivatePtr nv_output = output->driver_private;
159 ScrnInfoPtr pScrn = output->scrn;
160 NVPtr pNv = NVPTR(pScrn);
162 nvWriteRAMDAC(pNv, nv_output->ramdac, ramdac_reg, val);
165 CARD32 NVOutputReadRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg)
167 NVOutputPrivatePtr nv_output = output->driver_private;
168 ScrnInfoPtr pScrn = output->scrn;
169 NVPtr pNv = NVPTR(pScrn);
171 return nvReadRAMDAC(pNv, nv_output->ramdac, ramdac_reg);
174 static void nv_output_backlight_enable(xf86OutputPtr output, Bool on)
176 ScrnInfoPtr pScrn = output->scrn;
177 NVPtr pNv = NVPTR(pScrn);
179 ErrorF("nv_output_backlight_enable is called for output %s to turn %s\n", output->name, on ? "on" : "off");
181 /* This is done differently on each laptop. Here we
182 * define the ones we know for sure. */
184 #if defined(__powerpc__)
185 if ((pNv->Chipset == 0x10DE0179) ||
186 (pNv->Chipset == 0x10DE0189) ||
187 (pNv->Chipset == 0x10DE0329)) {
188 /* NV17,18,34 Apple iMac, iBook, PowerBook */
189 CARD32 tmp_pmc, tmp_pcrt;
190 tmp_pmc = nvReadMC(pNv, 0x10F0) & 0x7FFFFFFF;
191 tmp_pcrt = nvReadCRTC0(pNv, NV_CRTC_081C) & 0xFFFFFFFC;
193 tmp_pmc |= (1 << 31);
196 nvWriteMC(pNv, 0x10F0, tmp_pmc);
197 nvWriteCRTC0(pNv, NV_CRTC_081C, tmp_pcrt);
201 if(pNv->twoHeads && ((pNv->Chipset & 0x0ff0) != CHIPSET_NV11))
202 nvWriteMC(pNv, 0x130C, on ? 3 : 7);
206 nv_lvds_output_dpms(xf86OutputPtr output, int mode)
208 NVOutputPrivatePtr nv_output = output->driver_private;
209 NVPtr pNv = NVPTR(output->scrn);
211 if (nv_output->ramdac != -1 && mode != DPMSModeOff) {
212 /* This was not a modeset, but a normal dpms call */
213 pNv->ramdac_active[nv_output->ramdac] = TRUE;
214 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
215 nv_output->ramdac_assigned = TRUE;
219 case DPMSModeStandby:
220 case DPMSModeSuspend:
222 nv_output_backlight_enable(output, 0);
225 nv_output_backlight_enable(output, 1);
230 /* We may be going for modesetting, so we must reset the ramdacs */
231 if (nv_output->ramdac != -1 && mode == DPMSModeOff) {
232 pNv->ramdac_active[nv_output->ramdac] = FALSE;
233 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
234 nv_output->ramdac_assigned = FALSE;
239 nv_analog_output_dpms(xf86OutputPtr output, int mode)
241 xf86CrtcPtr crtc = output->crtc;
242 NVOutputPrivatePtr nv_output = output->driver_private;
243 NVPtr pNv = NVPTR(output->scrn);
245 ErrorF("nv_analog_output_dpms is called with mode %d\n", mode);
247 if (nv_output->ramdac != -1) {
248 /* We may be going for modesetting, so we must reset the ramdacs */
249 if (mode == DPMSModeOff) {
250 pNv->ramdac_active[nv_output->ramdac] = FALSE;
251 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
252 nv_output->ramdac_assigned = FALSE;
253 /* This was not a modeset, but a normal dpms call */
255 pNv->ramdac_active[nv_output->ramdac] = TRUE;
256 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
257 nv_output->ramdac_assigned = TRUE;
262 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
264 ErrorF("nv_analog_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
269 nv_tmds_output_dpms(xf86OutputPtr output, int mode)
271 xf86CrtcPtr crtc = output->crtc;
272 NVOutputPrivatePtr nv_output = output->driver_private;
273 NVPtr pNv = NVPTR(output->scrn);
275 ErrorF("nv_tmds_output_dpms is called with mode %d\n", mode);
277 /* We just woke up again from an actual monitor dpms and not a modeset prepare */
278 /* Put here since we actually need our ramdac to wake up again ;-) */
279 if (nv_output->ramdac != -1 && mode != DPMSModeOff) {
280 pNv->ramdac_active[nv_output->ramdac] = TRUE;
281 nv_output->ramdac_assigned = TRUE;
282 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
285 /* Are we assigned a ramdac already?, else we will be activated during mode set */
286 if (crtc && nv_output->ramdac != -1) {
287 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
289 ErrorF("nv_tmds_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
291 CARD32 fpcontrol = nvReadRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_FP_CONTROL);
293 case DPMSModeStandby:
294 case DPMSModeSuspend:
296 /* cut the TMDS output */
297 fpcontrol |= 0x20000022;
300 /* disable cutting the TMDS output */
301 fpcontrol &= ~0x20000022;
304 nvWriteRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_FP_CONTROL, fpcontrol);
307 /* We may be going for modesetting, so we must reset the ramdacs */
308 if (nv_output->ramdac != -1 && mode == DPMSModeOff) {
309 pNv->ramdac_active[nv_output->ramdac] = FALSE;
310 nv_output->ramdac_assigned = FALSE;
311 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
315 /* This sequence is an optimized/shortened version of what the blob does */
316 uint32_t tmds_regs_nv40[] = { 0x04, 0x05, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x40, 0x43, 0x00, 0x01, 0x02, 0x2e, 0x2f, 0x3a, 0x2b };
317 uint32_t tmds_regs_nv30[] = { 0x04, 0x05, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x29, 0x2a, 0x00, 0x01, 0x02, 0x2e, 0x2f, 0x3a, 0x2b };
319 #define TMDS_REGS(index) ( tmds_regs(pNv, index) )
321 uint32_t tmds_regs(NVPtr pNv, int i)
323 if (pNv->Architecture == NV_ARCH_40) {
324 return tmds_regs_nv40[i];
326 return tmds_regs_nv30[i];
330 #define TMDS_SIZE ( tmds_size(pNv) )
332 uint32_t tmds_size(NVPtr pNv)
334 if (pNv->Architecture == NV_ARCH_40) {
335 return(sizeof(tmds_regs_nv40)/sizeof(tmds_regs_nv40[0]));
337 return(sizeof(tmds_regs_nv30)/sizeof(tmds_regs_nv30[0]));
341 /* Does anyone know the precise purpose of this second register set? */
342 uint32_t tmds2_regs_nv40[] = { 0x2b };
343 uint32_t tmds2_regs_nv30[] = { 0x2b };
345 #define TMDS2_REGS(index) ( tmds2_regs(pNv, index) )
347 uint32_t tmds2_regs(NVPtr pNv, int i)
349 if (pNv->Architecture == NV_ARCH_40) {
350 return tmds2_regs_nv40[i];
352 return tmds2_regs_nv30[i];
356 #define TMDS2_SIZE ( tmds2_size(pNv) )
358 uint32_t tmds2_size(NVPtr pNv)
360 if (pNv->Architecture == NV_ARCH_40) {
361 return(sizeof(tmds2_regs_nv40)/sizeof(tmds2_regs_nv40[0]));
363 return(sizeof(tmds2_regs_nv30)/sizeof(tmds2_regs_nv30[0]));
367 void nv_output_save_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
369 NVOutputPrivatePtr nv_output = output->driver_private;
370 ScrnInfoPtr pScrn = output->scrn;
371 NVPtr pNv = NVPTR(pScrn);
375 regp = &state->dac_reg[nv_output->ramdac];
376 state->config = nvReadFB(pNv, NV_PFB_CFG0);
378 /* This exists purely for proper text mode restore */
379 if (override) regp->output = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
381 for (i = 0; i < TMDS_SIZE; i++) {
382 regp->TMDS[TMDS_REGS(i)] = NVOutputReadTMDS(output, TMDS_REGS(i));
385 /* If the data ever changes between TMDS and TMDS2, then regp data needs a new set */
386 for (i = 0; i < TMDS2_SIZE; i++) {
387 regp->TMDS[TMDS2_REGS(i)] = NVOutputReadTMDS2(output, TMDS2_REGS(i));
391 void nv_output_load_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
393 NVOutputPrivatePtr nv_output = output->driver_private;
395 ScrnInfoPtr pScrn = output->scrn;
396 NVPtr pNv = NVPTR(pScrn);
399 regp = &state->dac_reg[nv_output->ramdac];
401 /* This exists purely for proper text mode restore */
402 if (override) NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, regp->output);
404 for (i = 0; i < TMDS_SIZE; i++) {
405 NVOutputWriteTMDS(output, TMDS_REGS(i), regp->TMDS[TMDS_REGS(i)]);
408 /* If the data ever changes between TMDS and TMDS2, then regp data needs a new set */
409 for (i = 0; i < TMDS2_SIZE; i++) {
410 NVOutputWriteTMDS(output, TMDS2_REGS(i), regp->TMDS[TMDS2_REGS(i)]);
414 /* NOTE: Don't rely on this data for anything other than restoring VT's */
417 nv_output_save (xf86OutputPtr output)
419 ScrnInfoPtr pScrn = output->scrn;
420 NVPtr pNv = NVPTR(pScrn);
421 RIVA_HW_STATE *state;
422 NVOutputPrivatePtr nv_output = output->driver_private;
423 int ramdac_backup = nv_output->ramdac;
425 ErrorF("nv_output_save is called\n");
427 /* This is early init and we have not yet been assigned a ramdac */
428 /* Always choose the prefered ramdac, for consistentcy */
429 /* Assumption: there is always once output that can only run of the primary ramdac */
430 if (nv_output->valid_ramdac & RAMDAC_1) {
431 nv_output->ramdac = 1;
433 nv_output->ramdac = 0;
436 state = &pNv->SavedReg;
438 /* Due to strange mapping of outputs we could have swapped analog and digital */
439 /* So we force save all the registers */
440 nv_output_save_state_ext(output, state, TRUE);
442 /* restore previous state */
443 nv_output->ramdac = ramdac_backup;
447 nv_output_restore (xf86OutputPtr output)
449 ScrnInfoPtr pScrn = output->scrn;
450 NVPtr pNv = NVPTR(pScrn);
451 RIVA_HW_STATE *state;
452 NVOutputPrivatePtr nv_output = output->driver_private;
453 int ramdac_backup = nv_output->ramdac;
455 ErrorF("nv_output_restore is called\n");
457 /* We want consistent mode restoring and the ramdac entry is variable */
458 /* Always choose the prefered ramdac, for consistentcy */
459 /* Assumption: there is always once output that can only run of the primary ramdac */
460 if (nv_output->valid_ramdac & RAMDAC_1) {
461 nv_output->ramdac = 1;
463 nv_output->ramdac = 0;
466 state = &pNv->SavedReg;
468 /* Due to strange mapping of outputs we could have swapped analog and digital */
469 /* So we force load all the registers */
470 nv_output_load_state_ext(output, state, TRUE);
472 /* restore previous state */
473 nv_output->ramdac = ramdac_backup;
477 nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
479 if (pMode->Flags & V_DBLSCAN)
480 return MODE_NO_DBLESCAN;
482 if (pMode->Clock > 400000 || pMode->Clock < 25000)
483 return MODE_CLOCK_RANGE;
490 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
491 DisplayModePtr adjusted_mode)
493 ErrorF("nv_output_mode_fixup is called\n");
499 nv_output_mode_set_regs(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
501 NVOutputPrivatePtr nv_output = output->driver_private;
502 ScrnInfoPtr pScrn = output->scrn;
503 NVPtr pNv = NVPTR(pScrn);
504 RIVA_HW_STATE *state, *sv_state;
506 Bool is_lvds = FALSE;
507 NVOutputRegPtr regp, regp2, savep;
508 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
511 xf86CrtcPtr crtc = output->crtc;
512 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
514 state = &pNv->ModeReg;
515 regp = &state->dac_reg[nv_output->ramdac];
516 /* The other ramdac */
517 regp2 = &state->dac_reg[(~(nv_output->ramdac)) & 1];
519 sv_state = &pNv->SavedReg;
520 savep = &sv_state->dac_reg[nv_output->ramdac];
522 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
524 if (nv_output->type == OUTPUT_LVDS) {
529 /* This is just a guess, there are probably more registers which need setting */
530 /* But we must start somewhere ;-) */
532 regp->TMDS[0x4] = 0x80;
533 /* Enable crosswired mode */
534 /* This will upset the monitor, trust me, i know it :-( */
535 /* Now allowed for non-bios inited systems */
536 //if (nv_output->ramdac != nv_output->preferred_ramdac) {
537 if (nv_crtc->head != nv_output->preferred_crtc) {
538 regp->TMDS[0x4] |= (1 << 3);
542 regp->TMDS[0x4] |= (1 << 0);
546 /* The TMDS game begins */
547 /* A few registers are also programmed on non-tmds monitors */
548 /* At the moment i can't give rationale for these values */
550 regp->TMDS[0x2b] = 0x7d;
552 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
553 uint32_t pll_setup_control = nvReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SETUP_CONTROL);
554 regp->TMDS[0x2b] = 0x7d;
555 regp->TMDS[0x2c] = 0x0;
556 /* Various combinations exist for lvds, 0x08, 0x48, 0xc8, 0x88 */
557 /* 0x88 seems most popular and (maybe) the end setting */
559 if (pNv->Architecture == NV_ARCH_40) {
560 regp->TMDS[0x2e] = 0x88;
562 /* observed on nv31m */
563 regp->TMDS[0x2e] = 0x0;
567 //if (nv_output->ramdac == nv_output->preferred_ramdac) {
568 if (nv_crtc->head == nv_output->preferred_crtc) {
569 regp->TMDS[0x2e] = 0x81;
571 regp->TMDS[0x2e] = 0x85;
574 /* 0x08 is also seen for lvds */
575 regp->TMDS[0x2f] = 0x21;
576 regp->TMDS[0x30] = 0x0;
577 regp->TMDS[0x31] = 0x0;
578 regp->TMDS[0x32] = 0x0;
579 regp->TMDS[0x33] = 0xf0;
580 regp->TMDS[0x3a] = 0x0;
582 /* Rarely the value 0x68 is used */
583 regp->TMDS[0x5] = 0x6e;
586 if (pNv->Architecture == NV_ARCH_40) {
587 regp->TMDS[0x0] = 0x60;
589 /* observed on a nv31m */
590 regp->TMDS[0x0] = 0x70;
593 /* This seems to be related to PLL_SETUP_CONTROL */
594 /* When PLL_SETUP_CONTROL ends with 0x1c, then this value is 0xcX */
596 if ((pll_setup_control & 0xff) == 0x1c) {
597 regp->TMDS[0x0] = 0xc0;
599 regp->TMDS[0x0] = 0xf0;
603 /* Not a 100% sure if this is not crtc determined */
604 if (nv_output->preferred_ramdac != nv_output->ramdac) {
605 regp->TMDS[0x0] |= 0xa;
607 regp->TMDS[0x0] |= 0x1;
610 /* Also seen: 0x47, what does this register do? */
611 if (nv_output->ramdac != nv_output->preferred_ramdac) {
612 regp->TMDS[0x1] = 0x42;
614 regp->TMDS[0x1] = 0x41;
618 regp->TMDS[0x2] = 0x0;
620 if (nv_output->preferred_crtc == 1) { /* bus */
621 regp->TMDS[0x2] = 0xa9;
623 regp->TMDS[0x2] = 0x89;
627 /* I assume they are zero for !is_lvds */
628 if (is_lvds && pNv->Architecture == NV_ARCH_40) {
629 /* Observed values are 0x11 and 0x14, TODO: this needs refinement */
630 regp->TMDS[0x40] = 0x14;
631 regp->TMDS[0x43] = 0xb0;
636 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
640 for (i = 0; i < config->num_output; i++) {
641 NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
643 /* is it this output ?? */
644 if (config->output[i] == output)
647 /* it the output connected */
648 if (config->output[i]->crtc == NULL)
652 if ((nv_output2->type == OUTPUT_ANALOG) && (nv_output->type == OUTPUT_ANALOG)) {
657 ErrorF("%d: crtc %d ramdac %d twocrt %d twomon %d\n", is_fp, nv_crtc->crtc, nv_output->ramdac, two_crt, two_mon);
662 nv_output_mode_set_routing(xf86OutputPtr output)
664 NVOutputPrivatePtr nv_output = output->driver_private;
665 xf86CrtcPtr crtc = output->crtc;
666 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
667 ScrnInfoPtr pScrn = output->scrn;
668 NVPtr pNv = NVPTR(pScrn);
672 uint32_t output_reg = nvReadRAMDAC(pNv, nv_output->preferred_ramdac, NV_RAMDAC_OUTPUT);
674 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
681 output_reg = NV_RAMDAC_OUTPUT_DAC_ENABLE;
684 if (nv_crtc->head == 1) {
685 output_reg |= NV_RAMDAC_OUTPUT_SELECT_CRTC1;
687 output_reg &= ~NV_RAMDAC_OUTPUT_SELECT_CRTC1;
690 if (nv_output->preferred_ramdac == 1) {
696 uint32_t output2_reg = nvReadRAMDAC(pNv, other, NV_RAMDAC_OUTPUT);
698 if (nv_crtc->head == 1) {
699 output2_reg &= ~NV_RAMDAC_OUTPUT_SELECT_CRTC1;
701 output2_reg |= NV_RAMDAC_OUTPUT_SELECT_CRTC1;
704 nvWriteRAMDAC(pNv, nv_output->preferred_ramdac, NV_RAMDAC_OUTPUT, output_reg);
705 nvWriteRAMDAC(pNv, other, NV_RAMDAC_OUTPUT, output2_reg);
707 /* This could use refinement for flatpanels, but it should work this way */
708 if (pNv->NVArch < 0x44) {
709 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, 0xf0000000);
710 nvWriteRAMDAC(pNv, 1, NV_RAMDAC_TEST_CONTROL, 0xf0000000);
711 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_670, 0xf0000000);
713 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, 0x00100000);
714 nvWriteRAMDAC(pNv, 1, NV_RAMDAC_TEST_CONTROL, 0x00100000);
715 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_670, 0x00100000);
720 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
721 DisplayModePtr adjusted_mode)
723 ScrnInfoPtr pScrn = output->scrn;
724 NVPtr pNv = NVPTR(pScrn);
725 RIVA_HW_STATE *state;
727 ErrorF("nv_output_mode_set is called\n");
729 state = &pNv->ModeReg;
731 nv_output_mode_set_regs(output, mode, adjusted_mode);
732 nv_output_load_state_ext(output, state, FALSE);
733 nv_output_mode_set_routing(output);
737 nv_get_edid(xf86OutputPtr output)
739 /* no use for shared DDC output */
740 NVOutputPrivatePtr nv_output = output->driver_private;
743 if (nv_output->pDDCBus == NULL)
746 ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
750 if (ddc_mon->features.input_type && (nv_output->type == OUTPUT_ANALOG))
753 if ((!ddc_mon->features.input_type) && (nv_output->type == OUTPUT_TMDS ||
754 nv_output->type == OUTPUT_LVDS))
765 nv_ddc_detect(xf86OutputPtr output)
767 xf86MonPtr m = nv_get_edid(output);
777 nv_crt_load_detect(xf86OutputPtr output)
779 ScrnInfoPtr pScrn = output->scrn;
780 NVOutputPrivatePtr nv_output = output->driver_private;
781 NVPtr pNv = NVPTR(pScrn);
782 CARD32 reg_output, reg_test_ctrl, temp;
783 Bool present = FALSE;
786 /* Usually these outputs are native to ramdac 1 */
787 if (nv_output->valid_ramdac & RAMDAC_0 && nv_output->valid_ramdac & RAMDAC_1) {
789 } else if (nv_output->valid_ramdac & RAMDAC_1) {
791 } else if (nv_output->valid_ramdac & RAMDAC_0) {
797 /* For some reason we get false positives on ramdac 1, maybe due tv-out? */
802 if (nv_output->pDDCBus != NULL) {
803 xf86MonPtr ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
804 /* Is there a digital flatpanel on this channel? */
805 if (ddc_mon && ddc_mon->features.input_type) {
810 reg_output = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT);
811 reg_test_ctrl = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL);
813 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, (reg_test_ctrl & ~0x00010000));
815 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, (reg_output & 0x0000FEEE));
818 temp = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT);
819 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, temp | 1);
821 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_DATA, 0x94050140);
822 temp = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL);
823 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
827 present = (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
829 temp = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
830 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
832 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, reg_output);
833 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, reg_test_ctrl);
836 ErrorF("A crt was detected on ramdac %d with no ddc support\n", ramdac);
843 static xf86OutputStatus
844 nv_tmds_output_detect(xf86OutputPtr output)
846 ErrorF("nv_tmds_output_detect is called\n");
848 if (nv_ddc_detect(output))
849 return XF86OutputStatusConnected;
851 return XF86OutputStatusDisconnected;
855 static xf86OutputStatus
856 nv_analog_output_detect(xf86OutputPtr output)
858 ErrorF("nv_analog_output_detect is called\n");
860 if (nv_ddc_detect(output))
861 return XF86OutputStatusConnected;
863 if (nv_crt_load_detect(output))
864 return XF86OutputStatusConnected;
866 return XF86OutputStatusDisconnected;
869 static DisplayModePtr
870 nv_output_get_modes(xf86OutputPtr output)
872 NVOutputPrivatePtr nv_output = output->driver_private;
874 DisplayModePtr ddc_modes;
876 ErrorF("nv_output_get_modes is called\n");
878 ddc_mon = nv_get_edid(output);
880 xf86OutputSetEDID(output, ddc_mon);
885 ddc_modes = xf86OutputGetEDIDModes (output);
887 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
891 for (i = 0; i < 4; i++) {
892 /* We only look at detailed timings atm */
893 if (ddc_mon->det_mon[i].type != DT)
895 /* Selecting only based on width ok? */
896 if (ddc_mon->det_mon[i].section.d_timings.h_active > nv_output->fpWidth) {
897 nv_output->fpWidth = ddc_mon->det_mon[i].section.d_timings.h_active;
898 nv_output->fpHeight = ddc_mon->det_mon[i].section.d_timings.v_active;
902 /* Add a native resolution mode that is preferred */
903 /* Reduced blanking should be fine on DVI monitor */
904 nv_output->native_mode = xf86CVTMode(nv_output->fpWidth, nv_output->fpHeight, 60.0, TRUE, FALSE);
905 nv_output->native_mode->type = M_T_DRIVER | M_T_PREFERRED;
906 /* We want the new mode to be preferred */
907 for (mode = ddc_modes; mode != NULL; mode = mode->next) {
908 if (mode->type & M_T_PREFERRED) {
909 mode->type &= ~M_T_PREFERRED;
912 ddc_modes = xf86ModesAdd(ddc_modes, nv_output->native_mode);
919 nv_output_destroy (xf86OutputPtr output)
921 ErrorF("nv_output_destroy is called\n");
922 if (output->driver_private)
923 xfree (output->driver_private);
927 nv_clear_ramdac_from_outputs(xf86OutputPtr output, int ramdac)
930 ScrnInfoPtr pScrn = output->scrn;
931 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
932 xf86OutputPtr output2;
933 NVOutputPrivatePtr nv_output2;
934 for (i = 0; i < xf86_config->num_output; i++) {
935 output2 = xf86_config->output[i];
936 nv_output2 = output2->driver_private;
937 if (nv_output2->ramdac == ramdac && output != output2) {
938 nv_output2->ramdac = -1;
939 nv_output2->ramdac_assigned = FALSE;
946 nv_output_prepare(xf86OutputPtr output)
948 ErrorF("nv_output_prepare is called\n");
949 NVOutputPrivatePtr nv_output = output->driver_private;
950 ScrnInfoPtr pScrn = output->scrn;
951 NVPtr pNv = NVPTR(pScrn);
952 Bool stole_ramdac = FALSE;
953 xf86OutputPtr output2 = NULL;
955 output->funcs->dpms(output, DPMSModeOff);
957 if (nv_output->ramdac_assigned) {
958 ErrorF("We already have a ramdac.\n");
962 /* We need ramdac 0, so let's steal it */
963 if (!(nv_output->valid_ramdac & RAMDAC_1) && pNv->ramdac_active[0]) {
964 ErrorF("Stealing ramdac0 ;-)\n");
966 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
967 NVOutputPrivatePtr nv_output2;
968 for (i = 0; i < xf86_config->num_output; i++) {
969 output2 = xf86_config->output[i];
970 nv_output2 = output2->driver_private;
971 if (nv_output2->ramdac == 0 && output != output2) {
972 nv_output2->ramdac = -1;
973 nv_output2->ramdac_assigned = FALSE;
977 pNv->ramdac_active[0] = FALSE;
981 /* We need ramdac 1, so let's steal it */
982 if (!(nv_output->valid_ramdac & RAMDAC_0) && pNv->ramdac_active[1]) {
983 ErrorF("Stealing ramdac1 ;-)\n");
985 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
986 NVOutputPrivatePtr nv_output2;
987 for (i = 0; i < xf86_config->num_output; i++) {
988 output2 = xf86_config->output[i];
989 nv_output2 = output2->driver_private;
990 if (nv_output2->ramdac == 1 && output != output2) {
991 nv_output2->ramdac = -1;
992 nv_output2->ramdac_assigned = FALSE;
996 pNv->ramdac_active[1] = FALSE;
1000 /* TODO: figure out what ramdac 2 is and how it is identified */
1002 /* At this point we already stole ramdac 0 or 1 if we need it */
1003 if (!pNv->ramdac_active[0] && (nv_output->valid_ramdac & RAMDAC_0)) {
1004 ErrorF("Activating ramdac %d\n", 0);
1005 pNv->ramdac_active[0] = TRUE;
1006 nv_output->ramdac = 0;
1008 ErrorF("Activating ramdac %d\n", 1);
1009 pNv->ramdac_active[1] = TRUE;
1010 nv_output->ramdac = 1;
1013 if (nv_output->ramdac != -1) {
1014 nv_output->ramdac_assigned = TRUE;
1015 nv_clear_ramdac_from_outputs(output, nv_output->ramdac);
1019 ErrorF("Resetting the stolen ramdac\n");
1020 DisplayModePtr adjusted_mode = xf86DuplicateMode(&(output2->crtc->desiredMode));
1021 xf86CrtcPtr crtc2 = output2->crtc;
1022 /* Assign a ramdac */
1023 output2->funcs->prepare(output2);
1024 /* We must set the vpll's to ensure they are properly set */
1025 crtc2->funcs->mode_fixup(crtc2, &(crtc2->desiredMode), adjusted_mode);
1026 crtc2->funcs->mode_set(crtc2, &(crtc2->desiredMode), adjusted_mode, crtc2->x, crtc2->y);
1027 output2->funcs->mode_set(output2, &(crtc2->desiredMode), adjusted_mode);
1028 /* Anyone know were this mode is stored, so we don't accidentally wake up a screen that is DPMSModeOff? */
1029 crtc2->funcs->dpms(crtc2, DPMSModeOn);
1030 xfree(adjusted_mode);
1035 nv_output_commit(xf86OutputPtr output)
1037 ErrorF("nv_output_commit is called\n");
1039 output->funcs->dpms(output, DPMSModeOn);
1042 static const xf86OutputFuncsRec nv_analog_output_funcs = {
1043 .dpms = nv_analog_output_dpms,
1044 .save = nv_output_save,
1045 .restore = nv_output_restore,
1046 .mode_valid = nv_output_mode_valid,
1047 .mode_fixup = nv_output_mode_fixup,
1048 .mode_set = nv_output_mode_set,
1049 .detect = nv_analog_output_detect,
1050 .get_modes = nv_output_get_modes,
1051 .destroy = nv_output_destroy,
1052 .prepare = nv_output_prepare,
1053 .commit = nv_output_commit,
1056 static const xf86OutputFuncsRec nv_tmds_output_funcs = {
1057 .dpms = nv_tmds_output_dpms,
1058 .save = nv_output_save,
1059 .restore = nv_output_restore,
1060 .mode_valid = nv_output_mode_valid,
1061 .mode_fixup = nv_output_mode_fixup,
1062 .mode_set = nv_output_mode_set,
1063 .detect = nv_tmds_output_detect,
1064 .get_modes = nv_output_get_modes,
1065 .destroy = nv_output_destroy,
1066 .prepare = nv_output_prepare,
1067 .commit = nv_output_commit,
1070 static int nv_lvds_output_mode_valid
1071 (xf86OutputPtr output, DisplayModePtr pMode)
1073 NVOutputPrivatePtr nv_output = output->driver_private;
1075 /* No modes > panel's native res */
1076 if (pMode->HDisplay > nv_output->fpWidth || pMode->VDisplay > nv_output->fpHeight)
1079 return nv_output_mode_valid(output, pMode);
1082 static xf86OutputStatus
1083 nv_lvds_output_detect(xf86OutputPtr output)
1085 ScrnInfoPtr pScrn = output->scrn;
1086 NVPtr pNv = NVPTR(pScrn);
1088 if (pNv->fp_native_mode || nv_ddc_detect(output))
1089 return XF86OutputStatusConnected;
1091 return XF86OutputStatusDisconnected;
1094 static DisplayModePtr
1095 nv_lvds_output_get_modes(xf86OutputPtr output)
1097 ScrnInfoPtr pScrn = output->scrn;
1098 NVPtr pNv = NVPTR(pScrn);
1099 NVOutputPrivatePtr nv_output = output->driver_private;
1100 DisplayModePtr modes;
1102 if ((modes = nv_output_get_modes(output)))
1105 /* it is possible to set up a mode from what we can read from the
1106 * RAMDAC registers, but if we can't read the BIOS table correctly
1107 * we might as well give up */
1108 if (pNv->fp_native_mode == NULL)
1111 nv_output->fpWidth = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HDISP_END) + 1;
1112 nv_output->fpHeight = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VDISP_END) + 1;
1113 nv_output->fpSyncs = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL) & 0x30000033;
1115 if (pNv->fp_native_mode->HDisplay != nv_output->fpWidth ||
1116 pNv->fp_native_mode->VDisplay != nv_output->fpHeight) {
1117 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1118 "Panel size mismatch; ignoring RAMDAC\n");
1119 nv_output->fpWidth = pNv->fp_native_mode->HDisplay;
1120 nv_output->fpHeight = pNv->fp_native_mode->VDisplay;
1123 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Panel size is %u x %u\n",
1124 nv_output->fpWidth, nv_output->fpHeight);
1126 nv_output->native_mode = xf86DuplicateMode(pNv->fp_native_mode);
1128 return xf86DuplicateMode(pNv->fp_native_mode);
1131 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
1132 .dpms = nv_lvds_output_dpms,
1133 .save = nv_output_save,
1134 .restore = nv_output_restore,
1135 .mode_valid = nv_lvds_output_mode_valid,
1136 .mode_fixup = nv_output_mode_fixup,
1137 .mode_set = nv_output_mode_set,
1138 .detect = nv_lvds_output_detect,
1139 .get_modes = nv_lvds_output_get_modes,
1140 .destroy = nv_output_destroy,
1141 .prepare = nv_output_prepare,
1142 .commit = nv_output_commit,
1145 static void nv_add_analog_output(ScrnInfoPtr pScrn, int heads, int order, int bus, int i2c_index, Bool dvi_pair)
1147 NVPtr pNv = NVPTR(pScrn);
1148 xf86OutputPtr output;
1149 NVOutputPrivatePtr nv_output;
1150 char outputname[20];
1151 Bool create_output = TRUE;
1153 /* DVI have an analog connector and a digital one, differentiate between that and a normal vga */
1155 sprintf(outputname, "DVI-A-%d", pNv->dvi_a_count);
1158 sprintf(outputname, "VGA-%d", pNv->vga_count);
1162 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1167 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1168 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1170 nv_output->type = OUTPUT_ANALOG;
1173 * bit0: RAMDAC_0 valid
1174 * bit1: RAMDAC_1 valid
1175 * So lowest order has highest priority.
1176 * Below is guesswork:
1177 * bit2: All ramdac's valid?
1178 * FIXME: this probably wrong
1180 nv_output->valid_ramdac = order;
1182 if (!create_output) {
1187 /* Delay creation of output until we actually know we want it */
1188 output = xf86OutputCreate (pScrn, &nv_analog_output_funcs, outputname);
1192 output->driver_private = nv_output;
1194 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1196 nv_output->ramdac = -1;
1198 nv_output->preferred_crtc = bus;
1200 /* This is only to facilitate proper output routing for dvi */
1201 /* See sel_clk assignment in nv_crtc.c */
1202 if (order & RAMDAC_1) {
1203 nv_output->preferred_ramdac = 1;
1205 nv_output->preferred_ramdac = 0;
1208 output->possible_crtcs = heads;
1209 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1212 static void nv_add_digital_output(ScrnInfoPtr pScrn, int heads, int order, int bus, int i2c_index, int lvds)
1214 NVPtr pNv = NVPTR(pScrn);
1215 xf86OutputPtr output;
1216 NVOutputPrivatePtr nv_output;
1217 char outputname[20];
1218 Bool create_output = TRUE;
1221 sprintf(outputname, "LVDS-%d", pNv->lvds_count);
1224 sprintf(outputname, "DVI-D-%d", pNv->dvi_d_count);
1228 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1234 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1235 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1237 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1240 * bit0: RAMDAC_0 valid
1241 * bit1: RAMDAC_1 valid
1242 * So lowest order has highest priority.
1243 * Below is guesswork:
1244 * bit2: All ramdac's valid?
1245 * FIXME: this probably wrong
1247 nv_output->valid_ramdac = order;
1250 nv_output->type = OUTPUT_LVDS;
1251 /* comment below two lines to test LVDS under RandR12.
1252 * If your screen "blooms" or "bleeds" (i.e. has a developing
1253 * white / psychedelic pattern) then KILL X IMMEDIATELY
1254 * (ctrl+alt+backspace) & if the effect continues reset power */
1255 ErrorF("Output refused because we don't accept LVDS at the moment.\n");
1256 create_output = FALSE;
1258 nv_output->type = OUTPUT_TMDS;
1261 if (!create_output) {
1266 /* Delay creation of output until we are certain is desirable */
1268 output = xf86OutputCreate (pScrn, &nv_lvds_output_funcs, outputname);
1270 output = xf86OutputCreate (pScrn, &nv_tmds_output_funcs, outputname);
1274 output->driver_private = nv_output;
1276 nv_output->ramdac = -1;
1278 nv_output->preferred_crtc = bus;
1280 /* This is only to facilitate proper output routing for dvi */
1281 /* See sel_clk assignment in nv_crtc.c */
1282 if (order & RAMDAC_1) {
1283 nv_output->preferred_ramdac = 1;
1285 nv_output->preferred_ramdac = 0;
1288 output->possible_crtcs = heads;
1289 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1292 void NvDCBSetupOutputs(ScrnInfoPtr pScrn)
1294 unsigned char type, i2c_index, or, heads, bus;
1295 NVPtr pNv = NVPTR(pScrn);
1296 int i, bus_count[0xf];
1298 memset(bus_count, 0, sizeof(bus_count));
1299 for (i = 0 ; i < pNv->dcb_table.entries; i++)
1300 bus_count[pNv->dcb_table.entry[i].bus]++;
1302 /* we setup the outputs up from the BIOS table */
1303 for (i = 0 ; i < pNv->dcb_table.entries; i++) {
1304 type = pNv->dcb_table.entry[i].type;
1305 i2c_index = pNv->dcb_table.entry[i].i2c_index;
1306 or = ffs(pNv->dcb_table.entry[i].or);
1307 heads = pNv->dcb_table.entry[i].head;
1308 bus = pNv->dcb_table.entry[i].bus;
1311 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", type);
1315 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DCB entry %d: type: %d, i2c_index: %d, head: %d, bus: %d, or: %d\n", i, type, i2c_index, heads, bus, or);
1319 nv_add_analog_output(pScrn, heads, or, bus, i2c_index, (bus_count[bus] > 1));
1322 nv_add_digital_output(pScrn, heads, or, bus, i2c_index, 0);
1325 nv_add_digital_output(pScrn, heads, or, bus, i2c_index, 1);
1333 void NvSetupOutputs(ScrnInfoPtr pScrn)
1335 NVPtr pNv = NVPTR(pScrn);
1337 pNv->Television = FALSE;
1339 memset(pNv->pI2CBus, 0, sizeof(pNv->pI2CBus));
1340 NvDCBSetupOutputs(pScrn);
1343 /*************************************************************************** \
1345 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
1347 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
1348 |* international laws. Users and possessors of this source code are *|
1349 |* hereby granted a nonexclusive, royalty-free copyright license to *|
1350 |* use this code in individual and commercial software. *|
1352 |* Any use of this source code must include, in the user documenta- *|
1353 |* tion and internal comments to the code, notices to the end user *|
1356 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
1358 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
1359 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
1360 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
1361 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
1362 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
1363 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
1364 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
1365 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
1366 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
1367 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
1368 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
1370 |* U.S. Government End Users. This source code is a "commercial *|
1371 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
1372 |* consisting of "commercial computer software" and "commercial *|
1373 |* computer software documentation," as such terms are used in *|
1374 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
1375 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
1376 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
1377 |* all U.S. Government End Users acquire the source code with only *|
1378 |* those rights set forth herein. *|
1380 \***************************************************************************/