2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "nv_include.h"
28 /* FIXME: put these somewhere */
29 #define CRTC_INDEX_COLOR 0x3d4
30 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
31 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
32 #define NV_PBUS_PCI_NV_19 0x0000184C
33 #define NV_PRAMIN_ROM_OFFSET 0x00700000
41 static int crtchead = 0;
48 static uint16_t le16_to_cpu(const uint16_t x)
50 #if X_BYTE_ORDER == X_BIG_ENDIAN
57 static uint32_t le32_to_cpu(const uint32_t x)
59 #if X_BYTE_ORDER == X_BIG_ENDIAN
66 static Bool nv_cksum(const uint8_t *data, unsigned int length)
68 /* there's a few checksums in the BIOS, so here's a generic checking function */
72 for (i = 0; i < length; i++)
81 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
83 /* check for BIOS signature */
84 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
85 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
86 "... BIOS signature not found\n");
90 if (nv_cksum(data, data[2] * 512)) {
91 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
92 "... BIOS checksum invalid\n");
93 /* probably ought to set a do_not_execute flag for table parsing here,
94 * assuming most BIOSen are valid */
97 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
102 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
104 NVPtr pNv = NVPTR(pScrn);
107 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
108 "Attempting to locate BIOS image in PROM\n");
110 /* enable ROM access */
111 nvWriteMC(pNv, 0x1850, 0x0);
112 for (i = 0; i < NV_PROM_SIZE; i++) {
113 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
114 data[i] = pNv->PROM[i];
115 data[i] = pNv->PROM[i];
116 data[i] = pNv->PROM[i];
117 data[i] = pNv->PROM[i];
118 data[i] = pNv->PROM[i];
120 /* disable ROM access */
121 nvWriteMC(pNv, 0x1850, 0x1);
124 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint32_t *data)
126 NVPtr pNv = NVPTR(pScrn);
127 const uint32_t *pramin = (uint32_t *)&pNv->REGS[NV_PRAMIN_ROM_OFFSET/4];
128 uint32_t old_bar0_pramin = 0;
130 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
131 "Attempting to locate BIOS image in PRAMIN\n");
133 if (pNv->Architecture >= NV_ARCH_50) {
136 vbios_vram = (pNv->REGS[0x619f04/4] & ~0xff) << 8;
138 vbios_vram = pNv->REGS[0x1700/4] << 16;
139 vbios_vram += 0xf0000;
142 old_bar0_pramin = pNv->REGS[0x1700/4];
143 pNv->REGS[0x1700/4] = vbios_vram >> 16;
146 memcpy(data, pramin, NV_PROM_SIZE);
148 if (pNv->Architecture >= NV_ARCH_50) {
149 pNv->REGS[0x1700/4] = old_bar0_pramin;
153 static Bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
155 NVShadowVBIOS_PROM(pScrn, data);
156 if (NVValidVBIOS(pScrn, data) == 2)
159 NVShadowVBIOS_PRAMIN(pScrn, (uint32_t *)data);
160 if (NVValidVBIOS(pScrn, data))
171 int length_multiplier;
172 Bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
181 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
183 #define MACRO_INDEX_SIZE 2
185 #define CONDITION_SIZE 12
186 #define IO_FLAG_CONDITION_SIZE 9
194 static int nv_valid_reg(uint32_t reg)
196 #define WITHIN(x,y,z) ((x>=y)&&(x<y+z))
197 if (WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
199 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE))
201 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE))
203 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
205 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
207 if (WITHIN(reg,NV_PGRAPH_OFFSET,NV_PGRAPH_SIZE))
209 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
211 if (WITHIN(reg,NV_PTIMER_OFFSET,NV_PTIMER_SIZE))
213 if (WITHIN(reg,NV_PVIDEO_OFFSET,NV_PVIDEO_SIZE))
215 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
217 if (WITHIN(reg,NV_FIFO_OFFSET,NV_FIFO_SIZE))
219 if (WITHIN(reg,NV_PCIO0_OFFSET,NV_PCIO0_SIZE))
221 if (WITHIN(reg,NV_PDIO0_OFFSET,NV_PDIO0_SIZE))
223 if (WITHIN(reg,NV_PVIO_OFFSET,NV_PVIO_SIZE))
225 if (WITHIN(reg,NV_PROM_OFFSET,NV_PROM_SIZE))
227 if (WITHIN(reg,NV_PRAMIN_ROM_OFFSET,NV_PROM_SIZE))
233 static void nv32_rd(ScrnInfoPtr pScrn, uint32_t reg, uint32_t *data)
235 NVPtr pNv = NVPTR(pScrn);
237 if (!nv_valid_reg(reg)) {
238 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
239 "========= unknown reg 0x%08X ==========\n", reg);
242 *data = pNv->REGS[reg/4];
244 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
245 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, *data);
248 static int nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
250 NVPtr pNv = NVPTR(pScrn);
251 if (DEBUGLEVEL >= 8) {
253 nv32_rd(pScrn, reg, &tmp);
256 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
257 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
258 if (!nv_valid_reg(reg)) {
259 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
260 "========= unknown reg 0x%08X ==========\n", reg);
264 if (pNv->VBIOS.execute) {
266 NVPtr pNv = NVPTR(pScrn);
267 pNv->REGS[reg/4] = data;
273 static void nv_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t *data)
275 NVPtr pNv = NVPTR(pScrn);
276 volatile uint8_t *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
278 VGA_WR08(ptr, port, index);
279 *data = VGA_RD08(ptr, port + 1);
282 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
283 " Indexed read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
284 port, index, crtchead, *data);
287 static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
289 NVPtr pNv = NVPTR(pScrn);
290 volatile uint8_t *ptr;
292 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
294 ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
296 if (DEBUGLEVEL >= 8) {
298 nv_port_rd(pScrn, port, index, &tmp);
301 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
302 " Indexed write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
303 port, index, crtchead, data);
305 if (pNv->VBIOS.execute) {
307 VGA_WR08(ptr, port, index);
308 VGA_WR08(ptr, port + 1, data);
311 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
315 static Bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
317 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
318 * for the CRTC index; 1 byte for the mask to apply to the value
319 * retrieved from the CRTC; 1 byte for the shift right to apply to the
320 * masked CRTC value; 2 bytes for the offset to the flag array, to
321 * which the shifted value is added; 1 byte for the mask applied to the
322 * value read from the flag array; and 1 byte for the value to compare
323 * against the masked byte from the flag table.
326 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
327 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
328 uint8_t crtcindex = bios->data[condptr + 2];
329 uint8_t mask = bios->data[condptr + 3];
330 uint8_t shift = bios->data[condptr + 4];
331 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
332 uint8_t flagarraymask = bios->data[condptr + 7];
333 uint8_t cmpval = bios->data[condptr + 8];
337 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
338 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
339 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
341 nv_port_rd(pScrn, crtcport, crtcindex, &data);
343 data = bios->data[flagarray + ((data & mask) >> shift)];
344 data &= flagarraymask;
347 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
348 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
349 offset, data, cmpval);
357 static Bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
359 /* INIT_PROG opcode: 0x31
361 * offset (8 bit): opcode
362 * offset + 1 (32 bit): reg
363 * offset + 5 (32 bit): and mask
364 * offset + 9 (8 bit): shift right
365 * offset + 10 (8 bit): number of configurations
366 * offset + 11 (32 bit): register
367 * offset + 15 (32 bit): configuration 1
370 * Starting at offset + 15 there are "number of configurations"
371 * 32 bit values. To find out which configuration value to use
372 * read "CRTC reg" on the CRTC controller with index "CRTC index"
373 * and bitwise AND this value with "and mask" and then bit shift the
374 * result "shift right" bits to the right.
375 * Assign "register" with appropriate configuration value.
378 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
379 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
380 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
381 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
382 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
384 CARD32 configval, tmp;
386 if (iexec->execute) {
387 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
390 nv32_rd(pScrn, reg, &tmp);
391 configuration = (tmp & and) >> shiftr;
393 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
394 offset, configuration);
396 if (configuration <= nr) {
399 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
401 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
404 nv32_rd(pScrn, reg2, &tmp);
405 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
407 nv32_wr(pScrn, reg2, configval);
413 static Bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
415 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
417 * offset (8 bit): opcode
418 * offset + 1 (16 bit): CRTC port
419 * offset + 3 (8 bit): CRTC index
420 * offset + 4 (8 bit): mask
421 * offset + 5 (8 bit): shift
422 * offset + 6 (8 bit): count
423 * offset + 7 (32 bit): register
424 * offset + 11 (32 bit): configuration 1
427 * Starting at offset + 11 there are "count" 32 bit values.
428 * To find out which value to use read index "CRTC index" on "CRTC port",
429 * AND this value with "mask" and then bit shift right "shift" bits.
430 * Read the appropriate value using this index and write to "register"
433 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
434 uint8_t crtcindex = bios->data[offset + 3];
435 uint8_t mask = bios->data[offset + 4];
436 uint8_t shift = bios->data[offset + 5];
437 uint8_t count = bios->data[offset + 6];
438 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
446 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
447 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
448 offset, crtcport, crtcindex, mask, shift, count, reg);
450 nv_port_rd(pScrn, crtcport, crtcindex, &config);
451 config = (config & mask) >> shift;
452 if (config > count) {
453 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
454 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
455 offset, config, count);
459 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
462 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
463 "0x%04X: Writing config %02X\n", offset, config);
465 nv32_wr(pScrn, reg, configval);
470 static Bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
472 /* INIT_REPEAT opcode: 0x33 ('3')
474 * offset (8 bit): opcode
475 * offset + 1 (8 bit): count
477 * Execute script following this opcode up to INIT_REPEAT_END
481 uint8_t count = bios->data[offset + 1];
484 /* no iexec->execute check by design */
486 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
487 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES.\n",
490 iexec->repeat = TRUE;
492 /* count - 1, as the script block will execute once when we leave this
493 * opcode -- this is compatible with bios behaviour as:
494 * a) the block is always executed at least once, even if count == 0
495 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
498 for (i = 0; i < count - 1; i++)
499 parse_init_table(pScrn, bios, offset + 2, iexec);
501 iexec->repeat = FALSE;
506 static Bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
508 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
510 * offset (8 bit): opcode
511 * offset + 1 (16 bit): CRTC port
512 * offset + 3 (8 bit): CRTC index
513 * offset + 4 (8 bit): mask
514 * offset + 5 (8 bit): shift
515 * offset + 6 (8 bit): IO flag condition index
516 * offset + 7 (8 bit): count
517 * offset + 8 (32 bit): register
518 * offset + 12 (16 bit): frequency 1
521 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
522 * Set PLL register "register" to coefficients for frequency n,
523 * selected by reading index "CRTC index" of "CRTC port" ANDed with
524 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
525 * and condition met, double frequency before setting it.
528 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
529 uint8_t crtcindex = bios->data[offset + 3];
530 uint8_t mask = bios->data[offset + 4];
531 uint8_t shift = bios->data[offset + 5];
532 int8_t io_flag_condition_idx = bios->data[offset + 6];
533 uint8_t count = bios->data[offset + 7];
534 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
542 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
543 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
544 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
546 nv_port_rd(pScrn, crtcport, crtcindex, &config);
547 config = (config & mask) >> shift;
548 if (config > count) {
549 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
550 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
551 offset, config, count);
555 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
557 if (io_flag_condition_idx > 0) {
558 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
559 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
560 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
563 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
564 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
568 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
569 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
570 offset, reg, config, freq);
572 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
577 configval = 0x01014E07;
580 configval = 0x13030E02;
587 static Bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
589 /* INIT_END_REPEAT opcode: 0x36 ('6')
591 * offset (8 bit): opcode
593 * Marks the end of the block for INIT_REPEAT to repeat
596 /* no iexec->execute check by design */
598 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
599 * we're not in repeat mode
607 static Bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
609 /* INIT_COPY opcode: 0x37 ('7')
611 * offset (8 bit): opcode
612 * offset + 1 (32 bit): register
613 * offset + 5 (8 bit): shift
614 * offset + 6 (8 bit): srcmask
615 * offset + 7 (16 bit): CRTC port
616 * offset + 9 (8 bit): CRTC index
617 * offset + 10 (8 bit): mask
619 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
620 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
623 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
624 uint8_t shift = bios->data[offset + 5];
625 uint8_t srcmask = bios->data[offset + 6];
626 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
627 uint8_t crtcindex = bios->data[offset + 9];
628 uint8_t mask = bios->data[offset + 10];
636 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
637 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
638 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
640 nv32_rd(pScrn, reg, &data);
645 data <<= (0x100 - shift);
649 nv_port_rd(pScrn, crtcport, crtcindex, &crtcdata);
650 crtcdata = (crtcdata & mask) | (uint8_t)data;
651 nv_port_wr(pScrn, crtcport, crtcindex, crtcdata);
656 static Bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
658 /* INIT_NOT opcode: 0x38 ('8')
660 * offset (8 bit): opcode
662 * Invert the current execute / no-execute condition (i.e. "else")
665 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
666 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
668 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
669 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
671 iexec->execute = !iexec->execute;
675 static Bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
677 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
679 * offset (8 bit): opcode
680 * offset + 1 (8 bit): condition number
682 * Check condition "condition number" in the IO flag condition table.
683 * If condition not met skip subsequent opcodes until condition
684 * is inverted (INIT_NOT), or we hit INIT_RESUME
687 uint8_t cond = bios->data[offset + 1];
692 if (io_flag_condition(pScrn, bios, offset, cond))
693 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
694 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
696 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
697 "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
698 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
699 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
700 iexec->execute = FALSE;
706 Bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
708 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
710 * offset (8 bit): opcode
711 * offset + 1 (32 bit): control register
712 * offset + 5 (32 bit): data register
713 * offset + 9 (32 bit): mask
714 * offset + 13 (32 bit): data
715 * offset + 17 (8 bit): count
716 * offset + 18 (8 bit): address 1
717 * offset + 19 (8 bit): data 1
720 * For each of "count" address and data pairs, write "data n" to "data register",
721 * read the current value of "control register", and write it back once ANDed
722 * with "mask", ORed with "data", and ORed with "address n"
725 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
726 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
727 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
728 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
729 uint8_t count = bios->data[offset + 17];
737 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
738 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
739 offset, controlreg, datareg, mask, data, count);
741 for (i = 0; i < count; i++) {
742 uint8_t instaddress = bios->data[offset + 18 + i * 2];
743 uint8_t instdata = bios->data[offset + 19 + i * 2];
746 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
747 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
749 nv32_wr(pScrn, datareg, instdata);
751 nv32_rd(pScrn, controlreg, &value);
752 value = (value & mask) | data | instaddress;
754 nv32_wr(pScrn, controlreg, value);
760 static Bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
762 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
764 * offset (8 bit): opcode
765 * offset + 1 (16 bit): CRTC port
766 * offset + 3 (8 bit): CRTC index
767 * offset + 4 (8 bit): mask
768 * offset + 5 (8 bit): shift
769 * offset + 6 (8 bit): count
770 * offset + 7 (32 bit): register
771 * offset + 11 (32 bit): frequency 1
774 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
775 * Set PLL register "register" to coefficients for frequency n,
776 * selected by reading index "CRTC index" of "CRTC port" ANDed with
777 * "mask" and shifted right by "shift".
780 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
781 uint8_t crtcindex = bios->data[offset + 3];
782 uint8_t mask = bios->data[offset + 4];
783 uint8_t shift = bios->data[offset + 5];
784 uint8_t count = bios->data[offset + 6];
785 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
793 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
794 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
795 offset, crtcport, crtcindex, mask, shift, count, reg);
800 nv_port_rd(pScrn, crtcport, crtcindex, &config);
801 config = (config & mask) >> shift;
802 if (config > count) {
803 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
804 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
805 offset, config, count);
809 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
812 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
813 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
814 offset, reg, config, freq);
816 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
821 static Bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
823 /* INIT_PLL2 opcode: 0x4B ('K')
825 * offset (8 bit): opcode
826 * offset + 1 (32 bit): register
827 * offset + 5 (32 bit): freq
829 * Set PLL register "register" to coefficients for frequency "freq"
832 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
833 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
839 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
840 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
843 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
848 Bool init_50(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
850 /* INIT_50 opcode: 0x50 ('P')
852 * offset (8 bit): opcode
853 * offset + 1 (8 bit): magic lookup value
854 * offset + 2 (8 bit): count
855 * offset + 3 (8 bit): addr 1
856 * offset + 4 (8 bit): data 1
859 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
860 * "magic lookup value" (mlv) determines which TMDS base address is used:
861 * For mlv < 80, it is an index into a table of TMDS base addresses
862 * For mlv == 80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
863 * to index a table of offsets to the basic 0x6808b0 address
864 * For mlv == 81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
865 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
867 NVPtr pNv = NVPTR(pScrn);
868 uint8_t mlv = bios->data[offset + 1];
869 uint8_t count = bios->data[offset + 2];
873 int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
874 uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
880 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
881 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
884 /* here we assume that the DCB table has already been parsed */
887 nv_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
888 nv_port_rd(pScrn, CRTC_INDEX_COLOR, 0x58, &dcb_entry);
889 if (dcb_entry > pNv->dcb_table.entries) {
890 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
891 "0x%04X: CR58 doesn't have a valid DCB entry currently (%02X)\n",
895 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
898 reg = 0x6808b0 + dacoffset;
900 reg = pramdac_table[mlv];
902 for (i = 0; i < count; i++) {
903 uint8_t tmds_addr = bios->data[offset + 3 + i * 2];
904 uint8_t tmds_data = bios->data[offset + 4 + i * 2];
906 nv32_wr(pScrn, reg + 4, tmds_data);
907 nv32_wr(pScrn, reg, tmds_addr);
913 Bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
915 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
917 * offset (8 bit): opcode
918 * offset + 1 (8 bit): CRTC index1
919 * offset + 2 (8 bit): CRTC index2
920 * offset + 3 (8 bit): baseaddr
921 * offset + 4 (8 bit): count
922 * offset + 5 (8 bit): data 1
925 * For each of "count" address and data pairs, write "baseaddr + n" to
926 * "CRTC index1" and "data n" to "CRTC index2"
927 * Once complete, restore initial value read from "CRTC index1"
929 uint8_t crtcindex1 = bios->data[offset + 1];
930 uint8_t crtcindex2 = bios->data[offset + 2];
931 uint8_t baseaddr = bios->data[offset + 3];
932 uint8_t count = bios->data[offset + 4];
933 uint8_t oldaddr, data;
940 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
941 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
942 offset, crtcindex1, crtcindex2, baseaddr, count);
944 nv_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1, &oldaddr);
946 for (i = 0; i < count; i++) {
947 nv_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
949 data = bios->data[offset + 5 + i];
950 nv_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
953 nv_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
958 Bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
960 /* INIT_CR opcode: 0x52 ('R')
962 * offset (8 bit): opcode
963 * offset + 1 (8 bit): CRTC index
964 * offset + 2 (8 bit): mask
965 * offset + 3 (8 bit): data
967 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
968 * back to "CRTC index"
971 uint8_t crtcindex = bios->data[offset + 1];
972 uint8_t mask = bios->data[offset + 2];
973 uint8_t data = bios->data[offset + 3];
980 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
981 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
982 offset, crtcindex, mask, data);
984 nv_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex, &value);
986 value = (value & mask) | data;
988 nv_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
993 static Bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
995 /* INIT_ZM_CR opcode: 0x53 ('S')
997 * offset (8 bit): opcode
998 * offset + 1 (8 bit): CRTC index
999 * offset + 2 (8 bit): value
1001 * Assign "value" to CRTC register with index "CRTC index".
1004 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1005 uint8_t data = bios->data[offset + 2];
1007 if (!iexec->execute)
1010 nv_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1015 static Bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1017 /* INIT_ZM_CR opcode: 0x54 ('T')
1019 * offset (8 bit): opcode
1020 * offset + 1 (8 bit): count
1021 * offset + 2 (8 bit): CRTC index 1
1022 * offset + 3 (8 bit): value 1
1025 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1028 uint8_t count = bios->data[offset + 1];
1031 if (!iexec->execute)
1034 for (i = 0; i < count; i++)
1035 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1040 static Bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1042 /* My BIOS does not use this command. */
1043 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1048 static Bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1050 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1052 * offset (8 bit): opcode
1053 * offset + 1 (32 bit): base register
1054 * offset + 5 (8 bit): count
1055 * offset + 6 (32 bit): value 1
1058 * Starting at offset + 6 there are "count" 32 bit values.
1059 * For "count" iterations set "base register" + 4 * current_iteration
1060 * to "value current_iteration"
1063 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1064 uint32_t count = bios->data[offset + 5];
1067 if (!iexec->execute)
1070 if (DEBUGLEVEL >= 6)
1071 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1072 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1073 offset, basereg, count);
1075 for (i = 0; i < count; i++) {
1076 uint32_t reg = basereg + i * 4;
1078 if ((reg & 0xffc) == 0x3c0)
1079 ErrorF("special case: FIXME\n");
1080 if ((reg & 0xffc) == 0x3cc)
1081 ErrorF("special case: FIXME\n");
1083 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1085 nv32_wr(pScrn, reg, data);
1091 static Bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1093 /* INIT_INDIRECT_REG opcode: 0x5A
1095 * offset (8 bit): opcode
1096 * offset + 1 (32 bit): register
1097 * offset + 5 (16 bit): adress offset (in bios)
1099 * Lookup value at offset data in the bios and write it to reg
1101 NVPtr pNv = NVPTR(pScrn);
1102 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1103 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1104 CARD32 data2 = bios->data[data];
1106 if (iexec->execute) {
1107 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1108 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1109 offset, reg, data, data2);
1111 if (DEBUGLEVEL >= 6) {
1113 nv32_rd(pScrn, reg, &tmpval);
1114 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1117 nv32_wr(pScrn, reg, data2);
1122 static Bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1124 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1126 * offset (8 bit): opcode
1127 * offset + 1 (16 bit): subroutine offset (in bios)
1129 * Calls a subroutine that will execute commands until INIT_DONE
1133 uint16_t sub_offset = le16_to_cpu(*((uint16_t *) (&bios->data[offset + 1])));
1135 if (!iexec->execute)
1138 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1139 offset, sub_offset);
1141 parse_init_table(pScrn, bios, sub_offset, iexec);
1143 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1144 offset, sub_offset);
1149 static Bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1151 CARD32 srcreg = *((CARD32 *) (&bios->data[offset + 1]));
1152 CARD8 shift = *((CARD8 *) (&bios->data[offset + 5]));
1153 CARD32 and1 = *((CARD32 *) (&bios->data[offset + 6]));
1154 CARD32 xor = *((CARD32 *) (&bios->data[offset + 10]));
1155 CARD32 dstreg = *((CARD32 *) (&bios->data[offset + 14]));
1156 CARD32 and2 = *((CARD32 *) (&bios->data[offset + 18]));
1160 if (iexec->execute) {
1161 nv32_rd(pScrn, srcreg, &srcdata);
1168 srcdata = (srcdata & and1) ^ xor;
1170 nv32_rd(pScrn, dstreg, &dstdata);
1176 nv32_rd(pScrn, dstreg, &tmp);
1178 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset, dstreg,
1181 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmp);
1183 nv32_wr(pScrn, dstreg, dstdata);
1188 static Bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1190 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1192 * offset (8 bit): opcode
1193 * offset + 1 (16 bit): CRTC port
1194 * offset + 3 (8 bit): CRTC index
1195 * offset + 4 (8 bit): data
1197 * Write "data" to index "CRTC index" of "CRTC port"
1199 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1200 uint8_t crtcindex = bios->data[offset + 3];
1201 uint8_t data = bios->data[offset + 4];
1203 if (!iexec->execute)
1206 nv_port_wr(pScrn, crtcport, crtcindex, data);
1211 static Bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1213 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1215 * offset (8 bit): opcode
1220 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1222 uint16_t ramcfg = le16_to_cpu(*((uint16_t *)(&bios->data[bios->ram_table_offset])));
1227 if (!iexec->execute)
1230 nv32_rd(pScrn, 0x00101000, &strapinfo);
1231 nv32_rd(pScrn, 0x00100080, &pfb_debug);
1233 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "STRAPINFO: 0x%08X\n", strapinfo);
1234 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PFB_DEBUG: 0x%08X\n", pfb_debug);
1235 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RAM CFG: 0x%04X\n", ramcfg);
1237 pfb_debug &= 0xffffffef;
1239 strapinfo &= 0x0000000f;
1240 ramcfg2 = le16_to_cpu(*((uint16_t *)
1241 (&bios->data[bios->ram_table_offset + (2 * strapinfo)])));
1243 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AFTER MANIPULATION\n");
1244 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "STRAPINFO: 0x%08X\n", strapinfo);
1245 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PFB_DEBUG: 0x%08X\n", pfb_debug);
1246 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RAM CFG2: 0x%08X\n", ramcfg2);
1252 nv32_rd(pScrn, 0x00100200, ®1);
1253 nv32_rd(pScrn, 0x0010020C, ®2);
1255 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x00100200: 0x%08X\n", reg1);
1256 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x0010020C: 0x%08X\n", reg2);
1262 static Bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1264 /* INIT_RESET opcode: 0x65 ('e')
1266 * offset (8 bit): opcode
1267 * offset + 1 (32 bit): register
1268 * offset + 5 (32 bit): value1
1269 * offset + 9 (32 bit): value2
1271 * Assign "value1" to "register", then assign "value2" to "register"
1274 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1275 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1276 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1279 if (!iexec->execute)
1282 if (DEBUGLEVEL >= 6)
1283 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1284 "0x%04X: Reg: 0x%08X, Value1: 0x%08X, Value2: 0x%08X\n",
1285 offset, reg, value1, value2);
1287 /* it's not clear from my .dmp file, but it seems we should zero out NV_PBUS_PCI_NV_19(0x0000184C) and then restore it */
1288 nv32_rd(pScrn, NV_PBUS_PCI_NV_19, &pci_nv_19);
1290 nv32_rd(pScrn, PCICFG(PCICFG_ROMSHADOW), &tmpval);
1291 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: PCICFG_ROMSHADOW: 0x%02X\n", offset, tmpval);
1293 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1294 nv32_wr(pScrn, reg, value1);
1295 nv32_wr(pScrn, reg, value2);
1296 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1298 /* PCI Config space init needs to be added here. */
1299 /* if (nv32_rd(pScrn, PCICFG(PCICFG_ROMSHADOW), value1)) */
1300 /* nv32_wr(pScrn, PCICFG(PCICFG_ROMSHADOW), value1 & 0xfffffffe) */
1305 static Bool init_index_io8(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1307 /* INIT_INDEX_IO8 opcode: 0x69
1309 * offset (8 bit): opcode
1310 * offset + 1 (16 bit): CRTC reg
1311 * offset + 3 (8 bit): and mask
1312 * offset + 4 (8 bit): or with
1317 NVPtr pNv = NVPTR(pScrn);
1318 volatile CARD8 *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
1319 CARD16 reg = le16_to_cpu(*((CARD16 *)(&bios->data[offset + 1])));
1320 CARD8 and = *((CARD8 *)(&bios->data[offset + 3]));
1321 CARD8 or = *((CARD8 *)(&bios->data[offset + 4]));
1324 if (iexec->execute) {
1325 data = (VGA_RD08(ptr, reg) & and) | or;
1327 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1328 "0x%04X: CRTC REG: 0x%04X, VALUE: 0x%02X\n",
1330 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%02X\n", offset,
1331 VGA_RD08(ptr, reg));
1333 #ifdef PERFORM_WRITE
1334 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init_index_io8 crtcreg 0x%X value 0x%X\n",reg,data);
1336 VGA_WR08(ptr, reg, data);
1342 static Bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1344 /* INIT_SUB opcode: 0x6B ('k')
1346 * offset (8 bit): opcode
1347 * offset + 1 (8 bit): script number
1349 * Execute script number "script number", as a subroutine
1352 uint8_t sub = bios->data[offset + 1];
1354 if (!iexec->execute)
1357 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1358 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
1360 parse_init_table(pScrn, bios,
1361 le16_to_cpu(*((CARD16 *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
1364 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1365 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
1370 static Bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1372 /* INIT_RAM_CONDITION opcode: 0x6D
1374 * offset (8 bit): opcode
1375 * offset + 1 (8 bit): and mask
1376 * offset + 2 (8 bit): cmpval
1378 * Test if (NV_PFB_BOOT & and mask) matches cmpval
1380 NVPtr pNv = NVPTR(pScrn);
1381 CARD8 and = *((CARD8 *) (&bios->data[offset + 1]));
1382 CARD8 cmpval = *((CARD8 *) (&bios->data[offset + 2]));
1385 if (iexec->execute) {
1386 data=(pNv->PFB[NV_PFB_BOOT/4])∧
1388 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1389 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1390 offset, data, cmpval);
1392 if (data == cmpval) {
1393 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1394 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1397 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
1398 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1399 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1400 iexec->execute = FALSE;
1406 static Bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1408 /* INIT_NV_REG opcode: 0x6E ('n')
1410 * offset (8 bit): opcode
1411 * offset + 1 (32 bit): register
1412 * offset + 5 (32 bit): mask
1413 * offset + 9 (32 bit): data
1415 * Assign ((REGVAL("register") & "mask") | "data") to "register"
1418 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1419 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1420 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1423 if (!iexec->execute)
1426 if (DEBUGLEVEL >= 6)
1427 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1428 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
1429 offset, reg, mask, data);
1431 nv32_rd(pScrn, reg, &value);
1433 value = (value & mask) | data;
1435 nv32_wr(pScrn, reg, value);
1440 static Bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1442 /* INIT_MACRO opcode: 0x6F ('o')
1444 * offset (8 bit): opcode
1445 * offset + 1 (8 bit): macro number
1447 * Look up macro index "macro number" in the macro index table.
1448 * The macro index table entry has 1 byte for the index in the macro table,
1449 * and 1 byte for the number of times to repeat the macro.
1450 * The macro table entry has 4 bytes for the register address and
1451 * 4 bytes for the value to write to that register
1454 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
1455 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
1456 uint8_t macro_tbl_idx = bios->data[tmp];
1457 uint8_t count = bios->data[tmp + 1];
1461 if (!iexec->execute)
1464 if (DEBUGLEVEL >= 6)
1465 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1466 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
1467 offset, macro_index_tbl_idx, macro_tbl_idx, count);
1469 for (i = 0; i < count; i++) {
1470 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
1472 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
1473 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
1475 nv32_wr(pScrn, reg, data);
1481 static Bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1483 /* INIT_DONE opcode: 0x71 ('q')
1485 * offset (8 bit): opcode
1487 * End the current script
1490 /* mild retval abuse to stop parsing this table */
1494 static Bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1496 /* INIT_RESUME opcode: 0x72 ('r')
1498 * offset (8 bit): opcode
1500 * End the current execute / no-execute condition
1506 iexec->execute = TRUE;;
1507 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1508 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
1513 static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1515 /* INIT_RAM_CONDITION2 opcode: 0x73
1517 * offset (8 bit): opcode
1518 * offset + 1 (8 bit): and mask
1519 * offset + 2 (8 bit): cmpval
1521 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
1523 NVPtr pNv = NVPTR(pScrn);
1524 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
1525 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
1528 if (iexec->execute) {
1529 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
1531 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1532 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1533 offset, data, cmpval);
1535 if (data == cmpval) {
1536 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1537 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1540 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
1541 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1542 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1543 iexec->execute = FALSE;
1549 static Bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1551 /* INIT_TIME opcode: 0x74 ('t')
1553 * offset (8 bit): opcode
1554 * offset + 1 (16 bit): time
1556 * Sleep for "time" microseconds.
1559 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1561 if (!iexec->execute)
1564 if (DEBUGLEVEL >= 6)
1565 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1566 "0x%04X: Sleeping for 0x%04X microseconds.\n", offset, time);
1573 static Bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1575 /* INIT_CONDITION opcode: 0x75 ('u')
1577 * offset (8 bit): opcode
1578 * offset + 1 (8 bit): condition number
1580 * Check condition "condition number" in the condition table.
1581 * The condition table entry has 4 bytes for the address of the
1582 * register to check, 4 bytes for a mask and 4 for a test value.
1583 * If condition not met skip subsequent opcodes until condition
1584 * is inverted (INIT_NOT), or we hit INIT_RESUME
1587 uint8_t cond = bios->data[offset + 1];
1588 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1589 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1590 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1591 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1594 if (!iexec->execute)
1597 if (DEBUGLEVEL >= 6)
1598 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1599 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
1600 offset, cond, reg, mask, cmpval);
1602 nv32_rd(pScrn, reg, &data);
1605 if (DEBUGLEVEL >= 6)
1606 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1607 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1608 offset, data, cmpval);
1610 if (data == cmpval) {
1611 if (DEBUGLEVEL >= 6)
1612 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1613 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1615 if (DEBUGLEVEL >= 6)
1616 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1617 "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
1618 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1619 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1620 iexec->execute = FALSE;
1626 static Bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1628 /* INIT_INDEX_IO opcode: 0x78 ('x')
1630 * offset (8 bit): opcode
1631 * offset + 1 (16 bit): CRTC port
1632 * offset + 3 (8 bit): CRTC index
1633 * offset + 4 (8 bit): mask
1634 * offset + 5 (8 bit): data
1636 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
1639 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1640 uint8_t crtcindex = bios->data[offset + 3];
1641 uint8_t mask = bios->data[offset + 4];
1642 uint8_t data = bios->data[offset + 5];
1645 if (!iexec->execute)
1648 if (DEBUGLEVEL >= 6)
1649 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1650 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1651 offset, crtcport, crtcindex, mask, data);
1653 nv_port_rd(pScrn, crtcport, crtcindex, &value);
1654 value = (value & mask) | data;
1655 nv_port_wr(pScrn, crtcport, crtcindex, value);
1660 static Bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1662 /* INIT_PLL opcode: 0x79 ('y')
1664 * offset (8 bit): opcode
1665 * offset + 1 (32 bit): register
1666 * offset + 5 (16 bit): freq
1668 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
1671 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1672 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
1674 if (!iexec->execute)
1677 if (DEBUGLEVEL >= 6)
1678 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1679 "0x%04X: Reg: 0x%04X, Freq: %d0kHz\n",
1682 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1687 configval = 0x00011F05;
1694 static Bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1696 /* INIT_ZM_REG opcode: 0x7A ('z')
1698 * offset (8 bit): opcode
1699 * offset + 1 (32 bit): register
1700 * offset + 5 (32 bit): value
1702 * Assign "value" to "register"
1705 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1706 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1708 if (!iexec->execute)
1711 nv32_wr(pScrn, reg, value);
1716 static init_tbl_entry_t itbl_entry[] = {
1717 /* command name , id , length , offset , mult , command handler */
1718 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
1719 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
1720 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
1721 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
1722 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
1723 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
1724 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
1725 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
1726 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
1727 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
1728 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
1729 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
1730 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
1731 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
1732 { "INIT_50" , 0x50, 3 , 2 , 2 , init_50 },
1733 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
1734 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
1735 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
1736 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
1737 // { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
1738 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
1739 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
1740 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
1741 // { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
1742 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
1743 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
1744 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
1745 /* { "INIT_NEXT" , 0x66, x , x , x , init_next }, */
1746 /* { "INIT_NEXT" , 0x67, x , x , x , init_next }, */
1747 /* { "INIT_NEXT" , 0x68, x , x , x , init_next }, */
1748 // { "INIT_INDEX_IO8" , 0x69, 5 , 0 , 0 , init_index_io8 },
1749 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
1750 // { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
1751 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
1752 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
1753 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
1754 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
1755 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
1756 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
1757 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
1758 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
1759 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
1760 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
1761 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
1762 /* { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, x , x , x , init_ram_restrict_zm_reg_group }, */
1763 /* { "INIT_COPY_ZM_REG" , 0x90, x , x , x , init_copy_zm_reg }, */
1764 /* { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, x , x , x , init_zm_reg_group_addr_latched }, */
1765 /* { "INIT_RESERVED" , 0x92, x , x , x , init_reserved }, */
1766 { 0 , 0 , 0 , 0 , 0 , 0 }
1769 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
1771 /* Calculates the length of a given init table entry. */
1772 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
1775 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
1777 /* Parses all commands in a init table. */
1779 /* We start out executing all commands found in the
1780 * init table. Some op codes may change the status
1781 * of this variable to SKIP, which will cause
1782 * the following op codes to perform no operation until
1783 * the value is changed back to EXECUTE.
1789 /* Loop until INIT_DONE causes us to break out of the loop
1790 * (or until offset > bios length just in case... )
1791 * (and no more than 10000 iterations just in case... ) */
1792 while ((offset < bios->length) && (count++ < 10000)) {
1793 id = bios->data[offset];
1795 /* Find matching id in itbl_entry */
1796 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
1799 if (itbl_entry[i].name) {
1800 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
1801 offset, itbl_entry[i].id, itbl_entry[i].name);
1803 /* execute eventual command handler */
1804 if (itbl_entry[i].handler)
1805 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
1808 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1809 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
1813 /* Add the offset of the current command including all data
1814 * of that command. The offset will then be pointing on the
1817 offset += get_init_table_entry_length(bios, offset, i);
1821 void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
1823 /* Loops and calls parse_init_table() for each present table. */
1827 init_exec_t iexec = {TRUE, FALSE};
1829 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
1831 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing init table %d\n",
1834 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1835 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
1837 parse_init_table(pScrn, bios, table, &iexec);
1843 uint16_t fptablepointer;
1844 uint16_t fpxlatetableptr;
1845 uint16_t lvdsmanufacturerpointer;
1846 uint16_t fpxlatemanufacturertableptr;
1849 static void parse_fp_tables(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
1851 NVPtr pNv = NVPTR(pScrn);
1852 unsigned int fpstrapping;
1853 uint8_t *fptable, *fpxlatetable;
1854 /* uint8_t *lvdsmanufacturertable, *fpxlatemanufacturertable;*/
1855 unsigned int fpindex;/* lvdsmanufacturerindex;*/
1856 uint8_t fptable_ver, headerlen = 0, recordlen = 44;
1858 DisplayModePtr mode;
1860 fpstrapping = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) >> 16) & 0xf;
1862 if (fpp->fptablepointer == 0x0) {
1863 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1864 "Pointer to flat panel table invalid\n");
1868 fptable = &bios->data[fpp->fptablepointer];
1870 fptable_ver = fptable[0];
1872 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1873 "Found flat panel mode table revision %d.%d\n",
1874 fptable_ver >> 4, fptable_ver & 0xf);
1876 switch (fptable_ver) {
1877 /* PINS version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
1878 * and miss one of the spread spectrum/PWM bytes.
1879 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
1880 * Here we assume that a version of 0x05 matches this case (combining with a
1881 * PINS version check would be better), as the common case for the panel type
1882 * field is 0x0005, and that is in fact what we are reading the first byte of. */
1883 case 0x05: /* some NV10, 11, 15, 16 */
1884 /* note that in this version the lvdsmanufacturertable is not defined */
1888 case 0x10: /* some NV15/16, and NV11+ */
1891 if (fpp->fpxlatetableptr == 0x0) {
1892 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1893 "Pointer to flat panel translation table invalid\n");
1896 fpxlatetable = &bios->data[fpp->fpxlatetableptr];
1898 lvdsmanufacturertable = &bios->data[fpp->lvdsmanufacturerpointer];
1899 fpxlatemanufacturertable = &bios->data[fpp->fpxlatemanufacturertableptr];*/
1901 fpindex = fpxlatetable[fpstrapping];
1903 lvdsmanufacturerindex = fpxlatemanufacturertable[fpstrapping]; */
1905 if (fpindex > 0xf) {
1906 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1907 "Bad flat panel table index\n");
1911 case 0x20: /* NV40+ */
1912 headerlen = fptable[1];
1913 recordlen = fptable[2]; // check this, or hardcode as 0x20
1914 /* may be the wrong test, if there's a translation table
1915 if (fpstrapping > fptable[3]) {
1916 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1917 "Flat panel strapping number too high\n");
1921 /* I don't know where the index for the table comes from in v2.0, so bail
1924 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1925 "FP Table revision not currently supported\n");
1929 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
1932 int modeofs = headerlen + recordlen * fpindex + ofs;
1933 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
1934 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 2]);
1935 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
1936 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
1937 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
1938 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 16]);
1939 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
1940 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
1941 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
1942 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
1943 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
1946 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
1947 * bytes 3-6 are bits per colour in RGBX
1949 * 13-14 is HValid Start
1950 * 15-16 is HValid End
1951 * bytes 38-39 relate to spread spectrum settings
1952 * bytes 40-43 are something to do with PWM */
1954 mode->prev = mode->next = NULL;
1955 mode->status = MODE_OK;
1956 mode->type = M_T_DRIVER | M_T_PREFERRED;
1957 xf86SetModeDefaultName(mode);
1959 // if (pNv->debug_modes) { this should exist
1960 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1961 "Found flat panel mode in BIOS tables:\n");
1962 xf86PrintModeline(pScrn->scrnIndex, mode);
1965 bios->fp_native_mode = mode;
1968 static void parse_t_table(ScrnInfoPtr pScrn, bios_t *bios, uint16_t ttableptr)
1970 uint8_t headerlen = 0;
1972 init_exec_t iexec = {TRUE, FALSE};
1974 if (ttableptr == 0x0) {
1975 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1976 "Pointer to T table invalid\n");
1980 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found T table revision %d.%d\n",
1981 bios->data[ttableptr] >> 4, bios->data[ttableptr] & 0xf);
1983 headerlen = bios->data[ttableptr + 1];
1984 table = ttableptr + headerlen;
1986 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing T table\n", table);
1987 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1988 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
1989 // bios->execute = TRUE;
1990 parse_init_table(pScrn, bios, table, &iexec);
1991 bios->execute = FALSE;
1994 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
1997 /* Parses the flat panel table segment that the bit entry points to.
1998 * Starting at bitentry->offset:
2000 * offset + 0 (16 bits): FIXME table pointer
2001 * offset + 2 (16 bits): mode table pointer
2004 struct fppointers fpp;
2006 /* If it's not a laptop, you probably don't care about fptables */
2007 /* FIXME: detect mobile BIOS? */
2009 NVPtr pNv = NVPTR(pScrn);
2014 if (bitentry->length != 4) {
2015 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2016 "Do not understand BIT display table entry.\n");
2020 table = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
2021 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
2023 parse_fp_tables(pScrn, bios, &fpp);
2028 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2030 /* Parses the init table segment that the bit entry points to.
2031 * Starting at bitentry->offset:
2033 * offset + 0 (16 bits): init script tables pointer
2034 * offset + 2 (16 bits): macro index table pointer
2035 * offset + 4 (16 bits): macro table pointer
2036 * offset + 6 (16 bits): condition table pointer
2037 * offset + 8 (16 bits): io condition table pointer
2038 * offset + 10 (16 bits): io flag condition table pointer
2039 * offset + 12 (16 bits): init function table pointer
2042 * * Are 'I' bit entries always of length 0xE?
2046 if (bitentry->length < 12) {
2047 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2048 "Unable to recognize BIT init table entry.\n");
2052 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
2053 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
2054 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
2055 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
2056 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
2057 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
2058 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
2060 parse_init_tables(pScrn, bios);
2065 static int parse_bit_t_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2067 /* Parses the pointer to the T table
2069 * Starting at bitentry->offset:
2071 * offset + 0 (16 bits): T table pointer
2074 if (bitentry->length != 2) {
2075 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2076 "Do not understand BIT T table entry.\n");
2080 bios->t_table_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
2082 /* just for testing */
2083 parse_t_table(pScrn, bios, bios->t_table_ptr);
2088 static unsigned int parse_bmp_table_pointers(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2090 /* Parse the pointers for useful tables in the BMP structure, starting at
2091 * offset 75 from the ..NV. signature.
2093 * First 7 pointers as for parse_bit_init_tbl_entry
2095 * offset + 30: flat panel timings table pointer
2096 * offset + 32: flat panel strapping translation table pointer
2097 * offset + 42: LVDS manufacturer panel config table pointer
2098 * offset + 44: LVDS manufacturer strapping translation table pointer
2101 NVPtr pNv = NVPTR(pScrn);
2102 struct fppointers fpp;
2104 if (!parse_bit_init_tbl_entry(pScrn, bios, bitentry))
2107 /* If it's not a laptop, you probably don't care about fptables */
2108 /* FIXME: detect mobile BIOS? */
2112 if (bitentry->length > 33) {
2113 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 30])));
2114 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 32])));
2116 if (bitentry->length > 45) {
2117 fpp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 42])));
2118 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 44])));
2121 parse_fp_tables(pScrn, bios, &fpp);
2126 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
2128 bit_entry_t bitentry;
2132 bitentry.id[0] = bios->data[offset];
2133 bitentry.id[1] = bios->data[offset + 1];
2134 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
2135 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
2137 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2138 "0x%04X: Found BIT command with id 0x%02X\n",
2139 offset, bitentry.id[0]);
2141 switch (bitentry.id[0]) {
2143 /* id[0] = 0 and id[1] = 0 ==> end of BIT struture */
2144 if (bitentry.id[1] == 0)
2148 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2149 "0x%04X: Found flat panel display table entry in BIT structure.\n", offset);
2150 parse_bit_display_tbl_entry(pScrn, bios, &bitentry);
2153 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2154 "0x%04X: Found init table entry in BIT structure.\n", offset);
2155 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
2158 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2159 "0x%04X: Found T table entry in BIT structure.\n", offset);
2160 parse_bit_t_tbl_entry(pScrn, bios, &bitentry);
2163 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2164 "0x%04X: Found unknown entry in BIT structure with id %c.\n", offset, bitentry.id[0]);
2166 /* TODO: What kind of information does the other BIT entrys point to?
2167 * 'P' entry is probably performance tables, but there are
2168 * quite a few others...
2172 offset += sizeof(bit_entry_t);
2176 static void parse_pins_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
2178 int pins_version_major=bios->data[offset+5];
2179 int pins_version_minor=bios->data[offset+6];
2180 int init1 = bios->data[offset + 18] + (bios->data[offset + 19] * 256);
2181 int init2 = bios->data[offset + 20] + (bios->data[offset + 21] * 256);
2182 int init_size = bios->data[offset + 22] + (bios->data[offset + 23] * 256) + 1;
2185 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PINS version %d.%d\n",
2186 pins_version_major, pins_version_minor);
2189 if (nv_cksum(bios->data + offset, 8)) {
2190 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "bad PINS checksum\n");
2194 switch (pins_version_major) {
2196 ram_tab = init1-0x0010;
2201 ram_tab = bios->data[offset + 24] + (bios->data[offset + 25] * 256);
2207 if ((pins_version_major==5)&&(pins_version_minor>=6)) {
2208 /* VCO range info */
2211 if ((pins_version_major==5)&&(pins_version_minor>=16)) {
2212 bit_entry_t bitentry;
2214 if (pins_version_minor == 0x10)
2215 bitentry.length = 12; /* I've not seen this version, so be "long enough" */
2216 else if (pins_version_minor < 0x14)
2217 bitentry.length = 34;
2219 bitentry.length = 48; /* versions after 0x14 are longer,
2220 but extra contents unneeded ATM */
2222 bitentry.offset = offset + 75;
2223 parse_bmp_table_pointers(pScrn, bios, &bitentry);
2225 /* TODO type1 script */
2229 static unsigned int findstr(bios_t* bios, unsigned char *str, int len)
2233 for (i = 2; i <= (bios->length - len); i++)
2234 if (strncmp((char *)&bios->data[i], (char *)str, len) == 0)
2240 static Bool parse_dcb_entry(uint8_t dcb_version, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
2242 if (dcb_version >= 0x20) {
2243 entry->type = conn & 0xf;
2244 entry->i2c_index = (conn >> 4) & 0xf;
2245 entry->heads = (conn >> 8) & 0xf;
2246 entry->bus = (conn >> 16) & 0xf;
2247 entry->location = (conn >> 20) & 0xf;
2248 entry->or = (conn >> 24) & 0xf;
2249 if ((1 << ffs(entry->or)) * 3 == entry->or)
2250 entry->duallink = TRUE;
2252 entry->duallink = FALSE;
2253 } else if (dcb_version >= 0x14 ) {
2254 if (conn != 0xf0003f00) {
2255 ErrorF("Unknown DCB 1.4 entry, please report\n");
2258 /* safe defaults for a crt */
2260 entry->i2c_index = 0;
2263 entry->location = 0;
2265 entry->duallink = FALSE;
2267 // 1.2 needs more loving
2270 entry->i2c_index = 0;
2273 entry->location = 0;
2275 entry->duallink = FALSE;
2282 read_dcb_i2c_table(ScrnInfoPtr pScrn, bios_t *bios, uint8_t dcb_version, uint16_t i2ctabptr)
2284 NVPtr pNv = NVPTR(pScrn);
2286 uint8_t headerlen = 0;
2288 int recordoffset = 0, rdofs = 1, wrofs = 0;
2291 i2c_entries = MAX_NUM_DCB_ENTRIES;
2292 memset(pNv->dcb_table.i2c_read, 0, sizeof(pNv->dcb_table.i2c_read));
2293 memset(pNv->dcb_table.i2c_write, 0, sizeof(pNv->dcb_table.i2c_write));
2295 i2ctable = &bios->data[i2ctabptr];
2297 if (dcb_version >= 0x30) {
2298 if (i2ctable[0] != dcb_version) { /* necessary? */
2299 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2300 "DCB I2C table version mismatch (%02X vs %02X)\n",
2301 i2ctable[0], dcb_version);
2304 headerlen = i2ctable[1];
2305 i2c_entries = i2ctable[2];
2306 if (i2ctable[0] >= 0x40) {
2307 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2308 "G80 DCB I2C table detected, arrgh\n"); /* they're plain weird */
2312 /* it's your own fault if you call this function on a DCB 1.1 BIOS */
2313 if (dcb_version < 0x14) {
2319 for (i = 0; i < i2c_entries; i++) {
2320 if (i2ctable[headerlen + 4 * i + 3] != 0xff) {
2321 pNv->dcb_table.i2c_read[i] = i2ctable[headerlen + recordoffset + rdofs + 4 * i];
2322 pNv->dcb_table.i2c_write[i] = i2ctable[headerlen + recordoffset + wrofs + 4 * i];
2327 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
2329 NVPtr pNv = NVPTR(pScrn);
2330 uint16_t dcbptr, i2ctabptr = 0;
2332 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
2333 Bool configblock = TRUE;
2334 int recordlength = 8, confofs = 4;
2337 pNv->dcb_table.entries = 0;
2339 /* get the offset from 0x36 */
2340 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
2342 if (dcbptr == 0x0) {
2343 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2344 "No Display Configuration Block pointer found\n");
2348 dcbtable = &bios->data[dcbptr];
2350 /* get DCB version */
2351 dcb_version = dcbtable[0];
2352 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2353 "Display Configuration Block version %d.%d found\n",
2354 dcb_version >> 4, dcb_version & 0xf);
2356 if (dcb_version >= 0x20) { /* NV17+ */
2359 if (dcb_version >= 0x30) { /* NV40+ */
2360 headerlen = dcbtable[1];
2361 entries = dcbtable[2];
2362 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
2363 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
2365 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2366 "DCB header length %02X, with %02X possible entries\n",
2367 headerlen, entries);
2369 /* dcb_block_count = *(dcbtable[1]); */
2370 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
2371 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
2375 if (sig != 0x4edcbdcb) {
2376 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2377 "Bad Display Configuration Block signature (%08X)\n", sig);
2380 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
2384 strncpy(sig, (char *)&dcbtable[-7], 7);
2385 /* dcb_block_count = *(dcbtable[1]); */
2386 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
2390 if (strcmp(sig, "DEV_REC")) {
2391 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2392 "Bad Display Configuration Block signature (%s)\n", sig);
2395 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
2396 /* dcb_block_count = *(dcbtable[1]); */
2397 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
2398 configblock = FALSE;
2399 } else { /* NV5+, maybe NV4 */
2400 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2401 "Structure of Display Configuration Blocks prior to version 1.2 unknown\n");
2405 if (entries >= MAX_NUM_DCB_ENTRIES)
2406 entries = MAX_NUM_DCB_ENTRIES;
2408 for (i = 0; i < entries; i++) {
2409 uint32_t connection, config = 0;
2411 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
2413 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
2415 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables
2416 * can be discontinuous */
2417 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
2420 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
2421 if (!parse_dcb_entry(dcb_version, connection, config, &pNv->dcb_table.entry[i]))
2424 pNv->dcb_table.entries = i;
2426 read_dcb_i2c_table(pScrn, bios, dcb_version, i2ctabptr);
2428 return pNv->dcb_table.entries;
2431 unsigned int NVParseBios(ScrnInfoPtr pScrn)
2433 unsigned int bit_offset;
2434 uint8_t nv_signature[]={0xff,0x7f,'N','V',0x0};
2435 uint8_t bit_signature[]={'B','I','T'};
2439 pNv->dcb_table.entries = 0;
2441 memset(&pNv->VBIOS, 0, sizeof(bios_t));
2442 pNv->VBIOS.execute = FALSE;
2443 pNv->VBIOS.data = xalloc(64 * 1024);
2444 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
2445 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2446 "No valid BIOS image found.\n");
2447 xfree(pNv->VBIOS.data);
2450 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
2451 if (pNv->VBIOS.length > NV_PROM_SIZE)
2452 pNv->VBIOS.length = NV_PROM_SIZE;
2454 /* parse Display Configuration Block (DCB) table */
2455 if (parse_dcb_table(pScrn, &pNv->VBIOS))
2456 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2457 "Found %d entries in DCB.\n", pNv->dcb_table.entries);
2459 /* check for known signatures */
2460 if ((bit_offset = findstr(&pNv->VBIOS, bit_signature, sizeof(bit_signature)))) {
2461 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT signature found.\n");
2462 parse_bit_structure(pScrn, &pNv->VBIOS, bit_offset + 4);
2463 } else if ((bit_offset = findstr(&pNv->VBIOS, nv_signature, sizeof(nv_signature)))) {
2464 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV signature found.\n");
2465 parse_pins_structure(pScrn, &pNv->VBIOS, bit_offset);
2467 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2468 "No known script signature found.\n");