git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 1993-2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "nv_include.h"
  27
  28 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  29 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  30 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  31 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  32 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  33 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  34 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  35 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  36
  37 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  38 {
  39         ScrnInfoPtr pScrn = crtc->scrn;
  40         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  41         NVPtr pNv = NVPTR(pScrn);
  42
  43         return NVReadCRTC(pNv, nv_crtc->head, reg);
  44 }
  45
  46 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  47 {
  48         ScrnInfoPtr pScrn = crtc->scrn;
  49         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  50         NVPtr pNv = NVPTR(pScrn);
  51
  52         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  53 }
  54
  55 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  56 {
  57         ScrnInfoPtr pScrn = crtc->scrn;
  58         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  59         NVPtr pNv = NVPTR(pScrn);
  60
  61         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  62 }
  63
  64 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  65 {
  66         ScrnInfoPtr pScrn = crtc->scrn;
  67         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  68         NVPtr pNv = NVPTR(pScrn);
  69
  70         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  71 }
  72
  73 void NVCrtcLockUnlock(xf86CrtcPtr crtc, bool lock)
  74 {
  75         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  76         NVPtr pNv = NVPTR(crtc->scrn);
  77
  78         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
  79 }
  80
  81 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
  82 /* They are only valid for NV4x, appearantly reordered for NV5x */
  83 /* gpu pll: 0x4000 + 0x4004
  84  * unknown pll: 0x4008 + 0x400c
  85  * vpll1: 0x4010 + 0x4014
  86  * vpll2: 0x4018 + 0x401c
  87  * unknown pll: 0x4020 + 0x4024
  88  * unknown pll: 0x4038 + 0x403c
  89  * Some of the unknown's are probably memory pll's.
  90  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
  91  * 1 and 2 refer to the registers of each pair. There is only one post divider.
  92  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
  93  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
  94  *     bit8: A switch that turns of the second divider and multiplier off.
  95  *     bit12: Also a switch, i haven't seen it yet.
  96  *     bit16-19: p-divider
  97  *     but 28-31: Something related to the mode that is used (see bit8).
  98  * 2) bit0-7: m-divider (a)
  99  *     bit8-15: n-multiplier (a)
 100  *     bit16-23: m-divider (b)
 101  *     bit24-31: n-multiplier (b)
 102  */
 103
 104 /* Modifying the gpu pll for example requires:
 105  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 106  * This is not needed for the vpll's which have their own bits.
 107  */
 108
 109 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 110 {
 111         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 112         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 113         NVPtr pNv = NVPTR(crtc->scrn);
 114
 115         if (nv_crtc->head) {
 116                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 117                 if (pNv->twoStagePLL)
 118                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 119         } else {
 120                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 121                 if (pNv->twoStagePLL)
 122                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 123         }
 124         if (pNv->twoHeads)
 125                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 126         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 127         if (pNv->Architecture == NV_ARCH_40)
 128                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 129 }
 130
 131 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 132 {
 133         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 134         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 135         ScrnInfoPtr pScrn = crtc->scrn;
 136         NVPtr pNv = NVPTR(pScrn);
 137         uint32_t savedc040 = 0;
 138
 139         /* This sequence is important, the NV28 is very sensitive in this area. */
 140         /* Keep pllsel last and sel_clk first. */
 141         if (pNv->twoHeads)
 142                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 143
 144         if (pNv->Architecture == NV_ARCH_40) {
 145                 savedc040 = nvReadMC(pNv, 0xc040);
 146
 147                 /* for vpll1 change bits 16 and 17 are disabled */
 148                 /* for vpll2 change bits 18 and 19 are disabled */
 149                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 150         }
 151
 152         if (nv_crtc->head) {
 153                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 154                 if (pNv->twoStagePLL)
 155                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 156         } else {
 157                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 158                 if (pNv->twoStagePLL)
 159                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 160         }
 161
 162         if (pNv->Architecture == NV_ARCH_40) {
 163                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 164
 165                 /* We need to wait a while */
 166                 usleep(5000);
 167                 nvWriteMC(pNv, 0xc040, savedc040);
 168         }
 169
 170         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 171         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 172 }
 173
 174 static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
 175 {
 176         NVPtr pNv = NVPTR(crtc->scrn);
 177         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 178         uint32_t cursor_start;
 179         uint8_t *CRTC = pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC;
 180
 181         if (pNv->Architecture == NV_ARCH_04)
 182                 cursor_start = 0x5E00 << 2;
 183         else
 184                 cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
 185
 186         CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
 187         if (pNv->Architecture != NV_ARCH_04)
 188                 CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
 189         CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
 190         if (crtc->mode.Flags & V_DBLSCAN)
 191                 CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
 192         CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
 193
 194         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
 195         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
 196         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
 197         if (pNv->Architecture == NV_ARCH_40)
 198                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
 199 }
 200
 201 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
 202 {
 203         ScrnInfoPtr pScrn = crtc->scrn;
 204         NVPtr pNv = NVPTR(pScrn);
 205         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 206         RIVA_HW_STATE *state = &pNv->ModeReg;
 207         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 208         struct pll_lims pll_lim;
 209         int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
 210         uint32_t g70_pll_special_bits = 0;
 211         bool nv4x_single_stage_pll_mode = false;
 212         uint8_t arbitration0;
 213         uint16_t arbitration1;
 214
 215         if (!get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
 216                 return;
 217
 218         if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
 219                 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 220                         nv4x_single_stage_pll_mode = true;
 221                         /* Turn the second set of divider and multiplier off */
 222                         /* Bogus data, the same nvidia uses */
 223                         NM2 = 0x11f;
 224                         VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 225                 } else
 226                         VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
 227         } else
 228                 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 229
 230         /* Are these all the (relevant) G70 cards? */
 231         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 232                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 233                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 234                 if (nv4x_single_stage_pll_mode)
 235                         g70_pll_special_bits = 0x1;
 236                 else
 237                         g70_pll_special_bits = 0x3;
 238         }
 239
 240         if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
 241                 /* See nvregisters.xml for details. */
 242                 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
 243         else
 244                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 245         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 246
 247         if (nv4x_single_stage_pll_mode) {
 248                 if (nv_crtc->head == 0)
 249                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 250                 else
 251                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 252         } else {
 253                 if (nv_crtc->head == 0)
 254                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 255                 else
 256                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 257         }
 258
 259         /* The NV40 seems to have more similarities to NV3x than other NV4x */
 260         if (pNv->NVArch < 0x41)
 261                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
 262                                  NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 263         /* The blob uses this always, so let's do the same */
 264         if (pNv->Architecture == NV_ARCH_40)
 265                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 266
 267         if (nv_crtc->head == 1) {
 268                 if (!nv4x_single_stage_pll_mode)
 269                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 270                 else
 271                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 272                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 273         } else {
 274                 if (!nv4x_single_stage_pll_mode)
 275                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 276                 else
 277                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 278                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 279         }
 280
 281         if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
 282                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 283         else
 284                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 285
 286         if (pNv->Architecture < NV_ARCH_30)
 287                 nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);
 288         else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
 289                  (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
 290                 arbitration0 = 128;
 291                 arbitration1 = 0x0480;
 292         } else
 293                 nv30UpdateArbitrationSettings(&arbitration0, &arbitration1);
 294
 295         regp->CRTC[NV_CIO_CRE_FF_INDEX] = arbitration0;
 296         regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arbitration1 & 0xff;
 297         if (pNv->Architecture >= NV_ARCH_30)
 298                 regp->CRTC[NV_CIO_CRE_47] = arbitration1 >> 8;
 299
 300         nv_crtc_cursor_set(crtc);
 301 }
 302
 303 static void
 304 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 305 {
 306         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 307         ScrnInfoPtr pScrn = crtc->scrn;
 308         NVPtr pNv = NVPTR(pScrn);
 309         unsigned char seq1 = 0, crtc17 = 0;
 310         unsigned char crtc1A;
 311
 312         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting dpms mode %d on CRTC %d\n", mode, nv_crtc->head);
 313
 314         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 315                 return;
 316
 317         nv_crtc->last_dpms = mode;
 318
 319         if (pNv->twoHeads)
 320                 NVSetOwner(pNv, nv_crtc->head);
 321
 322         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
 323         switch(mode) {
 324                 case DPMSModeStandby:
 325                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 326                 seq1 = 0x20;
 327                 crtc17 = 0x80;
 328                 crtc1A |= 0x80;
 329                 break;
 330         case DPMSModeSuspend:
 331                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 332                 seq1 = 0x20;
 333                 crtc17 = 0x80;
 334                 crtc1A |= 0x40;
 335                 break;
 336         case DPMSModeOff:
 337                 /* Screen: Off; HSync: Off, VSync: Off */
 338                 seq1 = 0x20;
 339                 crtc17 = 0x00;
 340                 crtc1A |= 0xC0;
 341                 break;
 342         case DPMSModeOn:
 343         default:
 344                 /* Screen: On; HSync: On, VSync: On */
 345                 seq1 = 0x00;
 346                 crtc17 = 0x80;
 347                 break;
 348         }
 349
 350         NVVgaSeqReset(pNv, nv_crtc->head, true);
 351         /* Each head has it's own sequencer, so we can turn it off when we want */
 352         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
 353         NVWriteVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX, seq1);
 354         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80);
 355         usleep(10000);
 356         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17);
 357         NVVgaSeqReset(pNv, nv_crtc->head, false);
 358
 359         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
 360 }
 361
 362 static Bool
 363 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 364                      DisplayModePtr adjusted_mode)
 365 {
 366         return TRUE;
 367 }
 368
 369 static void
 370 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 371 {
 372         ScrnInfoPtr pScrn = crtc->scrn;
 373         NVPtr pNv = NVPTR(pScrn);
 374         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 375         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 376
 377         /* Calculate our timings */
 378         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 379         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 380         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 381         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 382         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 383         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 384         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 385         int vertStart           = mode->CrtcVSyncStart          - 1;
 386         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 387         int vertTotal           = mode->CrtcVTotal                      - 2;
 388         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 389         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 390
 391         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 392         bool fp_output = false;
 393         int i;
 394
 395         for (i = 0; i < xf86_config->num_output; i++) {
 396                 xf86OutputPtr output = xf86_config->output[i];
 397                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 398
 399                 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
 400                                              nv_encoder->dcb->type == OUTPUT_TMDS))
 401                         fp_output = true;
 402         }
 403
 404         if (fp_output) {
 405                 vertStart = vertTotal - 3;
 406                 vertEnd = vertTotal - 2;
 407                 vertBlankStart = vertStart;
 408                 horizStart = horizTotal - 5;
 409                 horizEnd = horizTotal - 2;
 410                 horizBlankEnd = horizTotal + 4;
 411                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 412                         /* This reportedly works around some video overlay bandwidth problems */
 413                         horizTotal += 2;
 414         }
 415
 416         if (mode->Flags & V_INTERLACE)
 417                 vertTotal |= 1;
 418
 419 #if 0
 420         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 421         ErrorF("horizStart: 0x%X \n", horizStart);
 422         ErrorF("horizEnd: 0x%X \n", horizEnd);
 423         ErrorF("horizTotal: 0x%X \n", horizTotal);
 424         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 425         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 426         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 427         ErrorF("vertStart: 0x%X \n", vertStart);
 428         ErrorF("vertEnd: 0x%X \n", vertEnd);
 429         ErrorF("vertTotal: 0x%X \n", vertTotal);
 430         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 431         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 432 #endif
 433
 434         /*
 435         * compute correct Hsync & Vsync polarity
 436         */
 437         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 438                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 439
 440                 regp->MiscOutReg = 0x23;
 441                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 442                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 443         } else {
 444                 int VDisplay = mode->VDisplay;
 445                 if (mode->Flags & V_DBLSCAN)
 446                         VDisplay *= 2;
 447                 if (mode->VScan > 1)
 448                         VDisplay *= mode->VScan;
 449                 if (VDisplay < 400)
 450                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 451                 else if (VDisplay < 480)
 452                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 453                 else if (VDisplay < 768)
 454                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 455                 else
 456                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 457         }
 458
 459         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 460
 461         /*
 462         * Time Sequencer
 463         */
 464         regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
 465         /* 0x20 disables the sequencer */
 466         if (mode->Flags & V_CLKDIV2)
 467                 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
 468         else
 469                 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
 470         regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
 471         regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
 472         regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
 473
 474         /*
 475         * CRTC Controller
 476         */
 477         regp->CRTC[NV_CIO_CR_HDT_INDEX]  = Set8Bits(horizTotal);
 478         regp->CRTC[NV_CIO_CR_HDE_INDEX]  = Set8Bits(horizDisplay);
 479         regp->CRTC[NV_CIO_CR_HBS_INDEX]  = Set8Bits(horizBlankStart);
 480         regp->CRTC[NV_CIO_CR_HBE_INDEX]  = SetBitField(horizBlankEnd,4:0,4:0)
 481                                 | SetBit(7);
 482         regp->CRTC[NV_CIO_CR_HRS_INDEX]  = Set8Bits(horizStart);
 483         regp->CRTC[NV_CIO_CR_HRE_INDEX]  = SetBitField(horizBlankEnd,5:5,7:7)
 484                                 | SetBitField(horizEnd,4:0,4:0);
 485         regp->CRTC[NV_CIO_CR_VDT_INDEX]  = SetBitField(vertTotal,7:0,7:0);
 486         regp->CRTC[NV_CIO_CR_OVL_INDEX]  = SetBitField(vertTotal,8:8,0:0)
 487                                 | SetBitField(vertDisplay,8:8,1:1)
 488                                 | SetBitField(vertStart,8:8,2:2)
 489                                 | SetBitField(vertBlankStart,8:8,3:3)
 490                                 | SetBit(4)
 491                                 | SetBitField(vertTotal,9:9,5:5)
 492                                 | SetBitField(vertDisplay,9:9,6:6)
 493                                 | SetBitField(vertStart,9:9,7:7);
 494         regp->CRTC[NV_CIO_CR_RSAL_INDEX]  = 0x00;
 495         regp->CRTC[NV_CIO_CR_CELL_HT_INDEX]  = SetBitField(vertBlankStart,9:9,5:5)
 496                                 | SetBit(6)
 497                                 | (mode->Flags & V_DBLSCAN) * NV_CIO_CR_CELL_HT_SCANDBL;
 498         regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
 499         regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
 500         regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
 501         regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
 502         regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
 503         regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
 504         regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart);
 505         /* What is the meaning of bit5, it is empty in the vga spec. */
 506         regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
 507         regp->CRTC[NV_CIO_CR_VDE_INDEX] = Set8Bits(vertDisplay);
 508         /* framebuffer can be larger than crtc scanout area. */
 509         regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
 510         regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
 511         regp->CRTC[NV_CIO_CR_VBS_INDEX] = Set8Bits(vertBlankStart);
 512         regp->CRTC[NV_CIO_CR_VBE_INDEX] = Set8Bits(vertBlankEnd);
 513         regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
 514         regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
 515
 516         /*
 517          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 518          */
 519
 520         /* framebuffer can be larger than crtc scanout area. */
 521         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
 522         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 523         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = SetBitField(horizBlankEnd,6:6,4:4)
 524                                 | SetBitField(vertBlankStart,10:10,3:3)
 525                                 | SetBitField(vertStart,10:10,2:2)
 526                                 | SetBitField(vertDisplay,10:10,1:1)
 527                                 | SetBitField(vertTotal,10:10,0:0);
 528
 529         regp->CRTC[NV_CIO_CRE_HEB__INDEX] = SetBitField(horizTotal,8:8,0:0)
 530                                 | SetBitField(horizDisplay,8:8,1:1)
 531                                 | SetBitField(horizBlankStart,8:8,2:2)
 532                                 | SetBitField(horizStart,8:8,3:3);
 533
 534         regp->CRTC[NV_CIO_CRE_EBR_INDEX] = SetBitField(vertTotal,11:11,0:0)
 535                                 | SetBitField(vertDisplay,11:11,2:2)
 536                                 | SetBitField(vertStart,11:11,4:4)
 537                                 | SetBitField(vertBlankStart,11:11,6:6);
 538
 539         if(mode->Flags & V_INTERLACE) {
 540                 horizTotal = (horizTotal >> 1) & ~1;
 541                 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = Set8Bits(horizTotal);
 542                 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= SetBitField(horizTotal,8:8,4:4);
 543         } else
 544                 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;  /* interlace off */
 545
 546         /*
 547         * Graphics Display Controller
 548         */
 549         regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
 550         regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
 551         regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
 552         regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
 553         regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
 554         regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
 555         regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
 556         regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
 557         regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
 558
 559         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 560         regp->Attribute[1]  = 0x01;
 561         regp->Attribute[2]  = 0x02;
 562         regp->Attribute[3]  = 0x03;
 563         regp->Attribute[4]  = 0x04;
 564         regp->Attribute[5]  = 0x05;
 565         regp->Attribute[6]  = 0x06;
 566         regp->Attribute[7]  = 0x07;
 567         regp->Attribute[8]  = 0x08;
 568         regp->Attribute[9]  = 0x09;
 569         regp->Attribute[10] = 0x0A;
 570         regp->Attribute[11] = 0x0B;
 571         regp->Attribute[12] = 0x0C;
 572         regp->Attribute[13] = 0x0D;
 573         regp->Attribute[14] = 0x0E;
 574         regp->Attribute[15] = 0x0F;
 575         regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
 576         /* Non-vga */
 577         regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
 578         regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
 579         regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
 580         regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
 581 }
 582
 583 /**
 584  * Sets up registers for the given mode/adjusted_mode pair.
 585  *
 586  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 587  *
 588  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 589  * be easily turned on/off after this.
 590  */
 591 static void
 592 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 593 {
 594         ScrnInfoPtr pScrn = crtc->scrn;
 595         NVPtr pNv = NVPTR(pScrn);
 596         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 597         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 598         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 599         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 600         bool lvds_output = false, tmds_output = false;
 601         int i;
 602
 603         for (i = 0; i < xf86_config->num_output; i++) {
 604                 xf86OutputPtr output = xf86_config->output[i];
 605                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 606
 607                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 608                         lvds_output = true;
 609                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
 610                         tmds_output = true;
 611         }
 612
 613         /* Registers not directly related to the (s)vga mode */
 614
 615         /* bit2 = 0 -> fine pitched crtc granularity */
 616         /* The rest disables double buffering on CRTC access */
 617         regp->CRTC[NV_CIO_CRE_21] = 0xfa;
 618
 619         /* the blob sometimes sets |= 0x10 (which is the same as setting |=
 620          * 1 << 30 on 0x60.830), for no apparent reason */
 621         regp->CRTC[NV_CIO_CRE_59] = 0x0;
 622         if (tmds_output && pNv->Architecture < NV_ARCH_40)
 623                 regp->CRTC[NV_CIO_CRE_59] |= 0x1;
 624
 625         /* What is the meaning of this register? */
 626         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 627         regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
 628
 629         regp->head = 0;
 630         /* Except for rare conditions I2C is enabled on the primary crtc */
 631         if (nv_crtc->head == 0)
 632                 regp->head |= NV_CRTC_FSEL_I2C;
 633         /* Set overlay to desired crtc. */
 634         if (pNv->overlayAdaptor) {
 635                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 636                 if (pPriv->overlayCRTC == nv_crtc->head)
 637                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 638         }
 639
 640         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 641         /* This fixes my cursor corruption issue */
 642         regp->cursorConfig = 0x0;
 643         if(mode->Flags & V_DBLSCAN)
 644                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 645         if (pNv->alphaCursor) {
 646                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
 647                                       NV_CRTC_CURSOR_CONFIG_64PIXELS |
 648                                       NV_CRTC_CURSOR_CONFIG_64LINES |
 649                                       NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
 650         } else
 651                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 652
 653         /* Unblock some timings */
 654         regp->CRTC[NV_CIO_CRE_53] = 0;
 655         regp->CRTC[NV_CIO_CRE_54] = 0;
 656
 657         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 658         if (lvds_output)
 659                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
 660         else if (tmds_output)
 661                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
 662         else
 663                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
 664
 665         /* These values seem to vary */
 666         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 667         regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
 668
 669         regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
 670
 671         /* What does this do?:
 672          * bit0: crtc0
 673          * bit6: lvds
 674          * bit7: (only in X)
 675          */
 676         if (nv_crtc->head == 0)
 677                 regp->CRTC[NV_CIO_CRE_4B] = 0x81;
 678         else
 679                 regp->CRTC[NV_CIO_CRE_4B] = 0x80;
 680
 681         if (lvds_output)
 682                 regp->CRTC[NV_CIO_CRE_4B] |= 0x40;
 683
 684         /* The blob seems to take the current value from crtc 0, add 4 to that
 685          * and reuse the old value for crtc 1 */
 686         regp->CRTC[NV_CIO_CRE_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_CIO_CRE_52];
 687         if (!nv_crtc->head)
 688                 regp->CRTC[NV_CIO_CRE_52] += 4;
 689
 690         regp->unk830 = mode->CrtcVDisplay - 3;
 691         regp->unk834 = mode->CrtcVDisplay - 1;
 692
 693         if (pNv->twoHeads)
 694                 /* This is what the blob does */
 695                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 696
 697         /* Never ever modify gpio, unless you know very well what you're doing */
 698         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 699
 700         if (pNv->twoHeads)
 701                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 702
 703         regp->config = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
 704
 705         /* Some misc regs */
 706         if (pNv->Architecture == NV_ARCH_40) {
 707                 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
 708                 regp->CRTC[NV_CIO_CRE_86] = 0x1;
 709         }
 710
 711         regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (pScrn->depth + 1) / 8;
 712         /* Enable slaved mode */
 713         if (lvds_output || tmds_output)
 714                 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
 715
 716         /* Generic PRAMDAC regs */
 717
 718         if (pNv->Architecture >= NV_ARCH_10)
 719                 /* Only bit that bios and blob set. */
 720                 regp->nv10_cursync = (1 << 25);
 721
 722         switch (pScrn->depth) {
 723                 case 24:
 724                 case 15:
 725                         regp->general = 0x00100130;
 726                         break;
 727                 case 16:
 728                 default:
 729                         regp->general = 0x00101130;
 730                         break;
 731         }
 732         if (pNv->alphaCursor)
 733                 /* PIPE_LONG mode, something to do with the size of the cursor? */
 734                 regp->general |= 1 << 29;
 735
 736         regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
 737
 738         /* Some values the blob sets */
 739         regp->unk_a20 = 0x0;
 740         regp->unk_a24 = 0xfffff;
 741         regp->unk_a34 = 0x1;
 742 }
 743
 744 /* this could be set in nv_output, but would require some rework of load/save */
 745 static void
 746 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 747 {
 748         ScrnInfoPtr pScrn = crtc->scrn;
 749         NVPtr pNv = NVPTR(pScrn);
 750         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 751         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 752         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 753         struct nouveau_encoder *nv_encoder = NULL;
 754         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 755         bool is_fp = false;
 756         bool is_lvds = false;
 757         uint32_t mode_ratio, panel_ratio;
 758         int i;
 759
 760         for (i = 0; i < xf86_config->num_output; i++) {
 761                 xf86OutputPtr output = xf86_config->output[i];
 762                 /* assuming one fp output per crtc seems ok */
 763                 nv_encoder = to_nouveau_encoder(output);
 764
 765                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 766                         is_lvds = true;
 767                 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
 768                         is_fp = true;
 769                         break;
 770                 }
 771         }
 772         if (!is_fp)
 773                 return;
 774
 775         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
 776         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
 777         if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
 778                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
 779         else
 780                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
 781         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
 782         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
 783         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
 784         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
 785
 786         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
 787         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
 788         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
 789         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
 790         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
 791         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
 792         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
 793
 794         /*
 795         * bit0: positive vsync
 796         * bit4: positive hsync
 797         * bit8: enable center mode
 798         * bit9: enable native mode
 799         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
 800         * bit26: a bit sometimes seen on some g70 cards
 801         * bit28: fp display enable bit
 802         * bit31: set for dual link LVDS
 803         */
 804
 805         regp->fp_control = (savep->fp_control & 0x04100000) |
 806                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
 807
 808         /* Deal with vsync/hsync polarity */
 809         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 810         if (adjusted_mode->Flags & V_PVSYNC)
 811                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
 812         if (adjusted_mode->Flags & V_PHSYNC)
 813                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
 814
 815         if (nv_encoder->scaling_mode == SCALE_PANEL ||
 816             nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
 817                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
 818         /* This is also true for panel scaling, so we must put the panel scale check first */
 819         else if (mode->HDisplay == adjusted_mode->HDisplay &&
 820                  mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
 821                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
 822         else /* gpu needs to scale */
 823                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
 824
 825         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 826                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
 827
 828         if (is_lvds && pNv->VBIOS.fp.dual_link)
 829                 regp->fp_control |= (8 << 28);
 830
 831         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
 832         regp->debug_0 = 0x01101191;
 833         /* We want automatic scaling */
 834         regp->debug_1 = 0;
 835         /* This can override HTOTAL and VTOTAL */
 836         regp->debug_2 = 0;
 837
 838         /* Use 20.12 fixed point format to avoid floats */
 839         mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
 840         panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
 841         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 842          * get treated the same as SCALE_FULLSCREEN */
 843         if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
 844                 uint32_t diff, scale;
 845
 846                 if (mode_ratio < panel_ratio) {
 847                         /* vertical needs to expand to glass size (automatic)
 848                          * horizontal needs to be scaled at vertical scale factor
 849                          * to maintain aspect */
 850
 851                         scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
 852                         regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
 853
 854                         /* restrict area of screen used, horizontally */
 855                         diff = adjusted_mode->HDisplay -
 856                                adjusted_mode->VDisplay * mode_ratio / (1 << 12);
 857                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
 858                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
 859                 }
 860
 861                 if (mode_ratio > panel_ratio) {
 862                         /* horizontal needs to expand to glass size (automatic)
 863                          * vertical needs to be scaled at horizontal scale factor
 864                          * to maintain aspect */
 865
 866                         scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
 867                         regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
 868
 869                         /* restrict area of screen used, vertically */
 870                         diff = adjusted_mode->VDisplay -
 871                                (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
 872                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
 873                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
 874                 }
 875         }
 876
 877         /* Flatpanel support needs at least a NV10 */
 878         if (pNv->twoHeads) {
 879                 /* Output property. */
 880                 if (nv_encoder && nv_encoder->dithering) {
 881                         if (pNv->NVArch == 0x11)
 882                                 regp->dither = savep->dither | 0x00010000;
 883                         else {
 884                                 int i;
 885                                 regp->dither = savep->dither | 0x00000001;
 886                                 for (i = 0; i < 3; i++) {
 887                                         regp->dither_regs[i] = 0xe4e4e4e4;
 888                                         regp->dither_regs[i + 3] = 0x44444444;
 889                                 }
 890                         }
 891                 } else {
 892                         if (pNv->NVArch != 0x11) {
 893                                 /* reset them */
 894                                 int i;
 895                                 for (i = 0; i < 3; i++) {
 896                                         regp->dither_regs[i] = savep->dither_regs[i];
 897                                         regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 898                                 }
 899                         }
 900                         regp->dither = savep->dither;
 901                 }
 902         } else
 903                 regp->dither = savep->dither;
 904 }
 905
 906 /**
 907  * Sets up registers for the given mode/adjusted_mode pair.
 908  *
 909  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 910  *
 911  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 912  * be easily turned on/off after this.
 913  */
 914 static void
 915 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 916                  DisplayModePtr adjusted_mode,
 917                  int x, int y)
 918 {
 919         ScrnInfoPtr pScrn = crtc->scrn;
 920         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 921         NVPtr pNv = NVPTR(pScrn);
 922
 923         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CTRC mode on CRTC %d:\n", nv_crtc->head);
 924         xf86PrintModeline(pScrn->scrnIndex, mode);
 925         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output mode on CRTC %d:\n", nv_crtc->head);
 926         xf86PrintModeline(pScrn->scrnIndex, adjusted_mode);
 927
 928         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
 929
 930         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
 931         if (pNv->Architecture == NV_ARCH_40)
 932                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 933         nv_crtc_mode_set_regs(crtc, mode);
 934         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
 935         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 936
 937         NVVgaProtect(pNv, nv_crtc->head, true);
 938         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
 939         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
 940         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
 941         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
 942         nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
 943
 944         NVVgaProtect(pNv, nv_crtc->head, false);
 945
 946         NVCrtcSetBase(crtc, x, y);
 947
 948 #if X_BYTE_ORDER == X_BIG_ENDIAN
 949         /* turn on LFB swapping */
 950         {
 951                 uint8_t tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
 952                 tmp |= NV_CIO_CRE_RCR_ENDIAN_BIG;
 953                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp);
 954         }
 955 #endif
 956 }
 957
 958 static void nv_crtc_save(xf86CrtcPtr crtc)
 959 {
 960         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 961         NVPtr pNv = NVPTR(crtc->scrn);
 962
 963         if (pNv->twoHeads)
 964                 NVSetOwner(pNv, nv_crtc->head);
 965
 966         /* We just came back from terminal, so unlock */
 967         NVCrtcLockUnlock(crtc, false);
 968
 969         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
 970         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
 971         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
 972         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
 973         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
 974
 975         /* init some state to saved value */
 976         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
 977         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
 978         pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX];
 979 }
 980
 981 static void nv_crtc_restore(xf86CrtcPtr crtc)
 982 {
 983         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 984         NVPtr pNv = NVPTR(crtc->scrn);
 985
 986         /* Just to be safe */
 987         NVCrtcLockUnlock(crtc, false);
 988
 989         if (pNv->twoHeads)
 990                 NVSetOwner(pNv, nv_crtc->head);
 991
 992         NVVgaProtect(pNv, nv_crtc->head, true);
 993         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
 994         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
 995         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
 996         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
 997         nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
 998         NVVgaProtect(pNv, nv_crtc->head, false);
 999
1000         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1001 }
1002
1003 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1004 {
1005         ScrnInfoPtr pScrn = crtc->scrn;
1006         NVPtr pNv = NVPTR(pScrn);
1007         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1008
1009         if (pNv->twoHeads)
1010                 NVSetOwner(pNv, nv_crtc->head);
1011
1012         /* Just in case */
1013         NVCrtcLockUnlock(crtc, 0);
1014
1015         crtc->funcs->dpms(crtc, DPMSModeOff);
1016
1017         /* Sync the engine before adjust mode */
1018         if (pNv->EXADriverPtr) {
1019                 exaMarkSync(pScrn->pScreen);
1020                 exaWaitSync(pScrn->pScreen);
1021         }
1022
1023         NVBlankScreen(pNv, nv_crtc->head, true);
1024
1025         /* Some more preperation. */
1026         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
1027         if (pNv->Architecture == NV_ARCH_40) {
1028                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1029                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1030         }
1031 }
1032
1033 static void nv_crtc_commit(xf86CrtcPtr crtc)
1034 {
1035         crtc->funcs->dpms (crtc, DPMSModeOn);
1036
1037         if (crtc->scrn->pScreen != NULL) {
1038                 NVPtr pNv = NVPTR(crtc->scrn);
1039
1040                 xf86_reload_cursors (crtc->scrn->pScreen);
1041                 if (!pNv->alphaCursor) {
1042                         /* this works round the fact that xf86_reload_cursors
1043                          * will quite happily show the hw cursor when it knows
1044                          * the hardware can't do alpha, and the current cursor
1045                          * has an alpha channel
1046                          */
1047                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1048                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1049                 }
1050         }
1051 }
1052
1053 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1054 {
1055         xfree(to_nouveau_crtc(crtc));
1056 }
1057
1058 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1059 {
1060         return FALSE;
1061 }
1062
1063 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1064 {
1065 }
1066
1067 static void
1068 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1069                                         int size)
1070 {
1071         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1072         ScrnInfoPtr pScrn = crtc->scrn;
1073         NVPtr pNv = NVPTR(pScrn);
1074         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1075         int i, j;
1076
1077         switch (pScrn->depth) {
1078         case 15:
1079                 /* R5G5B5 */
1080                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1081                 for (i = 0; i < 32; i++)
1082                         for (j = 0; j < 8; j++) {
1083                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1084                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1085                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1086                         }
1087                 break;
1088         case 16:
1089                 /* R5G6B5 */
1090                 /* First deal with the 5 bit colors */
1091                 for (i = 0; i < 32; i++)
1092                         for (j = 0; j < 8; j++) {
1093                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1094                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1095                         }
1096                 /* Now deal with the 6 bit color */
1097                 for (i = 0; i < 64; i++)
1098                         for (j = 0; j < 4; j++)
1099                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1100                 break;
1101         default:
1102                 /* R8G8B8 */
1103                 for (i = 0; i < 256; i++) {
1104                         regp->DAC[i * 3] = red[i] >> 8;
1105                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1106                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1107                 }
1108                 break;
1109         }
1110
1111         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1112 }
1113
1114 /**
1115  * Allocates memory for a locked-in-framebuffer shadow of the given
1116  * width and height for this CRTC's rotated shadow framebuffer.
1117  */
1118
1119 static void *
1120 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1121 {
1122         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1123         ScrnInfoPtr pScrn = crtc->scrn;
1124         NVPtr pNv = NVPTR(pScrn);
1125         void *offset;
1126
1127         unsigned long rotate_pitch;
1128         int size, align = 64;
1129
1130         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1131         size = rotate_pitch * height;
1132
1133         assert(nv_crtc->shadow == NULL);
1134         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1135                         align, size, &nv_crtc->shadow)) {
1136                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1137                 return NULL;
1138         }
1139
1140         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1141                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1142                                 "Failed to map shadow buffer.\n");
1143                 return NULL;
1144         }
1145
1146         offset = nv_crtc->shadow->map;
1147         return offset;
1148 }
1149
1150 /**
1151  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1152  */
1153 static PixmapPtr
1154 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1155 {
1156         ScrnInfoPtr pScrn = crtc->scrn;
1157         ScreenPtr pScreen = pScrn->pScreen;
1158         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1159         unsigned long rotate_pitch;
1160         PixmapPtr rotate_pixmap;
1161         struct nouveau_pixmap *nvpix;
1162
1163         if (!data)
1164                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1165
1166         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1167
1168         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1169         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1170                                                                 0, /* width */
1171                                                                 0, /* height */
1172         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1173                                                                 pScrn->depth,
1174                                                                 0);
1175         #else
1176                                                                 pScrn->depth);
1177         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1178
1179         if (rotate_pixmap == NULL) {
1180                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1181                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1182         }
1183
1184         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1185         if (!nvpix) {
1186                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1187         } else {
1188                 nvpix->bo = nv_crtc->shadow;
1189         }
1190
1191         /* Modify the pixmap to actually be the one we need. */
1192         pScreen->ModifyPixmapHeader(rotate_pixmap,
1193                                         width,
1194                                         height,
1195                                         pScrn->depth,
1196                                         pScrn->bitsPerPixel,
1197                                         rotate_pitch,
1198                                         data);
1199
1200         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1201         if (!nvpix || !nvpix->bo)
1202                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1203
1204         return rotate_pixmap;
1205 }
1206
1207 static void
1208 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1209 {
1210         ScrnInfoPtr pScrn = crtc->scrn;
1211         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1212         ScreenPtr pScreen = pScrn->pScreen;
1213
1214         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1215                 pScreen->DestroyPixmap(rotate_pixmap);
1216         }
1217
1218         nv_crtc->shadow = NULL;
1219 }
1220
1221 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1222         .dpms = nv_crtc_dpms,
1223         .save = nv_crtc_save,
1224         .restore = nv_crtc_restore,
1225         .mode_fixup = nv_crtc_mode_fixup,
1226         .mode_set = nv_crtc_mode_set,
1227         .prepare = nv_crtc_prepare,
1228         .commit = nv_crtc_commit,
1229         .destroy = nv_crtc_destroy,
1230         .lock = nv_crtc_lock,
1231         .unlock = nv_crtc_unlock,
1232         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1233         .set_cursor_position = nv_crtc_set_cursor_position,
1234         .show_cursor = nv_crtc_show_cursor,
1235         .hide_cursor = nv_crtc_hide_cursor,
1236         .load_cursor_argb = nv_crtc_load_cursor_argb,
1237         .gamma_set = nv_crtc_gamma_set,
1238         .shadow_create = nv_crtc_shadow_create,
1239         .shadow_allocate = nv_crtc_shadow_allocate,
1240         .shadow_destroy = nv_crtc_shadow_destroy,
1241 };
1242
1243 void
1244 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1245 {
1246         NVPtr pNv = NVPTR(pScrn);
1247         static xf86CrtcFuncsRec crtcfuncs;
1248         xf86CrtcPtr crtc;
1249         struct nouveau_crtc *nv_crtc;
1250         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1251         int i;
1252
1253         crtcfuncs = nv_crtc_funcs;
1254
1255         /* NV04-NV10 doesn't support alpha cursors */
1256         if (pNv->NVArch < 0x11) {
1257                 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1258                 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1259                 crtcfuncs.load_cursor_argb = NULL;
1260         }
1261         if (pNv->NoAccel) {
1262                 crtcfuncs.shadow_create = NULL;
1263                 crtcfuncs.shadow_allocate = NULL;
1264                 crtcfuncs.shadow_destroy = NULL;
1265         }
1266
1267         if (!(crtc = xf86CrtcCreate(pScrn, &crtcfuncs)))
1268                 return;
1269
1270         if (!(nv_crtc = xcalloc(1, sizeof (struct nouveau_crtc)))) {
1271                 xf86CrtcDestroy(crtc);
1272                 return;
1273         }
1274
1275         nv_crtc->head = crtc_num;
1276         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1277
1278         crtc->driver_private = nv_crtc;
1279
1280         /* Initialise the default LUT table. */
1281         for (i = 0; i < 256; i++) {
1282                 regp->DAC[i*3] = i;
1283                 regp->DAC[(i*3)+1] = i;
1284                 regp->DAC[(i*3)+2] = i;
1285         }
1286
1287         NVCrtcLockUnlock(crtc, false);
1288 }
1289
1290 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1291 {
1292         ScrnInfoPtr pScrn = crtc->scrn;
1293         NVPtr pNv = NVPTR(pScrn);
1294         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1295         int i;
1296         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1297
1298         NVWritePRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
1299
1300         for (i = 0; i < 5; i++)
1301                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1302
1303         for (i = 0; i < 25; i++)
1304                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1305
1306         for (i = 0; i < 9; i++)
1307                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1308
1309         NVSetEnablePalette(pNv, nv_crtc->head, true);
1310         for (i = 0; i < 21; i++)
1311                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1312
1313         NVSetEnablePalette(pNv, nv_crtc->head, false);
1314 }
1315
1316 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1317 {
1318         ScrnInfoPtr pScrn = crtc->scrn;
1319         NVPtr pNv = NVPTR(pScrn);
1320         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1321         NVCrtcRegPtr regp;
1322         int i;
1323
1324         regp = &state->crtc_reg[nv_crtc->head];
1325
1326         if (pNv->Architecture >= NV_ARCH_10) {
1327                 if (pNv->twoHeads)
1328                         /* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some
1329                          * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1330                         NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1331
1332                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1333                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1334                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1335                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1336                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1337                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1338                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1339                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1340                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1341
1342                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21, regp->CRTC[NV_CIO_CRE_21]);
1343                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1344                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1345                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1346                 if (pNv->Architecture == NV_ARCH_40) {
1347                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1348                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1349                 }
1350
1351                 if (pNv->Architecture == NV_ARCH_40) {
1352                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1353                         if (regp->config == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
1354                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1355                         else
1356                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1357                 }
1358         }
1359
1360         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1361         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1362
1363         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX, regp->CRTC[NV_CIO_CRE_RPC0_INDEX]);
1364         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, regp->CRTC[NV_CIO_CRE_RPC1_INDEX]);
1365         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX, regp->CRTC[NV_CIO_CRE_LSR_INDEX]);
1366         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX, regp->CRTC[NV_CIO_CRE_PIXEL_INDEX]);
1367         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX, regp->CRTC[NV_CIO_CRE_LCD__INDEX]);
1368         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX, regp->CRTC[NV_CIO_CRE_HEB__INDEX]);
1369         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX, regp->CRTC[NV_CIO_CRE_ENH_INDEX]);
1370         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX, regp->CRTC[NV_CIO_CRE_FF_INDEX]);
1371         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX, regp->CRTC[NV_CIO_CRE_FFLWM__INDEX]);
1372         if (pNv->Architecture >= NV_ARCH_30)
1373                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47, regp->CRTC[NV_CIO_CRE_47]);
1374
1375         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
1376         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
1377         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
1378         if (pNv->Architecture == NV_ARCH_40)
1379                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
1380         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX, regp->CRTC[NV_CIO_CRE_ILACE__INDEX]);
1381
1382         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]);
1383         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]);
1384         if (pNv->Architecture >= NV_ARCH_10) {
1385                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX, regp->CRTC[NV_CIO_CRE_EBR_INDEX]);
1386                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB, regp->CRTC[NV_CIO_CRE_CSB]);
1387                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B, regp->CRTC[NV_CIO_CRE_4B]);
1388                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52, regp->CRTC[NV_CIO_CRE_52]);
1389         }
1390         /* NV11 and NV20 stop at 0x52. */
1391         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1392                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53, regp->CRTC[NV_CIO_CRE_53]);
1393                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54, regp->CRTC[NV_CIO_CRE_54]);
1394
1395                 for (i = 0; i < 0x10; i++)
1396                         NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1397                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59, regp->CRTC[NV_CIO_CRE_59]);
1398
1399                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85, regp->CRTC[NV_CIO_CRE_85]);
1400                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86, regp->CRTC[NV_CIO_CRE_86]);
1401         }
1402
1403         NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1404
1405         /* Setting 1 on this value gives you interrupts for every vblank period. */
1406         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1407         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1408 }
1409
1410 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1411 {
1412         ScrnInfoPtr pScrn = crtc->scrn;
1413         NVPtr pNv = NVPTR(pScrn);
1414         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1415         int i;
1416         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1417
1418         regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__READ);
1419
1420         for (i = 0; i < 25; i++)
1421                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1422
1423         NVSetEnablePalette(pNv, nv_crtc->head, true);
1424         for (i = 0; i < 21; i++)
1425                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1426         NVSetEnablePalette(pNv, nv_crtc->head, false);
1427
1428         for (i = 0; i < 9; i++)
1429                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1430
1431         for (i = 0; i < 5; i++)
1432                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1433 }
1434
1435 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1436 {
1437         ScrnInfoPtr pScrn = crtc->scrn;
1438         NVPtr pNv = NVPTR(pScrn);
1439         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1440         NVCrtcRegPtr regp;
1441         int i;
1442
1443         regp = &state->crtc_reg[nv_crtc->head];
1444
1445         regp->CRTC[NV_CIO_CRE_LCD__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX);
1446         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX);
1447         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX);
1448         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX);
1449         regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX);
1450         regp->CRTC[NV_CIO_CRE_HEB__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX);
1451         regp->CRTC[NV_CIO_CRE_ENH_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX);
1452
1453         regp->CRTC[NV_CIO_CRE_FF_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX);
1454         regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX);
1455         regp->CRTC[NV_CIO_CRE_21] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21);
1456         if (pNv->Architecture >= NV_ARCH_30)
1457                 regp->CRTC[NV_CIO_CRE_47] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47);
1458         regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1459         regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1460         regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1461         regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX);
1462
1463         if (pNv->Architecture >= NV_ARCH_10) {
1464                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1465                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1466                 if (pNv->Architecture == NV_ARCH_40) {
1467                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1468                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1469                 }
1470                 if (pNv->twoHeads)
1471                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1472                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1473         }
1474
1475         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1476         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1477
1478         regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX);
1479         regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX);
1480         if (pNv->Architecture >= NV_ARCH_10) {
1481                 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX);
1482                 regp->CRTC[NV_CIO_CRE_CSB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB);
1483                 regp->CRTC[NV_CIO_CRE_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B);
1484                 regp->CRTC[NV_CIO_CRE_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52);
1485         }
1486         /* NV11 and NV20 don't have this, they stop at 0x52. */
1487         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1488                 for (i = 0; i < 0x10; i++)
1489                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1490
1491                 regp->CRTC[NV_CIO_CRE_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59);
1492                 regp->CRTC[NV_CIO_CRE_53] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53);
1493                 regp->CRTC[NV_CIO_CRE_54] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54);
1494
1495                 regp->CRTC[NV_CIO_CRE_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85);
1496                 regp->CRTC[NV_CIO_CRE_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86);
1497         }
1498
1499         regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1500 }
1501
1502 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1503 {
1504         ScrnInfoPtr pScrn = crtc->scrn;
1505         NVPtr pNv = NVPTR(pScrn);
1506         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1507         NVCrtcRegPtr regp;
1508         int i;
1509
1510         regp = &state->crtc_reg[nv_crtc->head];
1511
1512         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1513
1514         if (pNv->twoHeads) {
1515                 if (pNv->NVArch >= 0x17)
1516                         regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1517                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1518                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1519                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1520                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1521
1522                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1523                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1524                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1525         }
1526
1527         if (pNv->NVArch == 0x11) {
1528                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1529         } else if (pNv->twoHeads) {
1530                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1531                 for (i = 0; i < 3; i++) {
1532                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1533                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1534                 }
1535         }
1536         if (pNv->Architecture >= NV_ARCH_10)
1537                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1538
1539         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1540
1541         for (i = 0; i < 7; i++) {
1542                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1543                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1544         }
1545
1546         for (i = 0; i < 7; i++) {
1547                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1548                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1549         }
1550 }
1551
1552 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1553 {
1554         ScrnInfoPtr pScrn = crtc->scrn;
1555         NVPtr pNv = NVPTR(pScrn);
1556         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1557         NVCrtcRegPtr regp;
1558         int i;
1559
1560         regp = &state->crtc_reg[nv_crtc->head];
1561
1562         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1563
1564         if (pNv->twoHeads) {
1565                 if (pNv->NVArch >= 0x17)
1566                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1567                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1568                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1569                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1570                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1571                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1572                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1573                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1574                 }
1575
1576                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1577                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1578                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1579         }
1580
1581         if (pNv->NVArch == 0x11)
1582                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1583         else if (pNv->twoHeads) {
1584                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1585                 for (i = 0; i < 3; i++) {
1586                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1587                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1588                 }
1589         }
1590         if (pNv->Architecture >= NV_ARCH_10)
1591                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1592
1593         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1594
1595         for (i = 0; i < 7; i++) {
1596                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1597                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1598         }
1599
1600         for (i = 0; i < 7; i++) {
1601                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1602                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1603         }
1604 }
1605
1606 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1607 {
1608         ScrnInfoPtr pScrn = crtc->scrn;
1609         NVPtr pNv = NVPTR(pScrn);
1610         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1611         uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1612
1613         if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1614                 start = nv_crtc->shadow->offset;
1615         else
1616                 start += pNv->FB->offset;
1617
1618         /* 30 bits addresses in 32 bits according to haiku */
1619         start &= ~3;
1620         pNv->ModeReg.crtc_reg[nv_crtc->head].fb_start = start;
1621         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start);
1622
1623         crtc->x = x;
1624         crtc->y = y;
1625 }
1626
1627 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1628 {
1629         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1630         NVPtr pNv = NVPTR(crtc->scrn);
1631         int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1632
1633         VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1634         VGA_WR08(pNv->REGS, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1635
1636         for (i = 0; i < 768; i++) {
1637                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset);
1638                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1639         }
1640
1641         NVSetEnablePalette(pNv, nv_crtc->head, false);
1642 }
1643 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1644 {
1645         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1646         NVPtr pNv = NVPTR(crtc->scrn);
1647         int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1648
1649         VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1650         VGA_WR08(pNv->REGS, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1651
1652         for (i = 0; i < 768; i++) {
1653                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1654                 NV_WR08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1655         }
1656
1657         NVSetEnablePalette(pNv, nv_crtc->head, false);
1658 }