git.oblomov.eu Git - clinfo/blob - src/ext.h

   1 /* Include OpenCL header, and define OpenCL extensions, since what is and is not
   2  * available in the official headers is very system-dependent */
   3
   4 #ifdef __APPLE__
   5 #include <OpenCL/opencl.h>
   6 #else
   7 #include <CL/cl.h>
   8 #endif
   9
  10 /* These two defines were introduced in the 1.2 headers
  11  * on 2012-11-30, so earlier versions don't have them
  12  * (e.g. Debian wheezy)
  13  */
  14
  15 #ifndef CL_DEVICE_IMAGE_PITCH_ALIGNMENT
  16 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT                 0x104A
  17 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT          0x104B
  18 #endif
  19
  20 /* 2.0 headers are not very common for the time being, so
  21  * let's copy the defines for the new CL_DEVICE_* properties
  22  * here.
  23  */
  24 #ifndef CL_VERSION_2_0
  25 #define CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS             0x104C
  26 #define CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE              0x104D
  27 #define CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES            0x104E
  28 #define CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE        0x104F
  29 #define CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE              0x1050
  30 #define CL_DEVICE_MAX_ON_DEVICE_QUEUES                  0x1051
  31 #define CL_DEVICE_MAX_ON_DEVICE_EVENTS                  0x1052
  32 #define CL_DEVICE_SVM_CAPABILITIES                      0x1053
  33 #define CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE  0x1054
  34 #define CL_DEVICE_MAX_PIPE_ARGS                         0x1055
  35 #define CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS          0x1056
  36 #define CL_DEVICE_PIPE_MAX_PACKET_SIZE                  0x1057
  37 #define CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT   0x1058
  38 #define CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT     0x1059
  39 #define CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT      0x105A
  40
  41 #define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER           (1 << 0)
  42 #define CL_DEVICE_SVM_FINE_GRAIN_BUFFER             (1 << 1)
  43 #define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM             (1 << 2)
  44 #define CL_DEVICE_SVM_ATOMICS                       (1 << 3)
  45
  46 typedef cl_bitfield         cl_device_svm_capabilities;
  47 #endif
  48
  49 #ifndef CL_VERSION_2_1
  50 #define CL_PLATFORM_HOST_TIMER_RESOLUTION               0x0905
  51 #define CL_DEVICE_IL_VERSION                            0x105B
  52 #define CL_DEVICE_MAX_NUM_SUB_GROUPS                    0x105C
  53 #define CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS 0x105D
  54 #endif
  55
  56 /*
  57  * Extensions
  58  */
  59
  60 /* cl_khr_icd */
  61 #define CL_PLATFORM_ICD_SUFFIX_KHR                      0x0920
  62 #define CL_PLATFORM_NOT_FOUND_KHR                       -1001
  63
  64
  65 /* cl_khr_fp64 */
  66 #define CL_DEVICE_DOUBLE_FP_CONFIG                      0x1032
  67
  68 /* cl_khr_fp16 */
  69 #define CL_DEVICE_HALF_FP_CONFIG                        0x1033
  70
  71 /* cl_khr_terminate_context */
  72 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR              0x200F
  73
  74 /* cl_nv_device_attribute_query */
  75 #define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV           0x4000
  76 #define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV           0x4001
  77 #define CL_DEVICE_REGISTERS_PER_BLOCK_NV                0x4002
  78 #define CL_DEVICE_WARP_SIZE_NV                          0x4003
  79 #define CL_DEVICE_GPU_OVERLAP_NV                        0x4004
  80 #define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV                0x4005
  81 #define CL_DEVICE_INTEGRATED_MEMORY_NV                  0x4006
  82 #define CL_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT_NV       0x4007
  83 #define CL_DEVICE_PCI_BUS_ID_NV                         0x4008
  84 #define CL_DEVICE_PCI_SLOT_ID_NV                        0x4009
  85
  86 /* cl_ext_atomic_counters_{32,64} */
  87 #define CL_DEVICE_MAX_ATOMIC_COUNTERS_EXT               0x4032
  88
  89 /* cl_amd_device_attribute_query */
  90 #define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD            0x4036
  91 #define CL_DEVICE_TOPOLOGY_AMD                          0x4037
  92 #define CL_DEVICE_BOARD_NAME_AMD                        0x4038
  93 #define CL_DEVICE_GLOBAL_FREE_MEMORY_AMD                0x4039
  94 #define CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD             0x4040
  95 #define CL_DEVICE_SIMD_WIDTH_AMD                        0x4041
  96 #define CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD            0x4042
  97 #define CL_DEVICE_WAVEFRONT_WIDTH_AMD                   0x4043
  98 #define CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD               0x4044
  99 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD          0x4045
 100 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD     0x4046
 101 #define CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD   0x4047
 102 #define CL_DEVICE_LOCAL_MEM_BANKS_AMD                   0x4048
 103 #define CL_DEVICE_THREAD_TRACE_SUPPORTED_AMD            0x4049
 104 #define CL_DEVICE_GFXIP_MAJOR_AMD                       0x404A
 105 #define CL_DEVICE_GFXIP_MINOR_AMD                       0x404B
 106 #define CL_DEVICE_AVAILABLE_ASYNC_QUEUES_AMD            0x404C
 107
 108 #ifndef CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD
 109 #define CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD                1
 110
 111 typedef union
 112 {
 113         struct { cl_uint type; cl_uint data[5]; } raw;
 114         struct { cl_uint type; cl_char unused[17]; cl_char bus; cl_char device; cl_char function; } pcie;
 115 } cl_device_topology_amd;
 116 #endif
 117
 118 /* cl_amd_offline_devices */
 119 #define CL_CONTEXT_OFFLINE_DEVICES_AMD                  0x403F
 120
 121 /* cl_ext_device_fission */
 122 #define cl_ext_device_fission                           1
 123
 124 typedef cl_ulong  cl_device_partition_property_ext;
 125
 126 #define CL_DEVICE_PARTITION_EQUALLY_EXT                 0x4050
 127 #define CL_DEVICE_PARTITION_BY_COUNTS_EXT               0x4051
 128 #define CL_DEVICE_PARTITION_BY_NAMES_EXT                0x4052
 129 #define CL_DEVICE_PARTITION_BY_NAMES_INTEL              0x4052 /* cl_intel_device_partition_by_names */
 130 #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT      0x4053
 131
 132 #define CL_DEVICE_PARENT_DEVICE_EXT                     0x4054
 133 #define CL_DEVICE_PARTITION_TYPES_EXT                   0x4055
 134 #define CL_DEVICE_AFFINITY_DOMAINS_EXT                  0x4056
 135 #define CL_DEVICE_REFERENCE_COUNT_EXT                   0x4057
 136 #define CL_DEVICE_PARTITION_STYLE_EXT                   0x4058
 137
 138 #define CL_AFFINITY_DOMAIN_L1_CACHE_EXT                 0x1
 139 #define CL_AFFINITY_DOMAIN_L2_CACHE_EXT                 0x2
 140 #define CL_AFFINITY_DOMAIN_L3_CACHE_EXT                 0x3
 141 #define CL_AFFINITY_DOMAIN_L4_CACHE_EXT                 0x4
 142 #define CL_AFFINITY_DOMAIN_NUMA_EXT                     0x10
 143 #define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT         0x100
 144
 145 /* cl_intel_advanced_motion_estimation */
 146 #define CL_DEVICE_ME_VERSION_INTEL                      0x407E
 147
 148 /* cl_qcom_ext_host_ptr */
 149 #define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM         0x40A0
 150 #define CL_DEVICE_PAGE_SIZE_QCOM                        0x40A1
 151
 152 /* cl_khr_spir */
 153 #define CL_DEVICE_SPIR_VERSIONS                         0x40E0
 154
 155 /* cl_altera_device_temperature */
 156 #define CL_DEVICE_CORE_TEMPERATURE_ALTERA               0x40F3
 157
 158 /* cl_intel_simultaneous_sharing */
 159 #define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL           0x4104
 160 #define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL       0x4105
 161