git.oblomov.eu Git - clinfo/blob - src/ext.h

   1 /* Include OpenCL header, and define OpenCL extensions, since what is and is not
   2  * available in the official headers is very system-dependent */
   3
   4 #ifndef _EXT_H
   5 #define _EXT_H
   6
   7 /* We will use the deprecated clGetExtensionFunctionAddress,
   8  * so let the headers know that we don't care about it being deprecated.
   9  * The standard CL_USE_DEPRECATED_OPENCL_1_1_APIS define apparently
  10  * doesn't work for macOS, so we'll just tell the compiler to not
  11  * warn about deprecated functions.
  12  * A more correct solution would be to suppress the warning only around the
  13  * clGetExtensionFunctionAddress call, but honestly I just cleaned up that
  14  * piece of code. And I'm actually wondering if it even makes sense to
  15  * build that part of the code on macOS: does anybody actually use
  16  * ocl-icd as OpenCL dispatcher on macOS?
  17  */
  18
  19 #ifdef __APPLE__
  20 #pragma GCC diagnostic ignored "-Wdeprecated-declarations"
  21 #include <OpenCL/opencl.h>
  22 #else
  23 #define CL_USE_DEPRECATED_OPENCL_1_1_APIS
  24 #include <CL/cl.h>
  25 #endif
  26
  27 /* These two defines were introduced in the 1.2 headers
  28  * on 2012-11-30, so earlier versions don't have them
  29  * (e.g. Debian wheezy)
  30  */
  31
  32 #ifndef CL_DEVICE_IMAGE_PITCH_ALIGNMENT
  33 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT                 0x104A
  34 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT          0x104B
  35 #endif
  36
  37 /* 2.0 headers are not very common for the time being, so
  38  * let's copy the defines for the new CL_DEVICE_* properties
  39  * here.
  40  */
  41 #ifndef CL_VERSION_2_0
  42 #define CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS             0x104C
  43 #define CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE              0x104D
  44 #define CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES            0x104E
  45 #define CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE        0x104F
  46 #define CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE              0x1050
  47 #define CL_DEVICE_MAX_ON_DEVICE_QUEUES                  0x1051
  48 #define CL_DEVICE_MAX_ON_DEVICE_EVENTS                  0x1052
  49 #define CL_DEVICE_SVM_CAPABILITIES                      0x1053
  50 #define CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE  0x1054
  51 #define CL_DEVICE_MAX_PIPE_ARGS                         0x1055
  52 #define CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS          0x1056
  53 #define CL_DEVICE_PIPE_MAX_PACKET_SIZE                  0x1057
  54 #define CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT   0x1058
  55 #define CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT     0x1059
  56 #define CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT      0x105A
  57
  58 #define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER           (1 << 0)
  59 #define CL_DEVICE_SVM_FINE_GRAIN_BUFFER             (1 << 1)
  60 #define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM             (1 << 2)
  61 #define CL_DEVICE_SVM_ATOMICS                       (1 << 3)
  62
  63 typedef cl_bitfield         cl_device_svm_capabilities;
  64 #endif
  65
  66 #ifndef CL_VERSION_2_1
  67 #define CL_PLATFORM_HOST_TIMER_RESOLUTION               0x0905
  68 #define CL_DEVICE_IL_VERSION                            0x105B
  69 #define CL_DEVICE_MAX_NUM_SUB_GROUPS                    0x105C
  70 #define CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS 0x105D
  71 #endif
  72
  73 /*
  74  * Extensions
  75  */
  76
  77 /* cl_khr_icd */
  78 #define CL_PLATFORM_ICD_SUFFIX_KHR                      0x0920
  79 #define CL_PLATFORM_NOT_FOUND_KHR                       -1001
  80
  81 /* cl_amd_object_metadata */
  82 #define CL_PLATFORM_MAX_KEYS_AMD                        0x403C
  83
  84 /* cl_khr_fp64 */
  85 #define CL_DEVICE_DOUBLE_FP_CONFIG                      0x1032
  86
  87 /* cl_khr_fp16 */
  88 #define CL_DEVICE_HALF_FP_CONFIG                        0x1033
  89
  90 /* cl_khr_il_program */
  91 #define CL_DEVICE_IL_VERSION_KHR                        0x105B
  92
  93 /* cl_khr_terminate_context */
  94 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR_1x           0x200F
  95 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR_2x           0x2031
  96
  97 /* TODO: I cannot find official definitions for these,
  98  * so I'm currently extrapolating them from the specification
  99  */
 100 typedef cl_bitfield cl_device_terminate_capability_khr;
 101 #define CL_DEVICE_TERMINATE_CAPABILITY_CONTEXT_KHR      (1<<0)
 102
 103 /* cl_khr_subgroup_named_barrier */
 104 #define CL_DEVICE_MAX_NAMED_BARRIER_COUNT_KHR           0x2035
 105
 106 /* cl_nv_device_attribute_query */
 107 #define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV           0x4000
 108 #define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV           0x4001
 109 #define CL_DEVICE_REGISTERS_PER_BLOCK_NV                0x4002
 110 #define CL_DEVICE_WARP_SIZE_NV                          0x4003
 111 #define CL_DEVICE_GPU_OVERLAP_NV                        0x4004
 112 #define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV                0x4005
 113 #define CL_DEVICE_INTEGRATED_MEMORY_NV                  0x4006
 114 #define CL_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT_NV       0x4007
 115 #define CL_DEVICE_PCI_BUS_ID_NV                         0x4008
 116 #define CL_DEVICE_PCI_SLOT_ID_NV                        0x4009
 117
 118 /* cl_ext_atomic_counters_{32,64} */
 119 #define CL_DEVICE_MAX_ATOMIC_COUNTERS_EXT               0x4032
 120
 121 /* cl_amd_device_attribute_query */
 122 #define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD            0x4036
 123 #define CL_DEVICE_TOPOLOGY_AMD                          0x4037
 124 #define CL_DEVICE_BOARD_NAME_AMD                        0x4038
 125 #define CL_DEVICE_GLOBAL_FREE_MEMORY_AMD                0x4039
 126 #define CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD             0x4040
 127 #define CL_DEVICE_SIMD_WIDTH_AMD                        0x4041
 128 #define CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD            0x4042
 129 #define CL_DEVICE_WAVEFRONT_WIDTH_AMD                   0x4043
 130 #define CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD               0x4044
 131 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD          0x4045
 132 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD     0x4046
 133 #define CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD   0x4047
 134 #define CL_DEVICE_LOCAL_MEM_BANKS_AMD                   0x4048
 135 #define CL_DEVICE_THREAD_TRACE_SUPPORTED_AMD            0x4049
 136 #define CL_DEVICE_GFXIP_MAJOR_AMD                       0x404A
 137 #define CL_DEVICE_GFXIP_MINOR_AMD                       0x404B
 138 #define CL_DEVICE_AVAILABLE_ASYNC_QUEUES_AMD            0x404C
 139 /* These two are undocumented */
 140 #define CL_DEVICE_MAX_REAL_TIME_COMPUTE_QUEUES_AMD      0x404D
 141 #define CL_DEVICE_MAX_REAL_TIME_COMPUTE_UNITS_AMD       0x404E
 142 /* These were added in v4 of the extension, but have values lower than
 143  * than the older ones, and spanning around the cl_ext_atomic_counters_*
 144  * define
 145  */
 146 #define CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_AMD         0x4030
 147 #define CL_DEVICE_MAX_WORK_GROUP_SIZE_AMD               0x4031
 148 #define CL_DEVICE_PREFERRED_CONSTANT_BUFFER_SIZE_AMD    0x4033
 149 #define CL_DEVICE_PCIE_ID_AMD                           0x4034
 150
 151 #ifndef CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD
 152 #define CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD                1
 153
 154 typedef union
 155 {
 156         struct { cl_uint type; cl_uint data[5]; } raw;
 157         struct { cl_uint type; cl_char unused[17]; cl_char bus; cl_char device; cl_char function; } pcie;
 158 } cl_device_topology_amd;
 159 #endif
 160
 161 /* cl_amd_offline_devices */
 162 #define CL_CONTEXT_OFFLINE_DEVICES_AMD                  0x403F
 163
 164 /* cl_amd_copy_buffer_p2p */
 165 #define CL_DEVICE_NUM_P2P_DEVICES_AMD                   0x4088
 166 #define CL_DEVICE_P2P_DEVICES_AMD                       0x4089
 167
 168 /* cl_ext_device_fission */
 169 #define cl_ext_device_fission                           1
 170
 171 typedef cl_ulong  cl_device_partition_property_ext;
 172
 173 #define CL_DEVICE_PARTITION_EQUALLY_EXT                 0x4050
 174 #define CL_DEVICE_PARTITION_BY_COUNTS_EXT               0x4051
 175 #define CL_DEVICE_PARTITION_BY_NAMES_EXT                0x4052
 176 #define CL_DEVICE_PARTITION_BY_NAMES_INTEL              0x4052 /* cl_intel_device_partition_by_names */
 177 #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT      0x4053
 178
 179 #define CL_DEVICE_PARENT_DEVICE_EXT                     0x4054
 180 #define CL_DEVICE_PARTITION_TYPES_EXT                   0x4055
 181 #define CL_DEVICE_AFFINITY_DOMAINS_EXT                  0x4056
 182 #define CL_DEVICE_REFERENCE_COUNT_EXT                   0x4057
 183 #define CL_DEVICE_PARTITION_STYLE_EXT                   0x4058
 184
 185 #define CL_AFFINITY_DOMAIN_L1_CACHE_EXT                 0x1
 186 #define CL_AFFINITY_DOMAIN_L2_CACHE_EXT                 0x2
 187 #define CL_AFFINITY_DOMAIN_L3_CACHE_EXT                 0x3
 188 #define CL_AFFINITY_DOMAIN_L4_CACHE_EXT                 0x4
 189 #define CL_AFFINITY_DOMAIN_NUMA_EXT                     0x10
 190 #define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT         0x100
 191
 192 /* cl_intel_advanced_motion_estimation */
 193 #define CL_DEVICE_ME_VERSION_INTEL                      0x407E
 194
 195 /* cl_intel_device_side_avc_motion_estimation */
 196 #define CL_DEVICE_AVC_ME_VERSION_INTEL                          0x410B
 197 #define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL     0x410C
 198 #define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL              0x410D
 199
 200 /* cl_intel_planar_yuv */
 201 #define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL            0x417E
 202 #define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL           0x417F
 203
 204 /* cl_qcom_ext_host_ptr */
 205 #define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM         0x40A0
 206 #define CL_DEVICE_PAGE_SIZE_QCOM                        0x40A1
 207
 208 /* cl_arm_shared_virtual_memory */
 209 #define CL_DEVICE_SVM_CAPABILITIES_ARM                  0x40B6
 210
 211 /* cl_khr_spir */
 212 #define CL_DEVICE_SPIR_VERSIONS                         0x40E0
 213
 214 /* cl_altera_device_temperature */
 215 #define CL_DEVICE_CORE_TEMPERATURE_ALTERA               0x40F3
 216
 217 /* cl_intel_simultaneous_sharing */
 218 #define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL           0x4104
 219 #define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL       0x4105
 220
 221 /* cl_intel_required_subgroup_size */
 222 #define CL_DEVICE_SUB_GROUP_SIZES_INTEL                 0x4108
 223
 224 #endif