1 /* Include OpenCL header, and define OpenCL extensions, since what is and is not
2 * available in the official headers is very system-dependent */
5 #include <OpenCL/opencl.h>
10 /* These two defines were introduced in the 1.2 headers
11 * on 2012-11-30, so earlier versions don't have them
12 * (e.g. Debian wheezy)
15 #ifndef CL_DEVICE_IMAGE_PITCH_ALIGNMENT
16 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT 0x104A
17 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT 0x104B
20 /* 2.0 headers are not very common for the time being, so
21 * let's copy the defines for the new CL_DEVICE_* properties
24 #ifndef CL_VERSION_2_0
25 #define CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS 0x104C
26 #define CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE 0x104D
27 #define CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES 0x104E
28 #define CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE 0x104F
29 #define CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE 0x1050
30 #define CL_DEVICE_MAX_ON_DEVICE_QUEUES 0x1051
31 #define CL_DEVICE_MAX_ON_DEVICE_EVENTS 0x1052
32 #define CL_DEVICE_SVM_CAPABILITIES 0x1053
33 #define CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE 0x1054
34 #define CL_DEVICE_MAX_PIPE_ARGS 0x1055
35 #define CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS 0x1056
36 #define CL_DEVICE_PIPE_MAX_PACKET_SIZE 0x1057
37 #define CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT 0x1058
38 #define CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT 0x1059
39 #define CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT 0x105A
41 #define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER (1 << 0)
42 #define CL_DEVICE_SVM_FINE_GRAIN_BUFFER (1 << 1)
43 #define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM (1 << 2)
44 #define CL_DEVICE_SVM_ATOMICS (1 << 3)
46 typedef cl_bitfield cl_device_svm_capabilities;
54 #define CL_PLATFORM_ICD_SUFFIX_KHR 0x0920
57 #define CL_DEVICE_DOUBLE_FP_CONFIG 0x1032
60 #define CL_DEVICE_HALF_FP_CONFIG 0x1033
62 /* cl_khr_terminate_context */
63 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR 0x200F
65 /* cl_nv_device_attribute_query */
66 #define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV 0x4000
67 #define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV 0x4001
68 #define CL_DEVICE_REGISTERS_PER_BLOCK_NV 0x4002
69 #define CL_DEVICE_WARP_SIZE_NV 0x4003
70 #define CL_DEVICE_GPU_OVERLAP_NV 0x4004
71 #define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV 0x4005
72 #define CL_DEVICE_INTEGRATED_MEMORY_NV 0x4006
73 #define CL_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT_NV 0x4007
74 #define CL_DEVICE_PCI_BUS_ID_NV 0x4008
75 #define CL_DEVICE_PCI_SLOT_ID_NV 0x4009
77 /* cl_ext_atomic_counters_{32,64} */
78 #define CL_DEVICE_MAX_ATOMIC_COUNTERS_EXT 0x4032
80 /* cl_amd_device_attribute_query */
81 #define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD 0x4036
82 #define CL_DEVICE_TOPOLOGY_AMD 0x4037
83 #define CL_DEVICE_BOARD_NAME_AMD 0x4038
84 #define CL_DEVICE_GLOBAL_FREE_MEMORY_AMD 0x4039
85 #define CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD 0x4040
86 #define CL_DEVICE_SIMD_WIDTH_AMD 0x4041
87 #define CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD 0x4042
88 #define CL_DEVICE_WAVEFRONT_WIDTH_AMD 0x4043
89 #define CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD 0x4044
90 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD 0x4045
91 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD 0x4046
92 #define CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD 0x4047
93 #define CL_DEVICE_LOCAL_MEM_BANKS_AMD 0x4048
95 #ifndef CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD
96 #define CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD 1
100 struct { cl_uint type; cl_uint data[5]; } raw;
101 struct { cl_uint type; cl_char unused[17]; cl_char bus; cl_char device; cl_char function; } pcie;
102 } cl_device_topology_amd;
105 /* cl_ext_device_fission */
106 #define cl_ext_device_fission 1
108 typedef cl_ulong cl_device_partition_property_ext;
110 #define CL_DEVICE_PARTITION_EQUALLY_EXT 0x4050
111 #define CL_DEVICE_PARTITION_BY_COUNTS_EXT 0x4051
112 #define CL_DEVICE_PARTITION_BY_NAMES_EXT 0x4052
113 #define CL_DEVICE_PARTITION_BY_NAMES_INTEL 0x4052 /* cl_intel_device_partition_by_names */
114 #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT 0x4053
116 #define CL_DEVICE_PARENT_DEVICE_EXT 0x4054
117 #define CL_DEVICE_PARTITION_TYPES_EXT 0x4055
118 #define CL_DEVICE_AFFINITY_DOMAINS_EXT 0x4056
119 #define CL_DEVICE_REFERENCE_COUNT_EXT 0x4057
120 #define CL_DEVICE_PARTITION_STYLE_EXT 0x4058
122 #define CL_AFFINITY_DOMAIN_L1_CACHE_EXT 0x1
123 #define CL_AFFINITY_DOMAIN_L2_CACHE_EXT 0x2
124 #define CL_AFFINITY_DOMAIN_L3_CACHE_EXT 0x3
125 #define CL_AFFINITY_DOMAIN_L4_CACHE_EXT 0x4
126 #define CL_AFFINITY_DOMAIN_NUMA_EXT 0x10
127 #define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT 0x100
129 /* cl_qcom_ext_host_ptr */
130 #define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM 0x40A0
131 #define CL_DEVICE_PAGE_SIZE_QCOM 0x40A1
134 #define CL_DEVICE_SPIR_VERSIONS 0x40E0
136 /* cl_altera_device_temperature */
137 #define CL_DEVICE_CORE_TEMPERATURE_ALTERA 0x40F3