drm/i915: unpin for an invalid memory domain.
[linux-2.6] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include <linux/swap.h>
33 #include <linux/pci.h>
34
35 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
36
37 static void
38 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
39                                   uint32_t read_domains,
40                                   uint32_t write_domain);
41 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
44 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45                                              int write);
46 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47                                                      uint64_t offset,
48                                                      uint64_t size);
49 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
50 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
51 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
52 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54                                            unsigned alignment);
55 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
56 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
57 static int i915_gem_evict_something(struct drm_device *dev);
58 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
59                                 struct drm_i915_gem_pwrite *args,
60                                 struct drm_file *file_priv);
61
62 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63                      unsigned long end)
64 {
65         drm_i915_private_t *dev_priv = dev->dev_private;
66
67         if (start >= end ||
68             (start & (PAGE_SIZE - 1)) != 0 ||
69             (end & (PAGE_SIZE - 1)) != 0) {
70                 return -EINVAL;
71         }
72
73         drm_mm_init(&dev_priv->mm.gtt_space, start,
74                     end - start);
75
76         dev->gtt_total = (uint32_t) (end - start);
77
78         return 0;
79 }
80
81 int
82 i915_gem_init_ioctl(struct drm_device *dev, void *data,
83                     struct drm_file *file_priv)
84 {
85         struct drm_i915_gem_init *args = data;
86         int ret;
87
88         mutex_lock(&dev->struct_mutex);
89         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
90         mutex_unlock(&dev->struct_mutex);
91
92         return ret;
93 }
94
95 int
96 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97                             struct drm_file *file_priv)
98 {
99         struct drm_i915_gem_get_aperture *args = data;
100
101         if (!(dev->driver->driver_features & DRIVER_GEM))
102                 return -ENODEV;
103
104         args->aper_size = dev->gtt_total;
105         args->aper_available_size = (args->aper_size -
106                                      atomic_read(&dev->pin_memory));
107
108         return 0;
109 }
110
111
112 /**
113  * Creates a new mm object and returns a handle to it.
114  */
115 int
116 i915_gem_create_ioctl(struct drm_device *dev, void *data,
117                       struct drm_file *file_priv)
118 {
119         struct drm_i915_gem_create *args = data;
120         struct drm_gem_object *obj;
121         int handle, ret;
122
123         args->size = roundup(args->size, PAGE_SIZE);
124
125         /* Allocate the new object */
126         obj = drm_gem_object_alloc(dev, args->size);
127         if (obj == NULL)
128                 return -ENOMEM;
129
130         ret = drm_gem_handle_create(file_priv, obj, &handle);
131         mutex_lock(&dev->struct_mutex);
132         drm_gem_object_handle_unreference(obj);
133         mutex_unlock(&dev->struct_mutex);
134
135         if (ret)
136                 return ret;
137
138         args->handle = handle;
139
140         return 0;
141 }
142
143 /**
144  * Reads data from the object referenced by handle.
145  *
146  * On error, the contents of *data are undefined.
147  */
148 int
149 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
150                      struct drm_file *file_priv)
151 {
152         struct drm_i915_gem_pread *args = data;
153         struct drm_gem_object *obj;
154         struct drm_i915_gem_object *obj_priv;
155         ssize_t read;
156         loff_t offset;
157         int ret;
158
159         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
160         if (obj == NULL)
161                 return -EBADF;
162         obj_priv = obj->driver_private;
163
164         /* Bounds check source.
165          *
166          * XXX: This could use review for overflow issues...
167          */
168         if (args->offset > obj->size || args->size > obj->size ||
169             args->offset + args->size > obj->size) {
170                 drm_gem_object_unreference(obj);
171                 return -EINVAL;
172         }
173
174         mutex_lock(&dev->struct_mutex);
175
176         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
177                                                         args->size);
178         if (ret != 0) {
179                 drm_gem_object_unreference(obj);
180                 mutex_unlock(&dev->struct_mutex);
181                 return ret;
182         }
183
184         offset = args->offset;
185
186         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
187                         args->size, &offset);
188         if (read != args->size) {
189                 drm_gem_object_unreference(obj);
190                 mutex_unlock(&dev->struct_mutex);
191                 if (read < 0)
192                         return read;
193                 else
194                         return -EINVAL;
195         }
196
197         drm_gem_object_unreference(obj);
198         mutex_unlock(&dev->struct_mutex);
199
200         return 0;
201 }
202
203 /* This is the fast write path which cannot handle
204  * page faults in the source data
205  */
206
207 static inline int
208 fast_user_write(struct io_mapping *mapping,
209                 loff_t page_base, int page_offset,
210                 char __user *user_data,
211                 int length)
212 {
213         char *vaddr_atomic;
214         unsigned long unwritten;
215
216         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
217         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
218                                                       user_data, length);
219         io_mapping_unmap_atomic(vaddr_atomic);
220         if (unwritten)
221                 return -EFAULT;
222         return 0;
223 }
224
225 /* Here's the write path which can sleep for
226  * page faults
227  */
228
229 static inline int
230 slow_user_write(struct io_mapping *mapping,
231                 loff_t page_base, int page_offset,
232                 char __user *user_data,
233                 int length)
234 {
235         char __iomem *vaddr;
236         unsigned long unwritten;
237
238         vaddr = io_mapping_map_wc(mapping, page_base);
239         if (vaddr == NULL)
240                 return -EFAULT;
241         unwritten = __copy_from_user(vaddr + page_offset,
242                                      user_data, length);
243         io_mapping_unmap(vaddr);
244         if (unwritten)
245                 return -EFAULT;
246         return 0;
247 }
248
249 static int
250 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
251                     struct drm_i915_gem_pwrite *args,
252                     struct drm_file *file_priv)
253 {
254         struct drm_i915_gem_object *obj_priv = obj->driver_private;
255         drm_i915_private_t *dev_priv = dev->dev_private;
256         ssize_t remain;
257         loff_t offset, page_base;
258         char __user *user_data;
259         int page_offset, page_length;
260         int ret;
261
262         user_data = (char __user *) (uintptr_t) args->data_ptr;
263         remain = args->size;
264         if (!access_ok(VERIFY_READ, user_data, remain))
265                 return -EFAULT;
266
267
268         mutex_lock(&dev->struct_mutex);
269         ret = i915_gem_object_pin(obj, 0);
270         if (ret) {
271                 mutex_unlock(&dev->struct_mutex);
272                 return ret;
273         }
274         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
275         if (ret)
276                 goto fail;
277
278         obj_priv = obj->driver_private;
279         offset = obj_priv->gtt_offset + args->offset;
280         obj_priv->dirty = 1;
281
282         while (remain > 0) {
283                 /* Operation in this page
284                  *
285                  * page_base = page offset within aperture
286                  * page_offset = offset within page
287                  * page_length = bytes to copy for this page
288                  */
289                 page_base = (offset & ~(PAGE_SIZE-1));
290                 page_offset = offset & (PAGE_SIZE-1);
291                 page_length = remain;
292                 if ((page_offset + remain) > PAGE_SIZE)
293                         page_length = PAGE_SIZE - page_offset;
294
295                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
296                                        page_offset, user_data, page_length);
297
298                 /* If we get a fault while copying data, then (presumably) our
299                  * source page isn't available. In this case, use the
300                  * non-atomic function
301                  */
302                 if (ret) {
303                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
304                                                page_base, page_offset,
305                                                user_data, page_length);
306                         if (ret)
307                                 goto fail;
308                 }
309
310                 remain -= page_length;
311                 user_data += page_length;
312                 offset += page_length;
313         }
314
315 fail:
316         i915_gem_object_unpin(obj);
317         mutex_unlock(&dev->struct_mutex);
318
319         return ret;
320 }
321
322 static int
323 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
324                       struct drm_i915_gem_pwrite *args,
325                       struct drm_file *file_priv)
326 {
327         int ret;
328         loff_t offset;
329         ssize_t written;
330
331         mutex_lock(&dev->struct_mutex);
332
333         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
334         if (ret) {
335                 mutex_unlock(&dev->struct_mutex);
336                 return ret;
337         }
338
339         offset = args->offset;
340
341         written = vfs_write(obj->filp,
342                             (char __user *)(uintptr_t) args->data_ptr,
343                             args->size, &offset);
344         if (written != args->size) {
345                 mutex_unlock(&dev->struct_mutex);
346                 if (written < 0)
347                         return written;
348                 else
349                         return -EINVAL;
350         }
351
352         mutex_unlock(&dev->struct_mutex);
353
354         return 0;
355 }
356
357 /**
358  * Writes data to the object referenced by handle.
359  *
360  * On error, the contents of the buffer that were to be modified are undefined.
361  */
362 int
363 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
364                       struct drm_file *file_priv)
365 {
366         struct drm_i915_gem_pwrite *args = data;
367         struct drm_gem_object *obj;
368         struct drm_i915_gem_object *obj_priv;
369         int ret = 0;
370
371         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
372         if (obj == NULL)
373                 return -EBADF;
374         obj_priv = obj->driver_private;
375
376         /* Bounds check destination.
377          *
378          * XXX: This could use review for overflow issues...
379          */
380         if (args->offset > obj->size || args->size > obj->size ||
381             args->offset + args->size > obj->size) {
382                 drm_gem_object_unreference(obj);
383                 return -EINVAL;
384         }
385
386         /* We can only do the GTT pwrite on untiled buffers, as otherwise
387          * it would end up going through the fenced access, and we'll get
388          * different detiling behavior between reading and writing.
389          * pread/pwrite currently are reading and writing from the CPU
390          * perspective, requiring manual detiling by the client.
391          */
392         if (obj_priv->phys_obj)
393                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
394         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
395                  dev->gtt_total != 0)
396                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
397         else
398                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
399
400 #if WATCH_PWRITE
401         if (ret)
402                 DRM_INFO("pwrite failed %d\n", ret);
403 #endif
404
405         drm_gem_object_unreference(obj);
406
407         return ret;
408 }
409
410 /**
411  * Called when user space prepares to use an object with the CPU, either
412  * through the mmap ioctl's mapping or a GTT mapping.
413  */
414 int
415 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
416                           struct drm_file *file_priv)
417 {
418         struct drm_i915_gem_set_domain *args = data;
419         struct drm_gem_object *obj;
420         uint32_t read_domains = args->read_domains;
421         uint32_t write_domain = args->write_domain;
422         int ret;
423
424         if (!(dev->driver->driver_features & DRIVER_GEM))
425                 return -ENODEV;
426
427         /* Only handle setting domains to types used by the CPU. */
428         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
429                 return -EINVAL;
430
431         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
432                 return -EINVAL;
433
434         /* Having something in the write domain implies it's in the read
435          * domain, and only that read domain.  Enforce that in the request.
436          */
437         if (write_domain != 0 && read_domains != write_domain)
438                 return -EINVAL;
439
440         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
441         if (obj == NULL)
442                 return -EBADF;
443
444         mutex_lock(&dev->struct_mutex);
445 #if WATCH_BUF
446         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
447                  obj, obj->size, read_domains, write_domain);
448 #endif
449         if (read_domains & I915_GEM_DOMAIN_GTT) {
450                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
451
452                 /* Silently promote "you're not bound, there was nothing to do"
453                  * to success, since the client was just asking us to
454                  * make sure everything was done.
455                  */
456                 if (ret == -EINVAL)
457                         ret = 0;
458         } else {
459                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
460         }
461
462         drm_gem_object_unreference(obj);
463         mutex_unlock(&dev->struct_mutex);
464         return ret;
465 }
466
467 /**
468  * Called when user space has done writes to this buffer
469  */
470 int
471 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
472                       struct drm_file *file_priv)
473 {
474         struct drm_i915_gem_sw_finish *args = data;
475         struct drm_gem_object *obj;
476         struct drm_i915_gem_object *obj_priv;
477         int ret = 0;
478
479         if (!(dev->driver->driver_features & DRIVER_GEM))
480                 return -ENODEV;
481
482         mutex_lock(&dev->struct_mutex);
483         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
484         if (obj == NULL) {
485                 mutex_unlock(&dev->struct_mutex);
486                 return -EBADF;
487         }
488
489 #if WATCH_BUF
490         DRM_INFO("%s: sw_finish %d (%p %d)\n",
491                  __func__, args->handle, obj, obj->size);
492 #endif
493         obj_priv = obj->driver_private;
494
495         /* Pinned buffers may be scanout, so flush the cache */
496         if (obj_priv->pin_count)
497                 i915_gem_object_flush_cpu_write_domain(obj);
498
499         drm_gem_object_unreference(obj);
500         mutex_unlock(&dev->struct_mutex);
501         return ret;
502 }
503
504 /**
505  * Maps the contents of an object, returning the address it is mapped
506  * into.
507  *
508  * While the mapping holds a reference on the contents of the object, it doesn't
509  * imply a ref on the object itself.
510  */
511 int
512 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
513                    struct drm_file *file_priv)
514 {
515         struct drm_i915_gem_mmap *args = data;
516         struct drm_gem_object *obj;
517         loff_t offset;
518         unsigned long addr;
519
520         if (!(dev->driver->driver_features & DRIVER_GEM))
521                 return -ENODEV;
522
523         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
524         if (obj == NULL)
525                 return -EBADF;
526
527         offset = args->offset;
528
529         down_write(&current->mm->mmap_sem);
530         addr = do_mmap(obj->filp, 0, args->size,
531                        PROT_READ | PROT_WRITE, MAP_SHARED,
532                        args->offset);
533         up_write(&current->mm->mmap_sem);
534         mutex_lock(&dev->struct_mutex);
535         drm_gem_object_unreference(obj);
536         mutex_unlock(&dev->struct_mutex);
537         if (IS_ERR((void *)addr))
538                 return addr;
539
540         args->addr_ptr = (uint64_t) addr;
541
542         return 0;
543 }
544
545 /**
546  * i915_gem_fault - fault a page into the GTT
547  * vma: VMA in question
548  * vmf: fault info
549  *
550  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
551  * from userspace.  The fault handler takes care of binding the object to
552  * the GTT (if needed), allocating and programming a fence register (again,
553  * only if needed based on whether the old reg is still valid or the object
554  * is tiled) and inserting a new PTE into the faulting process.
555  *
556  * Note that the faulting process may involve evicting existing objects
557  * from the GTT and/or fence registers to make room.  So performance may
558  * suffer if the GTT working set is large or there are few fence registers
559  * left.
560  */
561 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
562 {
563         struct drm_gem_object *obj = vma->vm_private_data;
564         struct drm_device *dev = obj->dev;
565         struct drm_i915_private *dev_priv = dev->dev_private;
566         struct drm_i915_gem_object *obj_priv = obj->driver_private;
567         pgoff_t page_offset;
568         unsigned long pfn;
569         int ret = 0;
570         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
571
572         /* We don't use vmf->pgoff since that has the fake offset */
573         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
574                 PAGE_SHIFT;
575
576         /* Now bind it into the GTT if needed */
577         mutex_lock(&dev->struct_mutex);
578         if (!obj_priv->gtt_space) {
579                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
580                 if (ret) {
581                         mutex_unlock(&dev->struct_mutex);
582                         return VM_FAULT_SIGBUS;
583                 }
584                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
585         }
586
587         /* Need a new fence register? */
588         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
589             obj_priv->tiling_mode != I915_TILING_NONE) {
590                 ret = i915_gem_object_get_fence_reg(obj, write);
591                 if (ret) {
592                         mutex_unlock(&dev->struct_mutex);
593                         return VM_FAULT_SIGBUS;
594                 }
595         }
596
597         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
598                 page_offset;
599
600         /* Finally, remap it using the new GTT offset */
601         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
602
603         mutex_unlock(&dev->struct_mutex);
604
605         switch (ret) {
606         case -ENOMEM:
607         case -EAGAIN:
608                 return VM_FAULT_OOM;
609         case -EFAULT:
610         case -EBUSY:
611                 DRM_ERROR("can't insert pfn??  fault or busy...\n");
612                 return VM_FAULT_SIGBUS;
613         default:
614                 return VM_FAULT_NOPAGE;
615         }
616 }
617
618 /**
619  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
620  * @obj: obj in question
621  *
622  * GEM memory mapping works by handing back to userspace a fake mmap offset
623  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
624  * up the object based on the offset and sets up the various memory mapping
625  * structures.
626  *
627  * This routine allocates and attaches a fake offset for @obj.
628  */
629 static int
630 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
631 {
632         struct drm_device *dev = obj->dev;
633         struct drm_gem_mm *mm = dev->mm_private;
634         struct drm_i915_gem_object *obj_priv = obj->driver_private;
635         struct drm_map_list *list;
636         struct drm_map *map;
637         int ret = 0;
638
639         /* Set the object up for mmap'ing */
640         list = &obj->map_list;
641         list->map = drm_calloc(1, sizeof(struct drm_map_list),
642                                DRM_MEM_DRIVER);
643         if (!list->map)
644                 return -ENOMEM;
645
646         map = list->map;
647         map->type = _DRM_GEM;
648         map->size = obj->size;
649         map->handle = obj;
650
651         /* Get a DRM GEM mmap offset allocated... */
652         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
653                                                     obj->size / PAGE_SIZE, 0, 0);
654         if (!list->file_offset_node) {
655                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
656                 ret = -ENOMEM;
657                 goto out_free_list;
658         }
659
660         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
661                                                   obj->size / PAGE_SIZE, 0);
662         if (!list->file_offset_node) {
663                 ret = -ENOMEM;
664                 goto out_free_list;
665         }
666
667         list->hash.key = list->file_offset_node->start;
668         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
669                 DRM_ERROR("failed to add to map hash\n");
670                 goto out_free_mm;
671         }
672
673         /* By now we should be all set, any drm_mmap request on the offset
674          * below will get to our mmap & fault handler */
675         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
676
677         return 0;
678
679 out_free_mm:
680         drm_mm_put_block(list->file_offset_node);
681 out_free_list:
682         drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
683
684         return ret;
685 }
686
687 /**
688  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
689  * @obj: object to check
690  *
691  * Return the required GTT alignment for an object, taking into account
692  * potential fence register mapping if needed.
693  */
694 static uint32_t
695 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
696 {
697         struct drm_device *dev = obj->dev;
698         struct drm_i915_gem_object *obj_priv = obj->driver_private;
699         int start, i;
700
701         /*
702          * Minimum alignment is 4k (GTT page size), but might be greater
703          * if a fence register is needed for the object.
704          */
705         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
706                 return 4096;
707
708         /*
709          * Previous chips need to be aligned to the size of the smallest
710          * fence register that can contain the object.
711          */
712         if (IS_I9XX(dev))
713                 start = 1024*1024;
714         else
715                 start = 512*1024;
716
717         for (i = start; i < obj->size; i <<= 1)
718                 ;
719
720         return i;
721 }
722
723 /**
724  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
725  * @dev: DRM device
726  * @data: GTT mapping ioctl data
727  * @file_priv: GEM object info
728  *
729  * Simply returns the fake offset to userspace so it can mmap it.
730  * The mmap call will end up in drm_gem_mmap(), which will set things
731  * up so we can get faults in the handler above.
732  *
733  * The fault handler will take care of binding the object into the GTT
734  * (since it may have been evicted to make room for something), allocating
735  * a fence register, and mapping the appropriate aperture address into
736  * userspace.
737  */
738 int
739 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
740                         struct drm_file *file_priv)
741 {
742         struct drm_i915_gem_mmap_gtt *args = data;
743         struct drm_i915_private *dev_priv = dev->dev_private;
744         struct drm_gem_object *obj;
745         struct drm_i915_gem_object *obj_priv;
746         int ret;
747
748         if (!(dev->driver->driver_features & DRIVER_GEM))
749                 return -ENODEV;
750
751         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
752         if (obj == NULL)
753                 return -EBADF;
754
755         mutex_lock(&dev->struct_mutex);
756
757         obj_priv = obj->driver_private;
758
759         if (!obj_priv->mmap_offset) {
760                 ret = i915_gem_create_mmap_offset(obj);
761                 if (ret) {
762                         drm_gem_object_unreference(obj);
763                         mutex_unlock(&dev->struct_mutex);
764                         return ret;
765                 }
766         }
767
768         args->offset = obj_priv->mmap_offset;
769
770         obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
771
772         /* Make sure the alignment is correct for fence regs etc */
773         if (obj_priv->agp_mem &&
774             (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
775                 drm_gem_object_unreference(obj);
776                 mutex_unlock(&dev->struct_mutex);
777                 return -EINVAL;
778         }
779
780         /*
781          * Pull it into the GTT so that we have a page list (makes the
782          * initial fault faster and any subsequent flushing possible).
783          */
784         if (!obj_priv->agp_mem) {
785                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
786                 if (ret) {
787                         drm_gem_object_unreference(obj);
788                         mutex_unlock(&dev->struct_mutex);
789                         return ret;
790                 }
791                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
792         }
793
794         drm_gem_object_unreference(obj);
795         mutex_unlock(&dev->struct_mutex);
796
797         return 0;
798 }
799
800 static void
801 i915_gem_object_free_page_list(struct drm_gem_object *obj)
802 {
803         struct drm_i915_gem_object *obj_priv = obj->driver_private;
804         int page_count = obj->size / PAGE_SIZE;
805         int i;
806
807         if (obj_priv->page_list == NULL)
808                 return;
809
810
811         for (i = 0; i < page_count; i++)
812                 if (obj_priv->page_list[i] != NULL) {
813                         if (obj_priv->dirty)
814                                 set_page_dirty(obj_priv->page_list[i]);
815                         mark_page_accessed(obj_priv->page_list[i]);
816                         page_cache_release(obj_priv->page_list[i]);
817                 }
818         obj_priv->dirty = 0;
819
820         drm_free(obj_priv->page_list,
821                  page_count * sizeof(struct page *),
822                  DRM_MEM_DRIVER);
823         obj_priv->page_list = NULL;
824 }
825
826 static void
827 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
828 {
829         struct drm_device *dev = obj->dev;
830         drm_i915_private_t *dev_priv = dev->dev_private;
831         struct drm_i915_gem_object *obj_priv = obj->driver_private;
832
833         /* Add a reference if we're newly entering the active list. */
834         if (!obj_priv->active) {
835                 drm_gem_object_reference(obj);
836                 obj_priv->active = 1;
837         }
838         /* Move from whatever list we were on to the tail of execution. */
839         list_move_tail(&obj_priv->list,
840                        &dev_priv->mm.active_list);
841         obj_priv->last_rendering_seqno = seqno;
842 }
843
844 static void
845 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
846 {
847         struct drm_device *dev = obj->dev;
848         drm_i915_private_t *dev_priv = dev->dev_private;
849         struct drm_i915_gem_object *obj_priv = obj->driver_private;
850
851         BUG_ON(!obj_priv->active);
852         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
853         obj_priv->last_rendering_seqno = 0;
854 }
855
856 static void
857 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
858 {
859         struct drm_device *dev = obj->dev;
860         drm_i915_private_t *dev_priv = dev->dev_private;
861         struct drm_i915_gem_object *obj_priv = obj->driver_private;
862
863         i915_verify_inactive(dev, __FILE__, __LINE__);
864         if (obj_priv->pin_count != 0)
865                 list_del_init(&obj_priv->list);
866         else
867                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
868
869         obj_priv->last_rendering_seqno = 0;
870         if (obj_priv->active) {
871                 obj_priv->active = 0;
872                 drm_gem_object_unreference(obj);
873         }
874         i915_verify_inactive(dev, __FILE__, __LINE__);
875 }
876
877 /**
878  * Creates a new sequence number, emitting a write of it to the status page
879  * plus an interrupt, which will trigger i915_user_interrupt_handler.
880  *
881  * Must be called with struct_lock held.
882  *
883  * Returned sequence numbers are nonzero on success.
884  */
885 static uint32_t
886 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
887 {
888         drm_i915_private_t *dev_priv = dev->dev_private;
889         struct drm_i915_gem_request *request;
890         uint32_t seqno;
891         int was_empty;
892         RING_LOCALS;
893
894         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
895         if (request == NULL)
896                 return 0;
897
898         /* Grab the seqno we're going to make this request be, and bump the
899          * next (skipping 0 so it can be the reserved no-seqno value).
900          */
901         seqno = dev_priv->mm.next_gem_seqno;
902         dev_priv->mm.next_gem_seqno++;
903         if (dev_priv->mm.next_gem_seqno == 0)
904                 dev_priv->mm.next_gem_seqno++;
905
906         BEGIN_LP_RING(4);
907         OUT_RING(MI_STORE_DWORD_INDEX);
908         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
909         OUT_RING(seqno);
910
911         OUT_RING(MI_USER_INTERRUPT);
912         ADVANCE_LP_RING();
913
914         DRM_DEBUG("%d\n", seqno);
915
916         request->seqno = seqno;
917         request->emitted_jiffies = jiffies;
918         was_empty = list_empty(&dev_priv->mm.request_list);
919         list_add_tail(&request->list, &dev_priv->mm.request_list);
920
921         /* Associate any objects on the flushing list matching the write
922          * domain we're flushing with our flush.
923          */
924         if (flush_domains != 0) {
925                 struct drm_i915_gem_object *obj_priv, *next;
926
927                 list_for_each_entry_safe(obj_priv, next,
928                                          &dev_priv->mm.flushing_list, list) {
929                         struct drm_gem_object *obj = obj_priv->obj;
930
931                         if ((obj->write_domain & flush_domains) ==
932                             obj->write_domain) {
933                                 obj->write_domain = 0;
934                                 i915_gem_object_move_to_active(obj, seqno);
935                         }
936                 }
937
938         }
939
940         if (was_empty && !dev_priv->mm.suspended)
941                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
942         return seqno;
943 }
944
945 /**
946  * Command execution barrier
947  *
948  * Ensures that all commands in the ring are finished
949  * before signalling the CPU
950  */
951 static uint32_t
952 i915_retire_commands(struct drm_device *dev)
953 {
954         drm_i915_private_t *dev_priv = dev->dev_private;
955         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
956         uint32_t flush_domains = 0;
957         RING_LOCALS;
958
959         /* The sampler always gets flushed on i965 (sigh) */
960         if (IS_I965G(dev))
961                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
962         BEGIN_LP_RING(2);
963         OUT_RING(cmd);
964         OUT_RING(0); /* noop */
965         ADVANCE_LP_RING();
966         return flush_domains;
967 }
968
969 /**
970  * Moves buffers associated only with the given active seqno from the active
971  * to inactive list, potentially freeing them.
972  */
973 static void
974 i915_gem_retire_request(struct drm_device *dev,
975                         struct drm_i915_gem_request *request)
976 {
977         drm_i915_private_t *dev_priv = dev->dev_private;
978
979         /* Move any buffers on the active list that are no longer referenced
980          * by the ringbuffer to the flushing/inactive lists as appropriate.
981          */
982         while (!list_empty(&dev_priv->mm.active_list)) {
983                 struct drm_gem_object *obj;
984                 struct drm_i915_gem_object *obj_priv;
985
986                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
987                                             struct drm_i915_gem_object,
988                                             list);
989                 obj = obj_priv->obj;
990
991                 /* If the seqno being retired doesn't match the oldest in the
992                  * list, then the oldest in the list must still be newer than
993                  * this seqno.
994                  */
995                 if (obj_priv->last_rendering_seqno != request->seqno)
996                         return;
997
998 #if WATCH_LRU
999                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1000                          __func__, request->seqno, obj);
1001 #endif
1002
1003                 if (obj->write_domain != 0)
1004                         i915_gem_object_move_to_flushing(obj);
1005                 else
1006                         i915_gem_object_move_to_inactive(obj);
1007         }
1008 }
1009
1010 /**
1011  * Returns true if seq1 is later than seq2.
1012  */
1013 static int
1014 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1015 {
1016         return (int32_t)(seq1 - seq2) >= 0;
1017 }
1018
1019 uint32_t
1020 i915_get_gem_seqno(struct drm_device *dev)
1021 {
1022         drm_i915_private_t *dev_priv = dev->dev_private;
1023
1024         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1025 }
1026
1027 /**
1028  * This function clears the request list as sequence numbers are passed.
1029  */
1030 void
1031 i915_gem_retire_requests(struct drm_device *dev)
1032 {
1033         drm_i915_private_t *dev_priv = dev->dev_private;
1034         uint32_t seqno;
1035
1036         seqno = i915_get_gem_seqno(dev);
1037
1038         while (!list_empty(&dev_priv->mm.request_list)) {
1039                 struct drm_i915_gem_request *request;
1040                 uint32_t retiring_seqno;
1041
1042                 request = list_first_entry(&dev_priv->mm.request_list,
1043                                            struct drm_i915_gem_request,
1044                                            list);
1045                 retiring_seqno = request->seqno;
1046
1047                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1048                     dev_priv->mm.wedged) {
1049                         i915_gem_retire_request(dev, request);
1050
1051                         list_del(&request->list);
1052                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1053                 } else
1054                         break;
1055         }
1056 }
1057
1058 void
1059 i915_gem_retire_work_handler(struct work_struct *work)
1060 {
1061         drm_i915_private_t *dev_priv;
1062         struct drm_device *dev;
1063
1064         dev_priv = container_of(work, drm_i915_private_t,
1065                                 mm.retire_work.work);
1066         dev = dev_priv->dev;
1067
1068         mutex_lock(&dev->struct_mutex);
1069         i915_gem_retire_requests(dev);
1070         if (!dev_priv->mm.suspended &&
1071             !list_empty(&dev_priv->mm.request_list))
1072                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1073         mutex_unlock(&dev->struct_mutex);
1074 }
1075
1076 /**
1077  * Waits for a sequence number to be signaled, and cleans up the
1078  * request and object lists appropriately for that event.
1079  */
1080 static int
1081 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1082 {
1083         drm_i915_private_t *dev_priv = dev->dev_private;
1084         int ret = 0;
1085
1086         BUG_ON(seqno == 0);
1087
1088         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1089                 dev_priv->mm.waiting_gem_seqno = seqno;
1090                 i915_user_irq_get(dev);
1091                 ret = wait_event_interruptible(dev_priv->irq_queue,
1092                                                i915_seqno_passed(i915_get_gem_seqno(dev),
1093                                                                  seqno) ||
1094                                                dev_priv->mm.wedged);
1095                 i915_user_irq_put(dev);
1096                 dev_priv->mm.waiting_gem_seqno = 0;
1097         }
1098         if (dev_priv->mm.wedged)
1099                 ret = -EIO;
1100
1101         if (ret && ret != -ERESTARTSYS)
1102                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1103                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1104
1105         /* Directly dispatch request retiring.  While we have the work queue
1106          * to handle this, the waiter on a request often wants an associated
1107          * buffer to have made it to the inactive list, and we would need
1108          * a separate wait queue to handle that.
1109          */
1110         if (ret == 0)
1111                 i915_gem_retire_requests(dev);
1112
1113         return ret;
1114 }
1115
1116 static void
1117 i915_gem_flush(struct drm_device *dev,
1118                uint32_t invalidate_domains,
1119                uint32_t flush_domains)
1120 {
1121         drm_i915_private_t *dev_priv = dev->dev_private;
1122         uint32_t cmd;
1123         RING_LOCALS;
1124
1125 #if WATCH_EXEC
1126         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1127                   invalidate_domains, flush_domains);
1128 #endif
1129
1130         if (flush_domains & I915_GEM_DOMAIN_CPU)
1131                 drm_agp_chipset_flush(dev);
1132
1133         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1134                                                      I915_GEM_DOMAIN_GTT)) {
1135                 /*
1136                  * read/write caches:
1137                  *
1138                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1139                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1140                  * also flushed at 2d versus 3d pipeline switches.
1141                  *
1142                  * read-only caches:
1143                  *
1144                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1145                  * MI_READ_FLUSH is set, and is always flushed on 965.
1146                  *
1147                  * I915_GEM_DOMAIN_COMMAND may not exist?
1148                  *
1149                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1150                  * invalidated when MI_EXE_FLUSH is set.
1151                  *
1152                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1153                  * invalidated with every MI_FLUSH.
1154                  *
1155                  * TLBs:
1156                  *
1157                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1158                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1159                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1160                  * are flushed at any MI_FLUSH.
1161                  */
1162
1163                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1164                 if ((invalidate_domains|flush_domains) &
1165                     I915_GEM_DOMAIN_RENDER)
1166                         cmd &= ~MI_NO_WRITE_FLUSH;
1167                 if (!IS_I965G(dev)) {
1168                         /*
1169                          * On the 965, the sampler cache always gets flushed
1170                          * and this bit is reserved.
1171                          */
1172                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1173                                 cmd |= MI_READ_FLUSH;
1174                 }
1175                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1176                         cmd |= MI_EXE_FLUSH;
1177
1178 #if WATCH_EXEC
1179                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1180 #endif
1181                 BEGIN_LP_RING(2);
1182                 OUT_RING(cmd);
1183                 OUT_RING(0); /* noop */
1184                 ADVANCE_LP_RING();
1185         }
1186 }
1187
1188 /**
1189  * Ensures that all rendering to the object has completed and the object is
1190  * safe to unbind from the GTT or access from the CPU.
1191  */
1192 static int
1193 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1194 {
1195         struct drm_device *dev = obj->dev;
1196         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197         int ret;
1198
1199         /* This function only exists to support waiting for existing rendering,
1200          * not for emitting required flushes.
1201          */
1202         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1203
1204         /* If there is rendering queued on the buffer being evicted, wait for
1205          * it.
1206          */
1207         if (obj_priv->active) {
1208 #if WATCH_BUF
1209                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1210                           __func__, obj, obj_priv->last_rendering_seqno);
1211 #endif
1212                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1213                 if (ret != 0)
1214                         return ret;
1215         }
1216
1217         return 0;
1218 }
1219
1220 /**
1221  * Unbinds an object from the GTT aperture.
1222  */
1223 int
1224 i915_gem_object_unbind(struct drm_gem_object *obj)
1225 {
1226         struct drm_device *dev = obj->dev;
1227         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1228         loff_t offset;
1229         int ret = 0;
1230
1231 #if WATCH_BUF
1232         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1233         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1234 #endif
1235         if (obj_priv->gtt_space == NULL)
1236                 return 0;
1237
1238         if (obj_priv->pin_count != 0) {
1239                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1240                 return -EINVAL;
1241         }
1242
1243         /* Move the object to the CPU domain to ensure that
1244          * any possible CPU writes while it's not in the GTT
1245          * are flushed when we go to remap it. This will
1246          * also ensure that all pending GPU writes are finished
1247          * before we unbind.
1248          */
1249         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1250         if (ret) {
1251                 if (ret != -ERESTARTSYS)
1252                         DRM_ERROR("set_domain failed: %d\n", ret);
1253                 return ret;
1254         }
1255
1256         if (obj_priv->agp_mem != NULL) {
1257                 drm_unbind_agp(obj_priv->agp_mem);
1258                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1259                 obj_priv->agp_mem = NULL;
1260         }
1261
1262         BUG_ON(obj_priv->active);
1263
1264         /* blow away mappings if mapped through GTT */
1265         offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1266         if (dev->dev_mapping)
1267                 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1268
1269         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1270                 i915_gem_clear_fence_reg(obj);
1271
1272         i915_gem_object_free_page_list(obj);
1273
1274         if (obj_priv->gtt_space) {
1275                 atomic_dec(&dev->gtt_count);
1276                 atomic_sub(obj->size, &dev->gtt_memory);
1277
1278                 drm_mm_put_block(obj_priv->gtt_space);
1279                 obj_priv->gtt_space = NULL;
1280         }
1281
1282         /* Remove ourselves from the LRU list if present. */
1283         if (!list_empty(&obj_priv->list))
1284                 list_del_init(&obj_priv->list);
1285
1286         return 0;
1287 }
1288
1289 static int
1290 i915_gem_evict_something(struct drm_device *dev)
1291 {
1292         drm_i915_private_t *dev_priv = dev->dev_private;
1293         struct drm_gem_object *obj;
1294         struct drm_i915_gem_object *obj_priv;
1295         int ret = 0;
1296
1297         for (;;) {
1298                 /* If there's an inactive buffer available now, grab it
1299                  * and be done.
1300                  */
1301                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1302                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1303                                                     struct drm_i915_gem_object,
1304                                                     list);
1305                         obj = obj_priv->obj;
1306                         BUG_ON(obj_priv->pin_count != 0);
1307 #if WATCH_LRU
1308                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1309 #endif
1310                         BUG_ON(obj_priv->active);
1311
1312                         /* Wait on the rendering and unbind the buffer. */
1313                         ret = i915_gem_object_unbind(obj);
1314                         break;
1315                 }
1316
1317                 /* If we didn't get anything, but the ring is still processing
1318                  * things, wait for one of those things to finish and hopefully
1319                  * leave us a buffer to evict.
1320                  */
1321                 if (!list_empty(&dev_priv->mm.request_list)) {
1322                         struct drm_i915_gem_request *request;
1323
1324                         request = list_first_entry(&dev_priv->mm.request_list,
1325                                                    struct drm_i915_gem_request,
1326                                                    list);
1327
1328                         ret = i915_wait_request(dev, request->seqno);
1329                         if (ret)
1330                                 break;
1331
1332                         /* if waiting caused an object to become inactive,
1333                          * then loop around and wait for it. Otherwise, we
1334                          * assume that waiting freed and unbound something,
1335                          * so there should now be some space in the GTT
1336                          */
1337                         if (!list_empty(&dev_priv->mm.inactive_list))
1338                                 continue;
1339                         break;
1340                 }
1341
1342                 /* If we didn't have anything on the request list but there
1343                  * are buffers awaiting a flush, emit one and try again.
1344                  * When we wait on it, those buffers waiting for that flush
1345                  * will get moved to inactive.
1346                  */
1347                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1348                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1349                                                     struct drm_i915_gem_object,
1350                                                     list);
1351                         obj = obj_priv->obj;
1352
1353                         i915_gem_flush(dev,
1354                                        obj->write_domain,
1355                                        obj->write_domain);
1356                         i915_add_request(dev, obj->write_domain);
1357
1358                         obj = NULL;
1359                         continue;
1360                 }
1361
1362                 DRM_ERROR("inactive empty %d request empty %d "
1363                           "flushing empty %d\n",
1364                           list_empty(&dev_priv->mm.inactive_list),
1365                           list_empty(&dev_priv->mm.request_list),
1366                           list_empty(&dev_priv->mm.flushing_list));
1367                 /* If we didn't do any of the above, there's nothing to be done
1368                  * and we just can't fit it in.
1369                  */
1370                 return -ENOMEM;
1371         }
1372         return ret;
1373 }
1374
1375 static int
1376 i915_gem_evict_everything(struct drm_device *dev)
1377 {
1378         int ret;
1379
1380         for (;;) {
1381                 ret = i915_gem_evict_something(dev);
1382                 if (ret != 0)
1383                         break;
1384         }
1385         if (ret == -ENOMEM)
1386                 return 0;
1387         return ret;
1388 }
1389
1390 static int
1391 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1392 {
1393         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1394         int page_count, i;
1395         struct address_space *mapping;
1396         struct inode *inode;
1397         struct page *page;
1398         int ret;
1399
1400         if (obj_priv->page_list)
1401                 return 0;
1402
1403         /* Get the list of pages out of our struct file.  They'll be pinned
1404          * at this point until we release them.
1405          */
1406         page_count = obj->size / PAGE_SIZE;
1407         BUG_ON(obj_priv->page_list != NULL);
1408         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1409                                          DRM_MEM_DRIVER);
1410         if (obj_priv->page_list == NULL) {
1411                 DRM_ERROR("Faled to allocate page list\n");
1412                 return -ENOMEM;
1413         }
1414
1415         inode = obj->filp->f_path.dentry->d_inode;
1416         mapping = inode->i_mapping;
1417         for (i = 0; i < page_count; i++) {
1418                 page = read_mapping_page(mapping, i, NULL);
1419                 if (IS_ERR(page)) {
1420                         ret = PTR_ERR(page);
1421                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1422                         i915_gem_object_free_page_list(obj);
1423                         return ret;
1424                 }
1425                 obj_priv->page_list[i] = page;
1426         }
1427         return 0;
1428 }
1429
1430 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1431 {
1432         struct drm_gem_object *obj = reg->obj;
1433         struct drm_device *dev = obj->dev;
1434         drm_i915_private_t *dev_priv = dev->dev_private;
1435         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1436         int regnum = obj_priv->fence_reg;
1437         uint64_t val;
1438
1439         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1440                     0xfffff000) << 32;
1441         val |= obj_priv->gtt_offset & 0xfffff000;
1442         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1443         if (obj_priv->tiling_mode == I915_TILING_Y)
1444                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1445         val |= I965_FENCE_REG_VALID;
1446
1447         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1448 }
1449
1450 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1451 {
1452         struct drm_gem_object *obj = reg->obj;
1453         struct drm_device *dev = obj->dev;
1454         drm_i915_private_t *dev_priv = dev->dev_private;
1455         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1456         int regnum = obj_priv->fence_reg;
1457         int tile_width;
1458         uint32_t val;
1459         uint32_t pitch_val;
1460
1461         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1462             (obj_priv->gtt_offset & (obj->size - 1))) {
1463                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1464                      __func__, obj_priv->gtt_offset, obj->size);
1465                 return;
1466         }
1467
1468         if (obj_priv->tiling_mode == I915_TILING_Y &&
1469             HAS_128_BYTE_Y_TILING(dev))
1470                 tile_width = 128;
1471         else
1472                 tile_width = 512;
1473
1474         /* Note: pitch better be a power of two tile widths */
1475         pitch_val = obj_priv->stride / tile_width;
1476         pitch_val = ffs(pitch_val) - 1;
1477
1478         val = obj_priv->gtt_offset;
1479         if (obj_priv->tiling_mode == I915_TILING_Y)
1480                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1481         val |= I915_FENCE_SIZE_BITS(obj->size);
1482         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1483         val |= I830_FENCE_REG_VALID;
1484
1485         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1486 }
1487
1488 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1489 {
1490         struct drm_gem_object *obj = reg->obj;
1491         struct drm_device *dev = obj->dev;
1492         drm_i915_private_t *dev_priv = dev->dev_private;
1493         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1494         int regnum = obj_priv->fence_reg;
1495         uint32_t val;
1496         uint32_t pitch_val;
1497
1498         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1499             (obj_priv->gtt_offset & (obj->size - 1))) {
1500                 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1501                      __func__, obj_priv->gtt_offset);
1502                 return;
1503         }
1504
1505         pitch_val = (obj_priv->stride / 128) - 1;
1506
1507         val = obj_priv->gtt_offset;
1508         if (obj_priv->tiling_mode == I915_TILING_Y)
1509                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1510         val |= I830_FENCE_SIZE_BITS(obj->size);
1511         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1512         val |= I830_FENCE_REG_VALID;
1513
1514         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1515
1516 }
1517
1518 /**
1519  * i915_gem_object_get_fence_reg - set up a fence reg for an object
1520  * @obj: object to map through a fence reg
1521  * @write: object is about to be written
1522  *
1523  * When mapping objects through the GTT, userspace wants to be able to write
1524  * to them without having to worry about swizzling if the object is tiled.
1525  *
1526  * This function walks the fence regs looking for a free one for @obj,
1527  * stealing one if it can't find any.
1528  *
1529  * It then sets up the reg based on the object's properties: address, pitch
1530  * and tiling format.
1531  */
1532 static int
1533 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
1534 {
1535         struct drm_device *dev = obj->dev;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1538         struct drm_i915_fence_reg *reg = NULL;
1539         int i, ret;
1540
1541         switch (obj_priv->tiling_mode) {
1542         case I915_TILING_NONE:
1543                 WARN(1, "allocating a fence for non-tiled object?\n");
1544                 break;
1545         case I915_TILING_X:
1546                 if (!obj_priv->stride)
1547                         return -EINVAL;
1548                 WARN((obj_priv->stride & (512 - 1)),
1549                      "object 0x%08x is X tiled but has non-512B pitch\n",
1550                      obj_priv->gtt_offset);
1551                 break;
1552         case I915_TILING_Y:
1553                 if (!obj_priv->stride)
1554                         return -EINVAL;
1555                 WARN((obj_priv->stride & (128 - 1)),
1556                      "object 0x%08x is Y tiled but has non-128B pitch\n",
1557                      obj_priv->gtt_offset);
1558                 break;
1559         }
1560
1561         /* First try to find a free reg */
1562         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1563                 reg = &dev_priv->fence_regs[i];
1564                 if (!reg->obj)
1565                         break;
1566         }
1567
1568         /* None available, try to steal one or wait for a user to finish */
1569         if (i == dev_priv->num_fence_regs) {
1570                 struct drm_i915_gem_object *old_obj_priv = NULL;
1571                 loff_t offset;
1572
1573 try_again:
1574                 /* Could try to use LRU here instead... */
1575                 for (i = dev_priv->fence_reg_start;
1576                      i < dev_priv->num_fence_regs; i++) {
1577                         reg = &dev_priv->fence_regs[i];
1578                         old_obj_priv = reg->obj->driver_private;
1579                         if (!old_obj_priv->pin_count)
1580                                 break;
1581                 }
1582
1583                 /*
1584                  * Now things get ugly... we have to wait for one of the
1585                  * objects to finish before trying again.
1586                  */
1587                 if (i == dev_priv->num_fence_regs) {
1588                         ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
1589                         if (ret) {
1590                                 WARN(ret != -ERESTARTSYS,
1591                                      "switch to GTT domain failed: %d\n", ret);
1592                                 return ret;
1593                         }
1594                         goto try_again;
1595                 }
1596
1597                 /*
1598                  * Zap this virtual mapping so we can set up a fence again
1599                  * for this object next time we need it.
1600                  */
1601                 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
1602                 if (dev->dev_mapping)
1603                         unmap_mapping_range(dev->dev_mapping, offset,
1604                                             reg->obj->size, 1);
1605                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1606         }
1607
1608         obj_priv->fence_reg = i;
1609         reg->obj = obj;
1610
1611         if (IS_I965G(dev))
1612                 i965_write_fence_reg(reg);
1613         else if (IS_I9XX(dev))
1614                 i915_write_fence_reg(reg);
1615         else
1616                 i830_write_fence_reg(reg);
1617
1618         return 0;
1619 }
1620
1621 /**
1622  * i915_gem_clear_fence_reg - clear out fence register info
1623  * @obj: object to clear
1624  *
1625  * Zeroes out the fence register itself and clears out the associated
1626  * data structures in dev_priv and obj_priv.
1627  */
1628 static void
1629 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1630 {
1631         struct drm_device *dev = obj->dev;
1632         drm_i915_private_t *dev_priv = dev->dev_private;
1633         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1634
1635         if (IS_I965G(dev))
1636                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1637         else
1638                 I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
1639
1640         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1641         obj_priv->fence_reg = I915_FENCE_REG_NONE;
1642 }
1643
1644 /**
1645  * Finds free space in the GTT aperture and binds the object there.
1646  */
1647 static int
1648 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1649 {
1650         struct drm_device *dev = obj->dev;
1651         drm_i915_private_t *dev_priv = dev->dev_private;
1652         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1653         struct drm_mm_node *free_space;
1654         int page_count, ret;
1655
1656         if (dev_priv->mm.suspended)
1657                 return -EBUSY;
1658         if (alignment == 0)
1659                 alignment = i915_gem_get_gtt_alignment(obj);
1660         if (alignment & (PAGE_SIZE - 1)) {
1661                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1662                 return -EINVAL;
1663         }
1664
1665  search_free:
1666         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1667                                         obj->size, alignment, 0);
1668         if (free_space != NULL) {
1669                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1670                                                        alignment);
1671                 if (obj_priv->gtt_space != NULL) {
1672                         obj_priv->gtt_space->private = obj;
1673                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1674                 }
1675         }
1676         if (obj_priv->gtt_space == NULL) {
1677                 /* If the gtt is empty and we're still having trouble
1678                  * fitting our object in, we're out of memory.
1679                  */
1680 #if WATCH_LRU
1681                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1682 #endif
1683                 if (list_empty(&dev_priv->mm.inactive_list) &&
1684                     list_empty(&dev_priv->mm.flushing_list) &&
1685                     list_empty(&dev_priv->mm.active_list)) {
1686                         DRM_ERROR("GTT full, but LRU list empty\n");
1687                         return -ENOMEM;
1688                 }
1689
1690                 ret = i915_gem_evict_something(dev);
1691                 if (ret != 0) {
1692                         if (ret != -ERESTARTSYS)
1693                                 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1694                         return ret;
1695                 }
1696                 goto search_free;
1697         }
1698
1699 #if WATCH_BUF
1700         DRM_INFO("Binding object of size %d at 0x%08x\n",
1701                  obj->size, obj_priv->gtt_offset);
1702 #endif
1703         ret = i915_gem_object_get_page_list(obj);
1704         if (ret) {
1705                 drm_mm_put_block(obj_priv->gtt_space);
1706                 obj_priv->gtt_space = NULL;
1707                 return ret;
1708         }
1709
1710         page_count = obj->size / PAGE_SIZE;
1711         /* Create an AGP memory structure pointing at our pages, and bind it
1712          * into the GTT.
1713          */
1714         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1715                                                obj_priv->page_list,
1716                                                page_count,
1717                                                obj_priv->gtt_offset,
1718                                                obj_priv->agp_type);
1719         if (obj_priv->agp_mem == NULL) {
1720                 i915_gem_object_free_page_list(obj);
1721                 drm_mm_put_block(obj_priv->gtt_space);
1722                 obj_priv->gtt_space = NULL;
1723                 return -ENOMEM;
1724         }
1725         atomic_inc(&dev->gtt_count);
1726         atomic_add(obj->size, &dev->gtt_memory);
1727
1728         /* Assert that the object is not currently in any GPU domain. As it
1729          * wasn't in the GTT, there shouldn't be any way it could have been in
1730          * a GPU cache
1731          */
1732         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1733         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1734
1735         return 0;
1736 }
1737
1738 void
1739 i915_gem_clflush_object(struct drm_gem_object *obj)
1740 {
1741         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1742
1743         /* If we don't have a page list set up, then we're not pinned
1744          * to GPU, and we can ignore the cache flush because it'll happen
1745          * again at bind time.
1746          */
1747         if (obj_priv->page_list == NULL)
1748                 return;
1749
1750         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1751 }
1752
1753 /** Flushes any GPU write domain for the object if it's dirty. */
1754 static void
1755 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1756 {
1757         struct drm_device *dev = obj->dev;
1758         uint32_t seqno;
1759
1760         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1761                 return;
1762
1763         /* Queue the GPU write cache flushing we need. */
1764         i915_gem_flush(dev, 0, obj->write_domain);
1765         seqno = i915_add_request(dev, obj->write_domain);
1766         obj->write_domain = 0;
1767         i915_gem_object_move_to_active(obj, seqno);
1768 }
1769
1770 /** Flushes the GTT write domain for the object if it's dirty. */
1771 static void
1772 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1773 {
1774         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1775                 return;
1776
1777         /* No actual flushing is required for the GTT write domain.   Writes
1778          * to it immediately go to main memory as far as we know, so there's
1779          * no chipset flush.  It also doesn't land in render cache.
1780          */
1781         obj->write_domain = 0;
1782 }
1783
1784 /** Flushes the CPU write domain for the object if it's dirty. */
1785 static void
1786 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1787 {
1788         struct drm_device *dev = obj->dev;
1789
1790         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1791                 return;
1792
1793         i915_gem_clflush_object(obj);
1794         drm_agp_chipset_flush(dev);
1795         obj->write_domain = 0;
1796 }
1797
1798 /**
1799  * Moves a single object to the GTT read, and possibly write domain.
1800  *
1801  * This function returns when the move is complete, including waiting on
1802  * flushes to occur.
1803  */
1804 int
1805 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1806 {
1807         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1808         int ret;
1809
1810         /* Not valid to be called on unbound objects. */
1811         if (obj_priv->gtt_space == NULL)
1812                 return -EINVAL;
1813
1814         i915_gem_object_flush_gpu_write_domain(obj);
1815         /* Wait on any GPU rendering and flushing to occur. */
1816         ret = i915_gem_object_wait_rendering(obj);
1817         if (ret != 0)
1818                 return ret;
1819
1820         /* If we're writing through the GTT domain, then CPU and GPU caches
1821          * will need to be invalidated at next use.
1822          */
1823         if (write)
1824                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1825
1826         i915_gem_object_flush_cpu_write_domain(obj);
1827
1828         /* It should now be out of any other write domains, and we can update
1829          * the domain values for our changes.
1830          */
1831         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1832         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1833         if (write) {
1834                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1835                 obj_priv->dirty = 1;
1836         }
1837
1838         return 0;
1839 }
1840
1841 /**
1842  * Moves a single object to the CPU read, and possibly write domain.
1843  *
1844  * This function returns when the move is complete, including waiting on
1845  * flushes to occur.
1846  */
1847 static int
1848 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1849 {
1850         struct drm_device *dev = obj->dev;
1851         int ret;
1852
1853         i915_gem_object_flush_gpu_write_domain(obj);
1854         /* Wait on any GPU rendering and flushing to occur. */
1855         ret = i915_gem_object_wait_rendering(obj);
1856         if (ret != 0)
1857                 return ret;
1858
1859         i915_gem_object_flush_gtt_write_domain(obj);
1860
1861         /* If we have a partially-valid cache of the object in the CPU,
1862          * finish invalidating it and free the per-page flags.
1863          */
1864         i915_gem_object_set_to_full_cpu_read_domain(obj);
1865
1866         /* Flush the CPU cache if it's still invalid. */
1867         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1868                 i915_gem_clflush_object(obj);
1869                 drm_agp_chipset_flush(dev);
1870
1871                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1872         }
1873
1874         /* It should now be out of any other write domains, and we can update
1875          * the domain values for our changes.
1876          */
1877         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1878
1879         /* If we're writing through the CPU, then the GPU read domains will
1880          * need to be invalidated at next use.
1881          */
1882         if (write) {
1883                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1884                 obj->write_domain = I915_GEM_DOMAIN_CPU;
1885         }
1886
1887         return 0;
1888 }
1889
1890 /*
1891  * Set the next domain for the specified object. This
1892  * may not actually perform the necessary flushing/invaliding though,
1893  * as that may want to be batched with other set_domain operations
1894  *
1895  * This is (we hope) the only really tricky part of gem. The goal
1896  * is fairly simple -- track which caches hold bits of the object
1897  * and make sure they remain coherent. A few concrete examples may
1898  * help to explain how it works. For shorthand, we use the notation
1899  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1900  * a pair of read and write domain masks.
1901  *
1902  * Case 1: the batch buffer
1903  *
1904  *      1. Allocated
1905  *      2. Written by CPU
1906  *      3. Mapped to GTT
1907  *      4. Read by GPU
1908  *      5. Unmapped from GTT
1909  *      6. Freed
1910  *
1911  *      Let's take these a step at a time
1912  *
1913  *      1. Allocated
1914  *              Pages allocated from the kernel may still have
1915  *              cache contents, so we set them to (CPU, CPU) always.
1916  *      2. Written by CPU (using pwrite)
1917  *              The pwrite function calls set_domain (CPU, CPU) and
1918  *              this function does nothing (as nothing changes)
1919  *      3. Mapped by GTT
1920  *              This function asserts that the object is not
1921  *              currently in any GPU-based read or write domains
1922  *      4. Read by GPU
1923  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1924  *              As write_domain is zero, this function adds in the
1925  *              current read domains (CPU+COMMAND, 0).
1926  *              flush_domains is set to CPU.
1927  *              invalidate_domains is set to COMMAND
1928  *              clflush is run to get data out of the CPU caches
1929  *              then i915_dev_set_domain calls i915_gem_flush to
1930  *              emit an MI_FLUSH and drm_agp_chipset_flush
1931  *      5. Unmapped from GTT
1932  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1933  *              flush_domains and invalidate_domains end up both zero
1934  *              so no flushing/invalidating happens
1935  *      6. Freed
1936  *              yay, done
1937  *
1938  * Case 2: The shared render buffer
1939  *
1940  *      1. Allocated
1941  *      2. Mapped to GTT
1942  *      3. Read/written by GPU
1943  *      4. set_domain to (CPU,CPU)
1944  *      5. Read/written by CPU
1945  *      6. Read/written by GPU
1946  *
1947  *      1. Allocated
1948  *              Same as last example, (CPU, CPU)
1949  *      2. Mapped to GTT
1950  *              Nothing changes (assertions find that it is not in the GPU)
1951  *      3. Read/written by GPU
1952  *              execbuffer calls set_domain (RENDER, RENDER)
1953  *              flush_domains gets CPU
1954  *              invalidate_domains gets GPU
1955  *              clflush (obj)
1956  *              MI_FLUSH and drm_agp_chipset_flush
1957  *      4. set_domain (CPU, CPU)
1958  *              flush_domains gets GPU
1959  *              invalidate_domains gets CPU
1960  *              wait_rendering (obj) to make sure all drawing is complete.
1961  *              This will include an MI_FLUSH to get the data from GPU
1962  *              to memory
1963  *              clflush (obj) to invalidate the CPU cache
1964  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1965  *      5. Read/written by CPU
1966  *              cache lines are loaded and dirtied
1967  *      6. Read written by GPU
1968  *              Same as last GPU access
1969  *
1970  * Case 3: The constant buffer
1971  *
1972  *      1. Allocated
1973  *      2. Written by CPU
1974  *      3. Read by GPU
1975  *      4. Updated (written) by CPU again
1976  *      5. Read by GPU
1977  *
1978  *      1. Allocated
1979  *              (CPU, CPU)
1980  *      2. Written by CPU
1981  *              (CPU, CPU)
1982  *      3. Read by GPU
1983  *              (CPU+RENDER, 0)
1984  *              flush_domains = CPU
1985  *              invalidate_domains = RENDER
1986  *              clflush (obj)
1987  *              MI_FLUSH
1988  *              drm_agp_chipset_flush
1989  *      4. Updated (written) by CPU again
1990  *              (CPU, CPU)
1991  *              flush_domains = 0 (no previous write domain)
1992  *              invalidate_domains = 0 (no new read domains)
1993  *      5. Read by GPU
1994  *              (CPU+RENDER, 0)
1995  *              flush_domains = CPU
1996  *              invalidate_domains = RENDER
1997  *              clflush (obj)
1998  *              MI_FLUSH
1999  *              drm_agp_chipset_flush
2000  */
2001 static void
2002 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
2003                                   uint32_t read_domains,
2004                                   uint32_t write_domain)
2005 {
2006         struct drm_device               *dev = obj->dev;
2007         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2008         uint32_t                        invalidate_domains = 0;
2009         uint32_t                        flush_domains = 0;
2010
2011         BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
2012         BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
2013
2014 #if WATCH_BUF
2015         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2016                  __func__, obj,
2017                  obj->read_domains, read_domains,
2018                  obj->write_domain, write_domain);
2019 #endif
2020         /*
2021          * If the object isn't moving to a new write domain,
2022          * let the object stay in multiple read domains
2023          */
2024         if (write_domain == 0)
2025                 read_domains |= obj->read_domains;
2026         else
2027                 obj_priv->dirty = 1;
2028
2029         /*
2030          * Flush the current write domain if
2031          * the new read domains don't match. Invalidate
2032          * any read domains which differ from the old
2033          * write domain
2034          */
2035         if (obj->write_domain && obj->write_domain != read_domains) {
2036                 flush_domains |= obj->write_domain;
2037                 invalidate_domains |= read_domains & ~obj->write_domain;
2038         }
2039         /*
2040          * Invalidate any read caches which may have
2041          * stale data. That is, any new read domains.
2042          */
2043         invalidate_domains |= read_domains & ~obj->read_domains;
2044         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2045 #if WATCH_BUF
2046                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2047                          __func__, flush_domains, invalidate_domains);
2048 #endif
2049                 i915_gem_clflush_object(obj);
2050         }
2051
2052         if ((write_domain | flush_domains) != 0)
2053                 obj->write_domain = write_domain;
2054         obj->read_domains = read_domains;
2055
2056         dev->invalidate_domains |= invalidate_domains;
2057         dev->flush_domains |= flush_domains;
2058 #if WATCH_BUF
2059         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2060                  __func__,
2061                  obj->read_domains, obj->write_domain,
2062                  dev->invalidate_domains, dev->flush_domains);
2063 #endif
2064 }
2065
2066 /**
2067  * Moves the object from a partially CPU read to a full one.
2068  *
2069  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2070  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2071  */
2072 static void
2073 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2074 {
2075         struct drm_device *dev = obj->dev;
2076         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2077
2078         if (!obj_priv->page_cpu_valid)
2079                 return;
2080
2081         /* If we're partially in the CPU read domain, finish moving it in.
2082          */
2083         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2084                 int i;
2085
2086                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2087                         if (obj_priv->page_cpu_valid[i])
2088                                 continue;
2089                         drm_clflush_pages(obj_priv->page_list + i, 1);
2090                 }
2091                 drm_agp_chipset_flush(dev);
2092         }
2093
2094         /* Free the page_cpu_valid mappings which are now stale, whether
2095          * or not we've got I915_GEM_DOMAIN_CPU.
2096          */
2097         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2098                  DRM_MEM_DRIVER);
2099         obj_priv->page_cpu_valid = NULL;
2100 }
2101
2102 /**
2103  * Set the CPU read domain on a range of the object.
2104  *
2105  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2106  * not entirely valid.  The page_cpu_valid member of the object flags which
2107  * pages have been flushed, and will be respected by
2108  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2109  * of the whole object.
2110  *
2111  * This function returns when the move is complete, including waiting on
2112  * flushes to occur.
2113  */
2114 static int
2115 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2116                                           uint64_t offset, uint64_t size)
2117 {
2118         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2119         int i, ret;
2120
2121         if (offset == 0 && size == obj->size)
2122                 return i915_gem_object_set_to_cpu_domain(obj, 0);
2123
2124         i915_gem_object_flush_gpu_write_domain(obj);
2125         /* Wait on any GPU rendering and flushing to occur. */
2126         ret = i915_gem_object_wait_rendering(obj);
2127         if (ret != 0)
2128                 return ret;
2129         i915_gem_object_flush_gtt_write_domain(obj);
2130
2131         /* If we're already fully in the CPU read domain, we're done. */
2132         if (obj_priv->page_cpu_valid == NULL &&
2133             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2134                 return 0;
2135
2136         /* Otherwise, create/clear the per-page CPU read domain flag if we're
2137          * newly adding I915_GEM_DOMAIN_CPU
2138          */
2139         if (obj_priv->page_cpu_valid == NULL) {
2140                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2141                                                       DRM_MEM_DRIVER);
2142                 if (obj_priv->page_cpu_valid == NULL)
2143                         return -ENOMEM;
2144         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2145                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2146
2147         /* Flush the cache on any pages that are still invalid from the CPU's
2148          * perspective.
2149          */
2150         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2151              i++) {
2152                 if (obj_priv->page_cpu_valid[i])
2153                         continue;
2154
2155                 drm_clflush_pages(obj_priv->page_list + i, 1);
2156
2157                 obj_priv->page_cpu_valid[i] = 1;
2158         }
2159
2160         /* It should now be out of any other write domains, and we can update
2161          * the domain values for our changes.
2162          */
2163         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2164
2165         obj->read_domains |= I915_GEM_DOMAIN_CPU;
2166
2167         return 0;
2168 }
2169
2170 /**
2171  * Pin an object to the GTT and evaluate the relocations landing in it.
2172  */
2173 static int
2174 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2175                                  struct drm_file *file_priv,
2176                                  struct drm_i915_gem_exec_object *entry)
2177 {
2178         struct drm_device *dev = obj->dev;
2179         drm_i915_private_t *dev_priv = dev->dev_private;
2180         struct drm_i915_gem_relocation_entry reloc;
2181         struct drm_i915_gem_relocation_entry __user *relocs;
2182         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2183         int i, ret;
2184         void __iomem *reloc_page;
2185
2186         /* Choose the GTT offset for our buffer and put it there. */
2187         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2188         if (ret)
2189                 return ret;
2190
2191         entry->offset = obj_priv->gtt_offset;
2192
2193         relocs = (struct drm_i915_gem_relocation_entry __user *)
2194                  (uintptr_t) entry->relocs_ptr;
2195         /* Apply the relocations, using the GTT aperture to avoid cache
2196          * flushing requirements.
2197          */
2198         for (i = 0; i < entry->relocation_count; i++) {
2199                 struct drm_gem_object *target_obj;
2200                 struct drm_i915_gem_object *target_obj_priv;
2201                 uint32_t reloc_val, reloc_offset;
2202                 uint32_t __iomem *reloc_entry;
2203
2204                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2205                 if (ret != 0) {
2206                         i915_gem_object_unpin(obj);
2207                         return ret;
2208                 }
2209
2210                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2211                                                    reloc.target_handle);
2212                 if (target_obj == NULL) {
2213                         i915_gem_object_unpin(obj);
2214                         return -EBADF;
2215                 }
2216                 target_obj_priv = target_obj->driver_private;
2217
2218                 /* The target buffer should have appeared before us in the
2219                  * exec_object list, so it should have a GTT space bound by now.
2220                  */
2221                 if (target_obj_priv->gtt_space == NULL) {
2222                         DRM_ERROR("No GTT space found for object %d\n",
2223                                   reloc.target_handle);
2224                         drm_gem_object_unreference(target_obj);
2225                         i915_gem_object_unpin(obj);
2226                         return -EINVAL;
2227                 }
2228
2229                 if (reloc.offset > obj->size - 4) {
2230                         DRM_ERROR("Relocation beyond object bounds: "
2231                                   "obj %p target %d offset %d size %d.\n",
2232                                   obj, reloc.target_handle,
2233                                   (int) reloc.offset, (int) obj->size);
2234                         drm_gem_object_unreference(target_obj);
2235                         i915_gem_object_unpin(obj);
2236                         return -EINVAL;
2237                 }
2238                 if (reloc.offset & 3) {
2239                         DRM_ERROR("Relocation not 4-byte aligned: "
2240                                   "obj %p target %d offset %d.\n",
2241                                   obj, reloc.target_handle,
2242                                   (int) reloc.offset);
2243                         drm_gem_object_unreference(target_obj);
2244                         i915_gem_object_unpin(obj);
2245                         return -EINVAL;
2246                 }
2247
2248                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2249                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2250                         DRM_ERROR("reloc with read/write CPU domains: "
2251                                   "obj %p target %d offset %d "
2252                                   "read %08x write %08x",
2253                                   obj, reloc.target_handle,
2254                                   (int) reloc.offset,
2255                                   reloc.read_domains,
2256                                   reloc.write_domain);
2257                         drm_gem_object_unreference(target_obj);
2258                         i915_gem_object_unpin(obj);
2259                         return -EINVAL;
2260                 }
2261
2262                 if (reloc.write_domain && target_obj->pending_write_domain &&
2263                     reloc.write_domain != target_obj->pending_write_domain) {
2264                         DRM_ERROR("Write domain conflict: "
2265                                   "obj %p target %d offset %d "
2266                                   "new %08x old %08x\n",
2267                                   obj, reloc.target_handle,
2268                                   (int) reloc.offset,
2269                                   reloc.write_domain,
2270                                   target_obj->pending_write_domain);
2271                         drm_gem_object_unreference(target_obj);
2272                         i915_gem_object_unpin(obj);
2273                         return -EINVAL;
2274                 }
2275
2276 #if WATCH_RELOC
2277                 DRM_INFO("%s: obj %p offset %08x target %d "
2278                          "read %08x write %08x gtt %08x "
2279                          "presumed %08x delta %08x\n",
2280                          __func__,
2281                          obj,
2282                          (int) reloc.offset,
2283                          (int) reloc.target_handle,
2284                          (int) reloc.read_domains,
2285                          (int) reloc.write_domain,
2286                          (int) target_obj_priv->gtt_offset,
2287                          (int) reloc.presumed_offset,
2288                          reloc.delta);
2289 #endif
2290
2291                 target_obj->pending_read_domains |= reloc.read_domains;
2292                 target_obj->pending_write_domain |= reloc.write_domain;
2293
2294                 /* If the relocation already has the right value in it, no
2295                  * more work needs to be done.
2296                  */
2297                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2298                         drm_gem_object_unreference(target_obj);
2299                         continue;
2300                 }
2301
2302                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2303                 if (ret != 0) {
2304                         drm_gem_object_unreference(target_obj);
2305                         i915_gem_object_unpin(obj);
2306                         return -EINVAL;
2307                 }
2308
2309                 /* Map the page containing the relocation we're going to
2310                  * perform.
2311                  */
2312                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
2313                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2314                                                       (reloc_offset &
2315                                                        ~(PAGE_SIZE - 1)));
2316                 reloc_entry = (uint32_t __iomem *)(reloc_page +
2317                                                    (reloc_offset & (PAGE_SIZE - 1)));
2318                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2319
2320 #if WATCH_BUF
2321                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2322                           obj, (unsigned int) reloc.offset,
2323                           readl(reloc_entry), reloc_val);
2324 #endif
2325                 writel(reloc_val, reloc_entry);
2326                 io_mapping_unmap_atomic(reloc_page);
2327
2328                 /* Write the updated presumed offset for this entry back out
2329                  * to the user.
2330                  */
2331                 reloc.presumed_offset = target_obj_priv->gtt_offset;
2332                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2333                 if (ret != 0) {
2334                         drm_gem_object_unreference(target_obj);
2335                         i915_gem_object_unpin(obj);
2336                         return ret;
2337                 }
2338
2339                 drm_gem_object_unreference(target_obj);
2340         }
2341
2342 #if WATCH_BUF
2343         if (0)
2344                 i915_gem_dump_object(obj, 128, __func__, ~0);
2345 #endif
2346         return 0;
2347 }
2348
2349 /** Dispatch a batchbuffer to the ring
2350  */
2351 static int
2352 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2353                               struct drm_i915_gem_execbuffer *exec,
2354                               uint64_t exec_offset)
2355 {
2356         drm_i915_private_t *dev_priv = dev->dev_private;
2357         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2358                                              (uintptr_t) exec->cliprects_ptr;
2359         int nbox = exec->num_cliprects;
2360         int i = 0, count;
2361         uint32_t        exec_start, exec_len;
2362         RING_LOCALS;
2363
2364         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2365         exec_len = (uint32_t) exec->batch_len;
2366
2367         if ((exec_start | exec_len) & 0x7) {
2368                 DRM_ERROR("alignment\n");
2369                 return -EINVAL;
2370         }
2371
2372         if (!exec_start)
2373                 return -EINVAL;
2374
2375         count = nbox ? nbox : 1;
2376
2377         for (i = 0; i < count; i++) {
2378                 if (i < nbox) {
2379                         int ret = i915_emit_box(dev, boxes, i,
2380                                                 exec->DR1, exec->DR4);
2381                         if (ret)
2382                                 return ret;
2383                 }
2384
2385                 if (IS_I830(dev) || IS_845G(dev)) {
2386                         BEGIN_LP_RING(4);
2387                         OUT_RING(MI_BATCH_BUFFER);
2388                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2389                         OUT_RING(exec_start + exec_len - 4);
2390                         OUT_RING(0);
2391                         ADVANCE_LP_RING();
2392                 } else {
2393                         BEGIN_LP_RING(2);
2394                         if (IS_I965G(dev)) {
2395                                 OUT_RING(MI_BATCH_BUFFER_START |
2396                                          (2 << 6) |
2397                                          MI_BATCH_NON_SECURE_I965);
2398                                 OUT_RING(exec_start);
2399                         } else {
2400                                 OUT_RING(MI_BATCH_BUFFER_START |
2401                                          (2 << 6));
2402                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2403                         }
2404                         ADVANCE_LP_RING();
2405                 }
2406         }
2407
2408         /* XXX breadcrumb */
2409         return 0;
2410 }
2411
2412 /* Throttle our rendering by waiting until the ring has completed our requests
2413  * emitted over 20 msec ago.
2414  *
2415  * This should get us reasonable parallelism between CPU and GPU but also
2416  * relatively low latency when blocking on a particular request to finish.
2417  */
2418 static int
2419 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2420 {
2421         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2422         int ret = 0;
2423         uint32_t seqno;
2424
2425         mutex_lock(&dev->struct_mutex);
2426         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2427         i915_file_priv->mm.last_gem_throttle_seqno =
2428                 i915_file_priv->mm.last_gem_seqno;
2429         if (seqno)
2430                 ret = i915_wait_request(dev, seqno);
2431         mutex_unlock(&dev->struct_mutex);
2432         return ret;
2433 }
2434
2435 int
2436 i915_gem_execbuffer(struct drm_device *dev, void *data,
2437                     struct drm_file *file_priv)
2438 {
2439         drm_i915_private_t *dev_priv = dev->dev_private;
2440         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2441         struct drm_i915_gem_execbuffer *args = data;
2442         struct drm_i915_gem_exec_object *exec_list = NULL;
2443         struct drm_gem_object **object_list = NULL;
2444         struct drm_gem_object *batch_obj;
2445         int ret, i, pinned = 0;
2446         uint64_t exec_offset;
2447         uint32_t seqno, flush_domains;
2448         int pin_tries;
2449
2450 #if WATCH_EXEC
2451         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2452                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2453 #endif
2454
2455         if (args->buffer_count < 1) {
2456                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2457                 return -EINVAL;
2458         }
2459         /* Copy in the exec list from userland */
2460         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2461                                DRM_MEM_DRIVER);
2462         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2463                                  DRM_MEM_DRIVER);
2464         if (exec_list == NULL || object_list == NULL) {
2465                 DRM_ERROR("Failed to allocate exec or object list "
2466                           "for %d buffers\n",
2467                           args->buffer_count);
2468                 ret = -ENOMEM;
2469                 goto pre_mutex_err;
2470         }
2471         ret = copy_from_user(exec_list,
2472                              (struct drm_i915_relocation_entry __user *)
2473                              (uintptr_t) args->buffers_ptr,
2474                              sizeof(*exec_list) * args->buffer_count);
2475         if (ret != 0) {
2476                 DRM_ERROR("copy %d exec entries failed %d\n",
2477                           args->buffer_count, ret);
2478                 goto pre_mutex_err;
2479         }
2480
2481         mutex_lock(&dev->struct_mutex);
2482
2483         i915_verify_inactive(dev, __FILE__, __LINE__);
2484
2485         if (dev_priv->mm.wedged) {
2486                 DRM_ERROR("Execbuf while wedged\n");
2487                 mutex_unlock(&dev->struct_mutex);
2488                 ret = -EIO;
2489                 goto pre_mutex_err;
2490         }
2491
2492         if (dev_priv->mm.suspended) {
2493                 DRM_ERROR("Execbuf while VT-switched.\n");
2494                 mutex_unlock(&dev->struct_mutex);
2495                 ret = -EBUSY;
2496                 goto pre_mutex_err;
2497         }
2498
2499         /* Look up object handles */
2500         for (i = 0; i < args->buffer_count; i++) {
2501                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2502                                                        exec_list[i].handle);
2503                 if (object_list[i] == NULL) {
2504                         DRM_ERROR("Invalid object handle %d at index %d\n",
2505                                    exec_list[i].handle, i);
2506                         ret = -EBADF;
2507                         goto err;
2508                 }
2509         }
2510
2511         /* Pin and relocate */
2512         for (pin_tries = 0; ; pin_tries++) {
2513                 ret = 0;
2514                 for (i = 0; i < args->buffer_count; i++) {
2515                         object_list[i]->pending_read_domains = 0;
2516                         object_list[i]->pending_write_domain = 0;
2517                         ret = i915_gem_object_pin_and_relocate(object_list[i],
2518                                                                file_priv,
2519                                                                &exec_list[i]);
2520                         if (ret)
2521                                 break;
2522                         pinned = i + 1;
2523                 }
2524                 /* success */
2525                 if (ret == 0)
2526                         break;
2527
2528                 /* error other than GTT full, or we've already tried again */
2529                 if (ret != -ENOMEM || pin_tries >= 1) {
2530                         if (ret != -ERESTARTSYS)
2531                                 DRM_ERROR("Failed to pin buffers %d\n", ret);
2532                         goto err;
2533                 }
2534
2535                 /* unpin all of our buffers */
2536                 for (i = 0; i < pinned; i++)
2537                         i915_gem_object_unpin(object_list[i]);
2538                 pinned = 0;
2539
2540                 /* evict everyone we can from the aperture */
2541                 ret = i915_gem_evict_everything(dev);
2542                 if (ret)
2543                         goto err;
2544         }
2545
2546         /* Set the pending read domains for the batch buffer to COMMAND */
2547         batch_obj = object_list[args->buffer_count-1];
2548         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2549         batch_obj->pending_write_domain = 0;
2550
2551         i915_verify_inactive(dev, __FILE__, __LINE__);
2552
2553         /* Zero the global flush/invalidate flags. These
2554          * will be modified as new domains are computed
2555          * for each object
2556          */
2557         dev->invalidate_domains = 0;
2558         dev->flush_domains = 0;
2559
2560         for (i = 0; i < args->buffer_count; i++) {
2561                 struct drm_gem_object *obj = object_list[i];
2562
2563                 /* Compute new gpu domains and update invalidate/flush */
2564                 i915_gem_object_set_to_gpu_domain(obj,
2565                                                   obj->pending_read_domains,
2566                                                   obj->pending_write_domain);
2567         }
2568
2569         i915_verify_inactive(dev, __FILE__, __LINE__);
2570
2571         if (dev->invalidate_domains | dev->flush_domains) {
2572 #if WATCH_EXEC
2573                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2574                           __func__,
2575                          dev->invalidate_domains,
2576                          dev->flush_domains);
2577 #endif
2578                 i915_gem_flush(dev,
2579                                dev->invalidate_domains,
2580                                dev->flush_domains);
2581                 if (dev->flush_domains)
2582                         (void)i915_add_request(dev, dev->flush_domains);
2583         }
2584
2585         i915_verify_inactive(dev, __FILE__, __LINE__);
2586
2587 #if WATCH_COHERENCY
2588         for (i = 0; i < args->buffer_count; i++) {
2589                 i915_gem_object_check_coherency(object_list[i],
2590                                                 exec_list[i].handle);
2591         }
2592 #endif
2593
2594         exec_offset = exec_list[args->buffer_count - 1].offset;
2595
2596 #if WATCH_EXEC
2597         i915_gem_dump_object(object_list[args->buffer_count - 1],
2598                               args->batch_len,
2599                               __func__,
2600                               ~0);
2601 #endif
2602
2603         /* Exec the batchbuffer */
2604         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2605         if (ret) {
2606                 DRM_ERROR("dispatch failed %d\n", ret);
2607                 goto err;
2608         }
2609
2610         /*
2611          * Ensure that the commands in the batch buffer are
2612          * finished before the interrupt fires
2613          */
2614         flush_domains = i915_retire_commands(dev);
2615
2616         i915_verify_inactive(dev, __FILE__, __LINE__);
2617
2618         /*
2619          * Get a seqno representing the execution of the current buffer,
2620          * which we can wait on.  We would like to mitigate these interrupts,
2621          * likely by only creating seqnos occasionally (so that we have
2622          * *some* interrupts representing completion of buffers that we can
2623          * wait on when trying to clear up gtt space).
2624          */
2625         seqno = i915_add_request(dev, flush_domains);
2626         BUG_ON(seqno == 0);
2627         i915_file_priv->mm.last_gem_seqno = seqno;
2628         for (i = 0; i < args->buffer_count; i++) {
2629                 struct drm_gem_object *obj = object_list[i];
2630
2631                 i915_gem_object_move_to_active(obj, seqno);
2632 #if WATCH_LRU
2633                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2634 #endif
2635         }
2636 #if WATCH_LRU
2637         i915_dump_lru(dev, __func__);
2638 #endif
2639
2640         i915_verify_inactive(dev, __FILE__, __LINE__);
2641
2642 err:
2643         for (i = 0; i < pinned; i++)
2644                 i915_gem_object_unpin(object_list[i]);
2645
2646         for (i = 0; i < args->buffer_count; i++)
2647                 drm_gem_object_unreference(object_list[i]);
2648
2649         mutex_unlock(&dev->struct_mutex);
2650
2651         if (!ret) {
2652                 /* Copy the new buffer offsets back to the user's exec list. */
2653                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2654                                    (uintptr_t) args->buffers_ptr,
2655                                    exec_list,
2656                                    sizeof(*exec_list) * args->buffer_count);
2657                 if (ret)
2658                         DRM_ERROR("failed to copy %d exec entries "
2659                                   "back to user (%d)\n",
2660                                   args->buffer_count, ret);
2661         }
2662
2663 pre_mutex_err:
2664         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2665                  DRM_MEM_DRIVER);
2666         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2667                  DRM_MEM_DRIVER);
2668
2669         return ret;
2670 }
2671
2672 int
2673 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2674 {
2675         struct drm_device *dev = obj->dev;
2676         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2677         int ret;
2678
2679         i915_verify_inactive(dev, __FILE__, __LINE__);
2680         if (obj_priv->gtt_space == NULL) {
2681                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2682                 if (ret != 0) {
2683                         if (ret != -EBUSY && ret != -ERESTARTSYS)
2684                                 DRM_ERROR("Failure to bind: %d", ret);
2685                         return ret;
2686                 }
2687                 /*
2688                  * Pre-965 chips need a fence register set up in order to
2689                  * properly handle tiled surfaces.
2690                  */
2691                 if (!IS_I965G(dev) &&
2692                     obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2693                     obj_priv->tiling_mode != I915_TILING_NONE)
2694                         i915_gem_object_get_fence_reg(obj, true);
2695         }
2696         obj_priv->pin_count++;
2697
2698         /* If the object is not active and not pending a flush,
2699          * remove it from the inactive list
2700          */
2701         if (obj_priv->pin_count == 1) {
2702                 atomic_inc(&dev->pin_count);
2703                 atomic_add(obj->size, &dev->pin_memory);
2704                 if (!obj_priv->active &&
2705                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2706                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2707                     !list_empty(&obj_priv->list))
2708                         list_del_init(&obj_priv->list);
2709         }
2710         i915_verify_inactive(dev, __FILE__, __LINE__);
2711
2712         return 0;
2713 }
2714
2715 void
2716 i915_gem_object_unpin(struct drm_gem_object *obj)
2717 {
2718         struct drm_device *dev = obj->dev;
2719         drm_i915_private_t *dev_priv = dev->dev_private;
2720         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2721
2722         i915_verify_inactive(dev, __FILE__, __LINE__);
2723         obj_priv->pin_count--;
2724         BUG_ON(obj_priv->pin_count < 0);
2725         BUG_ON(obj_priv->gtt_space == NULL);
2726
2727         /* If the object is no longer pinned, and is
2728          * neither active nor being flushed, then stick it on
2729          * the inactive list
2730          */
2731         if (obj_priv->pin_count == 0) {
2732                 if (!obj_priv->active &&
2733                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2734                                            I915_GEM_DOMAIN_GTT)) == 0)
2735                         list_move_tail(&obj_priv->list,
2736                                        &dev_priv->mm.inactive_list);
2737                 atomic_dec(&dev->pin_count);
2738                 atomic_sub(obj->size, &dev->pin_memory);
2739         }
2740         i915_verify_inactive(dev, __FILE__, __LINE__);
2741 }
2742
2743 int
2744 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2745                    struct drm_file *file_priv)
2746 {
2747         struct drm_i915_gem_pin *args = data;
2748         struct drm_gem_object *obj;
2749         struct drm_i915_gem_object *obj_priv;
2750         int ret;
2751
2752         mutex_lock(&dev->struct_mutex);
2753
2754         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2755         if (obj == NULL) {
2756                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2757                           args->handle);
2758                 mutex_unlock(&dev->struct_mutex);
2759                 return -EBADF;
2760         }
2761         obj_priv = obj->driver_private;
2762
2763         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2764                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2765                           args->handle);
2766                 drm_gem_object_unreference(obj);
2767                 mutex_unlock(&dev->struct_mutex);
2768                 return -EINVAL;
2769         }
2770
2771         obj_priv->user_pin_count++;
2772         obj_priv->pin_filp = file_priv;
2773         if (obj_priv->user_pin_count == 1) {
2774                 ret = i915_gem_object_pin(obj, args->alignment);
2775                 if (ret != 0) {
2776                         drm_gem_object_unreference(obj);
2777                         mutex_unlock(&dev->struct_mutex);
2778                         return ret;
2779                 }
2780         }
2781
2782         /* XXX - flush the CPU caches for pinned objects
2783          * as the X server doesn't manage domains yet
2784          */
2785         i915_gem_object_flush_cpu_write_domain(obj);
2786         args->offset = obj_priv->gtt_offset;
2787         drm_gem_object_unreference(obj);
2788         mutex_unlock(&dev->struct_mutex);
2789
2790         return 0;
2791 }
2792
2793 int
2794 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2795                      struct drm_file *file_priv)
2796 {
2797         struct drm_i915_gem_pin *args = data;
2798         struct drm_gem_object *obj;
2799         struct drm_i915_gem_object *obj_priv;
2800
2801         mutex_lock(&dev->struct_mutex);
2802
2803         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2804         if (obj == NULL) {
2805                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2806                           args->handle);
2807                 mutex_unlock(&dev->struct_mutex);
2808                 return -EBADF;
2809         }
2810
2811         obj_priv = obj->driver_private;
2812         if (obj_priv->pin_filp != file_priv) {
2813                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2814                           args->handle);
2815                 drm_gem_object_unreference(obj);
2816                 mutex_unlock(&dev->struct_mutex);
2817                 return -EINVAL;
2818         }
2819         obj_priv->user_pin_count--;
2820         if (obj_priv->user_pin_count == 0) {
2821                 obj_priv->pin_filp = NULL;
2822                 i915_gem_object_unpin(obj);
2823         }
2824
2825         drm_gem_object_unreference(obj);
2826         mutex_unlock(&dev->struct_mutex);
2827         return 0;
2828 }
2829
2830 int
2831 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2832                     struct drm_file *file_priv)
2833 {
2834         struct drm_i915_gem_busy *args = data;
2835         struct drm_gem_object *obj;
2836         struct drm_i915_gem_object *obj_priv;
2837
2838         mutex_lock(&dev->struct_mutex);
2839         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2840         if (obj == NULL) {
2841                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2842                           args->handle);
2843                 mutex_unlock(&dev->struct_mutex);
2844                 return -EBADF;
2845         }
2846
2847         obj_priv = obj->driver_private;
2848         /* Don't count being on the flushing list against the object being
2849          * done.  Otherwise, a buffer left on the flushing list but not getting
2850          * flushed (because nobody's flushing that domain) won't ever return
2851          * unbusy and get reused by libdrm's bo cache.  The other expected
2852          * consumer of this interface, OpenGL's occlusion queries, also specs
2853          * that the objects get unbusy "eventually" without any interference.
2854          */
2855         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2856
2857         drm_gem_object_unreference(obj);
2858         mutex_unlock(&dev->struct_mutex);
2859         return 0;
2860 }
2861
2862 int
2863 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2864                         struct drm_file *file_priv)
2865 {
2866     return i915_gem_ring_throttle(dev, file_priv);
2867 }
2868
2869 int i915_gem_init_object(struct drm_gem_object *obj)
2870 {
2871         struct drm_i915_gem_object *obj_priv;
2872
2873         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2874         if (obj_priv == NULL)
2875                 return -ENOMEM;
2876
2877         /*
2878          * We've just allocated pages from the kernel,
2879          * so they've just been written by the CPU with
2880          * zeros. They'll need to be clflushed before we
2881          * use them with the GPU.
2882          */
2883         obj->write_domain = I915_GEM_DOMAIN_CPU;
2884         obj->read_domains = I915_GEM_DOMAIN_CPU;
2885
2886         obj_priv->agp_type = AGP_USER_MEMORY;
2887
2888         obj->driver_private = obj_priv;
2889         obj_priv->obj = obj;
2890         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2891         INIT_LIST_HEAD(&obj_priv->list);
2892
2893         return 0;
2894 }
2895
2896 void i915_gem_free_object(struct drm_gem_object *obj)
2897 {
2898         struct drm_device *dev = obj->dev;
2899         struct drm_gem_mm *mm = dev->mm_private;
2900         struct drm_map_list *list;
2901         struct drm_map *map;
2902         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2903
2904         while (obj_priv->pin_count > 0)
2905                 i915_gem_object_unpin(obj);
2906
2907         if (obj_priv->phys_obj)
2908                 i915_gem_detach_phys_object(dev, obj);
2909
2910         i915_gem_object_unbind(obj);
2911
2912         list = &obj->map_list;
2913         drm_ht_remove_item(&mm->offset_hash, &list->hash);
2914
2915         if (list->file_offset_node) {
2916                 drm_mm_put_block(list->file_offset_node);
2917                 list->file_offset_node = NULL;
2918         }
2919
2920         map = list->map;
2921         if (map) {
2922                 drm_free(map, sizeof(*map), DRM_MEM_DRIVER);
2923                 list->map = NULL;
2924         }
2925
2926         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2927         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2928 }
2929
2930 /** Unbinds all objects that are on the given buffer list. */
2931 static int
2932 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2933 {
2934         struct drm_gem_object *obj;
2935         struct drm_i915_gem_object *obj_priv;
2936         int ret;
2937
2938         while (!list_empty(head)) {
2939                 obj_priv = list_first_entry(head,
2940                                             struct drm_i915_gem_object,
2941                                             list);
2942                 obj = obj_priv->obj;
2943
2944                 if (obj_priv->pin_count != 0) {
2945                         DRM_ERROR("Pinned object in unbind list\n");
2946                         mutex_unlock(&dev->struct_mutex);
2947                         return -EINVAL;
2948                 }
2949
2950                 ret = i915_gem_object_unbind(obj);
2951                 if (ret != 0) {
2952                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2953                                   ret);
2954                         mutex_unlock(&dev->struct_mutex);
2955                         return ret;
2956                 }
2957         }
2958
2959
2960         return 0;
2961 }
2962
2963 static int
2964 i915_gem_idle(struct drm_device *dev)
2965 {
2966         drm_i915_private_t *dev_priv = dev->dev_private;
2967         uint32_t seqno, cur_seqno, last_seqno;
2968         int stuck, ret;
2969
2970         mutex_lock(&dev->struct_mutex);
2971
2972         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2973                 mutex_unlock(&dev->struct_mutex);
2974                 return 0;
2975         }
2976
2977         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2978          * We need to replace this with a semaphore, or something.
2979          */
2980         dev_priv->mm.suspended = 1;
2981
2982         /* Cancel the retire work handler, wait for it to finish if running
2983          */
2984         mutex_unlock(&dev->struct_mutex);
2985         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2986         mutex_lock(&dev->struct_mutex);
2987
2988         i915_kernel_lost_context(dev);
2989
2990         /* Flush the GPU along with all non-CPU write domains
2991          */
2992         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2993                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2994         seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
2995
2996         if (seqno == 0) {
2997                 mutex_unlock(&dev->struct_mutex);
2998                 return -ENOMEM;
2999         }
3000
3001         dev_priv->mm.waiting_gem_seqno = seqno;
3002         last_seqno = 0;
3003         stuck = 0;
3004         for (;;) {
3005                 cur_seqno = i915_get_gem_seqno(dev);
3006                 if (i915_seqno_passed(cur_seqno, seqno))
3007                         break;
3008                 if (last_seqno == cur_seqno) {
3009                         if (stuck++ > 100) {
3010                                 DRM_ERROR("hardware wedged\n");
3011                                 dev_priv->mm.wedged = 1;
3012                                 DRM_WAKEUP(&dev_priv->irq_queue);
3013                                 break;
3014                         }
3015                 }
3016                 msleep(10);
3017                 last_seqno = cur_seqno;
3018         }
3019         dev_priv->mm.waiting_gem_seqno = 0;
3020
3021         i915_gem_retire_requests(dev);
3022
3023         if (!dev_priv->mm.wedged) {
3024                 /* Active and flushing should now be empty as we've
3025                  * waited for a sequence higher than any pending execbuffer
3026                  */
3027                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3028                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3029                 /* Request should now be empty as we've also waited
3030                  * for the last request in the list
3031                  */
3032                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3033         }
3034
3035         /* Empty the active and flushing lists to inactive.  If there's
3036          * anything left at this point, it means that we're wedged and
3037          * nothing good's going to happen by leaving them there.  So strip
3038          * the GPU domains and just stuff them onto inactive.
3039          */
3040         while (!list_empty(&dev_priv->mm.active_list)) {
3041                 struct drm_i915_gem_object *obj_priv;
3042
3043                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3044                                             struct drm_i915_gem_object,
3045                                             list);
3046                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3047                 i915_gem_object_move_to_inactive(obj_priv->obj);
3048         }
3049
3050         while (!list_empty(&dev_priv->mm.flushing_list)) {
3051                 struct drm_i915_gem_object *obj_priv;
3052
3053                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3054                                             struct drm_i915_gem_object,
3055                                             list);
3056                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3057                 i915_gem_object_move_to_inactive(obj_priv->obj);
3058         }
3059
3060
3061         /* Move all inactive buffers out of the GTT. */
3062         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3063         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3064         if (ret) {
3065                 mutex_unlock(&dev->struct_mutex);
3066                 return ret;
3067         }
3068
3069         i915_gem_cleanup_ringbuffer(dev);
3070         mutex_unlock(&dev->struct_mutex);
3071
3072         return 0;
3073 }
3074
3075 static int
3076 i915_gem_init_hws(struct drm_device *dev)
3077 {
3078         drm_i915_private_t *dev_priv = dev->dev_private;
3079         struct drm_gem_object *obj;
3080         struct drm_i915_gem_object *obj_priv;
3081         int ret;
3082
3083         /* If we need a physical address for the status page, it's already
3084          * initialized at driver load time.
3085          */
3086         if (!I915_NEED_GFX_HWS(dev))
3087                 return 0;
3088
3089         obj = drm_gem_object_alloc(dev, 4096);
3090         if (obj == NULL) {
3091                 DRM_ERROR("Failed to allocate status page\n");
3092                 return -ENOMEM;
3093         }
3094         obj_priv = obj->driver_private;
3095         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3096
3097         ret = i915_gem_object_pin(obj, 4096);
3098         if (ret != 0) {
3099                 drm_gem_object_unreference(obj);
3100                 return ret;
3101         }
3102
3103         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3104
3105         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3106         if (dev_priv->hw_status_page == NULL) {
3107                 DRM_ERROR("Failed to map status page.\n");
3108                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3109                 drm_gem_object_unreference(obj);
3110                 return -EINVAL;
3111         }
3112         dev_priv->hws_obj = obj;
3113         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3114         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3115         I915_READ(HWS_PGA); /* posting read */
3116         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3117
3118         return 0;
3119 }
3120
3121 int
3122 i915_gem_init_ringbuffer(struct drm_device *dev)
3123 {
3124         drm_i915_private_t *dev_priv = dev->dev_private;
3125         struct drm_gem_object *obj;
3126         struct drm_i915_gem_object *obj_priv;
3127         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3128         int ret;
3129         u32 head;
3130
3131         ret = i915_gem_init_hws(dev);
3132         if (ret != 0)
3133                 return ret;
3134
3135         obj = drm_gem_object_alloc(dev, 128 * 1024);
3136         if (obj == NULL) {
3137                 DRM_ERROR("Failed to allocate ringbuffer\n");
3138                 return -ENOMEM;
3139         }
3140         obj_priv = obj->driver_private;
3141
3142         ret = i915_gem_object_pin(obj, 4096);
3143         if (ret != 0) {
3144                 drm_gem_object_unreference(obj);
3145                 return ret;
3146         }
3147
3148         /* Set up the kernel mapping for the ring. */
3149         ring->Size = obj->size;
3150         ring->tail_mask = obj->size - 1;
3151
3152         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3153         ring->map.size = obj->size;
3154         ring->map.type = 0;
3155         ring->map.flags = 0;
3156         ring->map.mtrr = 0;
3157
3158         drm_core_ioremap_wc(&ring->map, dev);
3159         if (ring->map.handle == NULL) {
3160                 DRM_ERROR("Failed to map ringbuffer.\n");
3161                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3162                 drm_gem_object_unreference(obj);
3163                 return -EINVAL;
3164         }
3165         ring->ring_obj = obj;
3166         ring->virtual_start = ring->map.handle;
3167
3168         /* Stop the ring if it's running. */
3169         I915_WRITE(PRB0_CTL, 0);
3170         I915_WRITE(PRB0_TAIL, 0);
3171         I915_WRITE(PRB0_HEAD, 0);
3172
3173         /* Initialize the ring. */
3174         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3175         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3176
3177         /* G45 ring initialization fails to reset head to zero */
3178         if (head != 0) {
3179                 DRM_ERROR("Ring head not reset to zero "
3180                           "ctl %08x head %08x tail %08x start %08x\n",
3181                           I915_READ(PRB0_CTL),
3182                           I915_READ(PRB0_HEAD),
3183                           I915_READ(PRB0_TAIL),
3184                           I915_READ(PRB0_START));
3185                 I915_WRITE(PRB0_HEAD, 0);
3186
3187                 DRM_ERROR("Ring head forced to zero "
3188                           "ctl %08x head %08x tail %08x start %08x\n",
3189                           I915_READ(PRB0_CTL),
3190                           I915_READ(PRB0_HEAD),
3191                           I915_READ(PRB0_TAIL),
3192                           I915_READ(PRB0_START));
3193         }
3194
3195         I915_WRITE(PRB0_CTL,
3196                    ((obj->size - 4096) & RING_NR_PAGES) |
3197                    RING_NO_REPORT |
3198                    RING_VALID);
3199
3200         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3201
3202         /* If the head is still not zero, the ring is dead */
3203         if (head != 0) {
3204                 DRM_ERROR("Ring initialization failed "
3205                           "ctl %08x head %08x tail %08x start %08x\n",
3206                           I915_READ(PRB0_CTL),
3207                           I915_READ(PRB0_HEAD),
3208                           I915_READ(PRB0_TAIL),
3209                           I915_READ(PRB0_START));
3210                 return -EIO;
3211         }
3212
3213         /* Update our cache of the ring state */
3214         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3215                 i915_kernel_lost_context(dev);
3216         else {
3217                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3218                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3219                 ring->space = ring->head - (ring->tail + 8);
3220                 if (ring->space < 0)
3221                         ring->space += ring->Size;
3222         }
3223
3224         return 0;
3225 }
3226
3227 void
3228 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3229 {
3230         drm_i915_private_t *dev_priv = dev->dev_private;
3231
3232         if (dev_priv->ring.ring_obj == NULL)
3233                 return;
3234
3235         drm_core_ioremapfree(&dev_priv->ring.map, dev);
3236
3237         i915_gem_object_unpin(dev_priv->ring.ring_obj);
3238         drm_gem_object_unreference(dev_priv->ring.ring_obj);
3239         dev_priv->ring.ring_obj = NULL;
3240         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3241
3242         if (dev_priv->hws_obj != NULL) {
3243                 struct drm_gem_object *obj = dev_priv->hws_obj;
3244                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3245
3246                 kunmap(obj_priv->page_list[0]);
3247                 i915_gem_object_unpin(obj);
3248                 drm_gem_object_unreference(obj);
3249                 dev_priv->hws_obj = NULL;
3250                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3251                 dev_priv->hw_status_page = NULL;
3252
3253                 /* Write high address into HWS_PGA when disabling. */
3254                 I915_WRITE(HWS_PGA, 0x1ffff000);
3255         }
3256 }
3257
3258 int
3259 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3260                        struct drm_file *file_priv)
3261 {
3262         drm_i915_private_t *dev_priv = dev->dev_private;
3263         int ret;
3264
3265         if (drm_core_check_feature(dev, DRIVER_MODESET))
3266                 return 0;
3267
3268         if (dev_priv->mm.wedged) {
3269                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3270                 dev_priv->mm.wedged = 0;
3271         }
3272
3273         mutex_lock(&dev->struct_mutex);
3274         dev_priv->mm.suspended = 0;
3275
3276         ret = i915_gem_init_ringbuffer(dev);
3277         if (ret != 0)
3278                 return ret;
3279
3280         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3281         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3282         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3283         BUG_ON(!list_empty(&dev_priv->mm.request_list));
3284         mutex_unlock(&dev->struct_mutex);
3285
3286         drm_irq_install(dev);
3287
3288         return 0;
3289 }
3290
3291 int
3292 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3293                        struct drm_file *file_priv)
3294 {
3295         int ret;
3296
3297         if (drm_core_check_feature(dev, DRIVER_MODESET))
3298                 return 0;
3299
3300         ret = i915_gem_idle(dev);
3301         drm_irq_uninstall(dev);
3302
3303         return ret;
3304 }
3305
3306 void
3307 i915_gem_lastclose(struct drm_device *dev)
3308 {
3309         int ret;
3310
3311         if (drm_core_check_feature(dev, DRIVER_MODESET))
3312                 return;
3313
3314         ret = i915_gem_idle(dev);
3315         if (ret)
3316                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3317 }
3318
3319 void
3320 i915_gem_load(struct drm_device *dev)
3321 {
3322         drm_i915_private_t *dev_priv = dev->dev_private;
3323
3324         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3325         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3326         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3327         INIT_LIST_HEAD(&dev_priv->mm.request_list);
3328         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3329                           i915_gem_retire_work_handler);
3330         dev_priv->mm.next_gem_seqno = 1;
3331
3332         /* Old X drivers will take 0-2 for front, back, depth buffers */
3333         dev_priv->fence_reg_start = 3;
3334
3335         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3336                 dev_priv->num_fence_regs = 16;
3337         else
3338                 dev_priv->num_fence_regs = 8;
3339
3340         i915_gem_detect_bit_6_swizzle(dev);
3341 }
3342
3343 /*
3344  * Create a physically contiguous memory object for this object
3345  * e.g. for cursor + overlay regs
3346  */
3347 int i915_gem_init_phys_object(struct drm_device *dev,
3348                               int id, int size)
3349 {
3350         drm_i915_private_t *dev_priv = dev->dev_private;
3351         struct drm_i915_gem_phys_object *phys_obj;
3352         int ret;
3353
3354         if (dev_priv->mm.phys_objs[id - 1] || !size)
3355                 return 0;
3356
3357         phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3358         if (!phys_obj)
3359                 return -ENOMEM;
3360
3361         phys_obj->id = id;
3362
3363         phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3364         if (!phys_obj->handle) {
3365                 ret = -ENOMEM;
3366                 goto kfree_obj;
3367         }
3368 #ifdef CONFIG_X86
3369         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3370 #endif
3371
3372         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3373
3374         return 0;
3375 kfree_obj:
3376         drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3377         return ret;
3378 }
3379
3380 void i915_gem_free_phys_object(struct drm_device *dev, int id)
3381 {
3382         drm_i915_private_t *dev_priv = dev->dev_private;
3383         struct drm_i915_gem_phys_object *phys_obj;
3384
3385         if (!dev_priv->mm.phys_objs[id - 1])
3386                 return;
3387
3388         phys_obj = dev_priv->mm.phys_objs[id - 1];
3389         if (phys_obj->cur_obj) {
3390                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3391         }
3392
3393 #ifdef CONFIG_X86
3394         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3395 #endif
3396         drm_pci_free(dev, phys_obj->handle);
3397         kfree(phys_obj);
3398         dev_priv->mm.phys_objs[id - 1] = NULL;
3399 }
3400
3401 void i915_gem_free_all_phys_object(struct drm_device *dev)
3402 {
3403         int i;
3404
3405         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3406                 i915_gem_free_phys_object(dev, i);
3407 }
3408
3409 void i915_gem_detach_phys_object(struct drm_device *dev,
3410                                  struct drm_gem_object *obj)
3411 {
3412         struct drm_i915_gem_object *obj_priv;
3413         int i;
3414         int ret;
3415         int page_count;
3416
3417         obj_priv = obj->driver_private;
3418         if (!obj_priv->phys_obj)
3419                 return;
3420
3421         ret = i915_gem_object_get_page_list(obj);
3422         if (ret)
3423                 goto out;
3424
3425         page_count = obj->size / PAGE_SIZE;
3426
3427         for (i = 0; i < page_count; i++) {
3428                 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3429                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3430
3431                 memcpy(dst, src, PAGE_SIZE);
3432                 kunmap_atomic(dst, KM_USER0);
3433         }
3434         drm_clflush_pages(obj_priv->page_list, page_count);
3435         drm_agp_chipset_flush(dev);
3436 out:
3437         obj_priv->phys_obj->cur_obj = NULL;
3438         obj_priv->phys_obj = NULL;
3439 }
3440
3441 int
3442 i915_gem_attach_phys_object(struct drm_device *dev,
3443                             struct drm_gem_object *obj, int id)
3444 {
3445         drm_i915_private_t *dev_priv = dev->dev_private;
3446         struct drm_i915_gem_object *obj_priv;
3447         int ret = 0;
3448         int page_count;
3449         int i;
3450
3451         if (id > I915_MAX_PHYS_OBJECT)
3452                 return -EINVAL;
3453
3454         obj_priv = obj->driver_private;
3455
3456         if (obj_priv->phys_obj) {
3457                 if (obj_priv->phys_obj->id == id)
3458                         return 0;
3459                 i915_gem_detach_phys_object(dev, obj);
3460         }
3461
3462
3463         /* create a new object */
3464         if (!dev_priv->mm.phys_objs[id - 1]) {
3465                 ret = i915_gem_init_phys_object(dev, id,
3466                                                 obj->size);
3467                 if (ret) {
3468                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
3469                         goto out;
3470                 }
3471         }
3472
3473         /* bind to the object */
3474         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3475         obj_priv->phys_obj->cur_obj = obj;
3476
3477         ret = i915_gem_object_get_page_list(obj);
3478         if (ret) {
3479                 DRM_ERROR("failed to get page list\n");
3480                 goto out;
3481         }
3482
3483         page_count = obj->size / PAGE_SIZE;
3484
3485         for (i = 0; i < page_count; i++) {
3486                 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3487                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3488
3489                 memcpy(dst, src, PAGE_SIZE);
3490                 kunmap_atomic(src, KM_USER0);
3491         }
3492
3493         return 0;
3494 out:
3495         return ret;
3496 }
3497
3498 static int
3499 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3500                      struct drm_i915_gem_pwrite *args,
3501                      struct drm_file *file_priv)
3502 {
3503         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3504         void *obj_addr;
3505         int ret;
3506         char __user *user_data;
3507
3508         user_data = (char __user *) (uintptr_t) args->data_ptr;
3509         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3510
3511         DRM_ERROR("obj_addr %p, %lld\n", obj_addr, args->size);
3512         ret = copy_from_user(obj_addr, user_data, args->size);
3513         if (ret)
3514                 return -EFAULT;
3515
3516         drm_agp_chipset_flush(dev);
3517         return 0;
3518 }