1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
21 select CPU_PABRT_NOIFAR
23 The ARM610 is the successor to the ARM3 processor
24 and was produced by VLSI Technology Inc.
26 Say Y if you want support for the ARM610 processor.
31 bool "Support ARM7TDMI processor"
35 select CPU_PABRT_NOIFAR
38 A 32-bit RISC microprocessor based on the ARM7 processor core
39 which has no memory control unit and cache.
41 Say Y if you want support for the ARM7TDMI processor.
46 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
47 default y if ARCH_CLPS7500
52 select CPU_COPY_V3 if MMU
53 select CPU_TLB_V3 if MMU
54 select CPU_PABRT_NOIFAR
56 A 32-bit RISC microprocessor based on the ARM7 processor core
57 designed by Advanced RISC Machines Ltd. The ARM710 is the
58 successor to the ARM610 processor. It was released in
59 July 1994 by VLSI Technology Inc.
61 Say Y if you want support for the ARM710 processor.
66 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
67 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
70 select CPU_PABRT_NOIFAR
74 select CPU_COPY_V4WT if MMU
75 select CPU_TLB_V4WT if MMU
77 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
78 MMU built around an ARM7TDMI core.
80 Say Y if you want support for the ARM720T processor.
85 bool "Support ARM740T processor" if ARCH_INTEGRATOR
89 select CPU_PABRT_NOIFAR
90 select CPU_CACHE_V3 # although the core is v4t
93 A 32-bit RISC processor with 8KB cache or 4KB variants,
94 write buffer and MPU(Protection Unit) built around
97 Say Y if you want support for the ARM740T processor.
102 bool "Support ARM9TDMI processor"
105 select CPU_ABRT_NOMMU
106 select CPU_PABRT_NOIFAR
109 A 32-bit RISC microprocessor based on the ARM9 processor core
110 which has no memory control unit and cache.
112 Say Y if you want support for the ARM9TDMI processor.
117 bool "Support ARM920T processor"
118 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
119 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
122 select CPU_PABRT_NOIFAR
123 select CPU_CACHE_V4WT
124 select CPU_CACHE_VIVT
126 select CPU_COPY_V4WB if MMU
127 select CPU_TLB_V4WBI if MMU
129 The ARM920T is licensed to be produced by numerous vendors,
130 and is used in the Maverick EP9312 and the Samsung S3C2410.
132 More information on the Maverick EP9312 at
133 <http://linuxdevices.com/products/PD2382866068.html>.
135 Say Y if you want support for the ARM920T processor.
140 bool "Support ARM922T processor" if ARCH_INTEGRATOR
141 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
142 default y if ARCH_LH7A40X || ARCH_KS8695
145 select CPU_PABRT_NOIFAR
146 select CPU_CACHE_V4WT
147 select CPU_CACHE_VIVT
149 select CPU_COPY_V4WB if MMU
150 select CPU_TLB_V4WBI if MMU
152 The ARM922T is a version of the ARM920T, but with smaller
153 instruction and data caches. It is used in Altera's
154 Excalibur XA device family and Micrel's KS8695 Centaur.
156 Say Y if you want support for the ARM922T processor.
161 bool "Support ARM925T processor" if ARCH_OMAP1
162 depends on ARCH_OMAP15XX
163 default y if ARCH_OMAP15XX
166 select CPU_PABRT_NOIFAR
167 select CPU_CACHE_V4WT
168 select CPU_CACHE_VIVT
170 select CPU_COPY_V4WB if MMU
171 select CPU_TLB_V4WBI if MMU
173 The ARM925T is a mix between the ARM920T and ARM926T, but with
174 different instruction and data caches. It is used in TI's OMAP
177 Say Y if you want support for the ARM925T processor.
182 bool "Support ARM926T processor"
183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
184 MACH_VERSATILE_AB || ARCH_OMAP730 || \
185 ARCH_OMAP16XX || MACH_REALVIEW_EB || \
186 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
187 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
188 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
189 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
190 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
191 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
192 ARCH_OMAP730 || ARCH_OMAP16XX || \
193 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
194 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
195 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
196 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
197 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
199 select CPU_ABRT_EV5TJ
200 select CPU_PABRT_NOIFAR
201 select CPU_CACHE_VIVT
203 select CPU_COPY_V4WB if MMU
204 select CPU_TLB_V4WBI if MMU
206 This is a variant of the ARM920. It has slightly different
207 instruction sequences for cache and TLB operations. Curiously,
208 there is no documentation on it at the ARM corporate website.
210 Say Y if you want support for the ARM926T processor.
215 bool "Support ARM940T processor" if ARCH_INTEGRATOR
218 select CPU_ABRT_NOMMU
219 select CPU_PABRT_NOIFAR
220 select CPU_CACHE_VIVT
223 ARM940T is a member of the ARM9TDMI family of general-
224 purpose microprocessors with MPU and separate 4KB
225 instruction and 4KB data cases, each with a 4-word line
228 Say Y if you want support for the ARM940T processor.
233 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
236 select CPU_ABRT_NOMMU
237 select CPU_PABRT_NOIFAR
238 select CPU_CACHE_VIVT
241 ARM946E-S is a member of the ARM9E-S family of high-
242 performance, 32-bit system-on-chip processor solutions.
243 The TCM and ARMv5TE 32-bit instruction set is supported.
245 Say Y if you want support for the ARM946E-S processor.
248 # ARM1020 - needs validating
250 bool "Support ARM1020T (rev 0) processor"
251 depends on ARCH_INTEGRATOR
254 select CPU_PABRT_NOIFAR
255 select CPU_CACHE_V4WT
256 select CPU_CACHE_VIVT
258 select CPU_COPY_V4WB if MMU
259 select CPU_TLB_V4WBI if MMU
261 The ARM1020 is the 32K cached version of the ARM10 processor,
262 with an addition of a floating-point unit.
264 Say Y if you want support for the ARM1020 processor.
267 # ARM1020E - needs validating
269 bool "Support ARM1020E processor"
270 depends on ARCH_INTEGRATOR
273 select CPU_PABRT_NOIFAR
274 select CPU_CACHE_V4WT
275 select CPU_CACHE_VIVT
277 select CPU_COPY_V4WB if MMU
278 select CPU_TLB_V4WBI if MMU
283 bool "Support ARM1022E processor"
284 depends on ARCH_INTEGRATOR
287 select CPU_PABRT_NOIFAR
288 select CPU_CACHE_VIVT
290 select CPU_COPY_V4WB if MMU # can probably do better
291 select CPU_TLB_V4WBI if MMU
293 The ARM1022E is an implementation of the ARMv5TE architecture
294 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
295 embedded trace macrocell, and a floating-point unit.
297 Say Y if you want support for the ARM1022E processor.
302 bool "Support ARM1026EJ-S processor"
303 depends on ARCH_INTEGRATOR
305 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
306 select CPU_PABRT_NOIFAR
307 select CPU_CACHE_VIVT
309 select CPU_COPY_V4WB if MMU # can probably do better
310 select CPU_TLB_V4WBI if MMU
312 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
313 based upon the ARM10 integer core.
315 Say Y if you want support for the ARM1026EJ-S processor.
320 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
321 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
322 select CPU_32v3 if ARCH_RPC
323 select CPU_32v4 if !ARCH_RPC
325 select CPU_PABRT_NOIFAR
326 select CPU_CACHE_V4WB
327 select CPU_CACHE_VIVT
329 select CPU_COPY_V4WB if MMU
330 select CPU_TLB_V4WB if MMU
332 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
333 is available at five speeds ranging from 100 MHz to 233 MHz.
334 More information is available at
335 <http://developer.intel.com/design/strong/sa110.htm>.
337 Say Y if you want support for the SA-110 processor.
343 depends on ARCH_SA1100
347 select CPU_PABRT_NOIFAR
348 select CPU_CACHE_V4WB
349 select CPU_CACHE_VIVT
351 select CPU_TLB_V4WB if MMU
356 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
360 select CPU_PABRT_NOIFAR
361 select CPU_CACHE_VIVT
363 select CPU_TLB_V4WBI if MMU
365 # XScale Core Version 3
368 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
372 select CPU_PABRT_NOIFAR
373 select CPU_CACHE_VIVT
375 select CPU_TLB_V4WBI if MMU
381 depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
385 select CPU_PABRT_NOIFAR
386 select CPU_CACHE_VIVT
388 select CPU_COPY_FEROCEON if MMU
389 select CPU_TLB_FEROCEON if MMU
391 config CPU_FEROCEON_OLD_ID
392 bool "Accept early Feroceon cores with an ARM926 ID"
393 depends on CPU_FEROCEON && !CPU_ARM926T
396 This enables the usage of some old Feroceon cores
397 for which the CPU ID is equal to the ARM926 ID.
398 Relevant for Feroceon-1850 and early Feroceon-2850.
402 bool "Support ARM V6 processor"
403 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
404 default y if ARCH_MX3
405 default y if ARCH_MSM7X00A
408 select CPU_PABRT_NOIFAR
410 select CPU_CACHE_VIPT
412 select CPU_HAS_ASID if MMU
413 select CPU_COPY_V6 if MMU
414 select CPU_TLB_V6 if MMU
418 bool "Support ARM V6K processor extensions" if !SMP
420 default y if SMP && !ARCH_MX3
422 Say Y here if your ARMv6 processor supports the 'K' extension.
423 This enables the kernel to use some instructions not present
424 on previous processors, and as such a kernel build with this
425 enabled will not boot on processors with do not support these
430 bool "Support ARM V7 processor"
431 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
435 select CPU_PABRT_IFAR
437 select CPU_CACHE_VIPT
439 select CPU_HAS_ASID if MMU
440 select CPU_COPY_V6 if MMU
441 select CPU_TLB_V7 if MMU
443 # Figure out what processor architecture version we should be using.
444 # This defines the compiler instruction set which depends on the machine type.
447 select TLS_REG_EMUL if SMP || !MMU
448 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
452 select TLS_REG_EMUL if SMP || !MMU
453 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
457 select TLS_REG_EMUL if SMP || !MMU
458 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
462 select TLS_REG_EMUL if SMP || !MMU
463 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
467 select TLS_REG_EMUL if !CPU_32v6K && !MMU
473 config CPU_ABRT_NOMMU
488 config CPU_ABRT_EV5TJ
497 config CPU_PABRT_IFAR
500 config CPU_PABRT_NOIFAR
510 config CPU_CACHE_V4WT
513 config CPU_CACHE_V4WB
522 config CPU_CACHE_VIVT
525 config CPU_CACHE_VIPT
529 # The copy-page model
539 config CPU_COPY_FEROCEON
545 # This selects the TLB model
549 ARM Architecture Version 3 TLB.
554 ARM Architecture Version 4 TLB with writethrough cache.
559 ARM Architecture Version 4 TLB with writeback cache.
564 ARM Architecture Version 4 TLB with writeback cache and invalidate
565 instruction cache entry.
567 config CPU_TLB_FEROCEON
570 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
583 This indicates whether the CPU has the ASID register; used to
584 tag TLB and possibly cache entries.
589 Processor has the CP15 register.
595 Processor has the CP15 register, which has MMU related registers.
601 Processor has the CP15 register, which has MPU related registers.
604 # CPU supports 36-bit I/O
609 comment "Processor Features"
612 bool "Support Thumb user binaries"
613 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
616 Say Y if you want to include kernel support for running user space
619 The Thumb instruction set is a compressed form of the standard ARM
620 instruction set resulting in smaller binaries at the expense of
621 slightly less efficient code.
623 If you don't know what this all is, saying Y is a safe choice.
626 bool "Enable ThumbEE CPU extension"
629 Say Y here if you have a CPU with the ThumbEE extension and code to
630 make use of it. Say N for code that can run on CPUs without ThumbEE.
632 config CPU_BIG_ENDIAN
633 bool "Build big-endian kernel"
634 depends on ARCH_SUPPORTS_BIG_ENDIAN
636 Say Y if you plan on running a kernel in big-endian mode.
637 Note that your board must be properly built and your board
638 port must properly enable any big-endian related features
639 of your chipset/board/processor.
641 config CPU_HIGH_VECTOR
642 depends on !MMU && CPU_CP15 && !CPU_ARM740T
643 bool "Select the High exception vector"
646 Say Y here to select high exception vector(0xFFFF0000~).
647 The exception vector can be vary depending on the platform
648 design in nommu mode. If your platform needs to select
649 high exception vector, say Y.
650 Otherwise or if you are unsure, say N, and the low exception
651 vector (0x00000000~) will be used.
653 config CPU_ICACHE_DISABLE
654 bool "Disable I-Cache (I-bit)"
655 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
657 Say Y here to disable the processor instruction cache. Unless
658 you have a reason not to or are unsure, say N.
660 config CPU_DCACHE_DISABLE
661 bool "Disable D-Cache (C-bit)"
664 Say Y here to disable the processor data cache. Unless
665 you have a reason not to or are unsure, say N.
667 config CPU_DCACHE_SIZE
669 depends on CPU_ARM740T || CPU_ARM946E
670 default 0x00001000 if CPU_ARM740T
671 default 0x00002000 # default size for ARM946E-S
673 Some cores are synthesizable to have various sized cache. For
674 ARM946E-S case, it can vary from 0KB to 1MB.
675 To support such cache operations, it is efficient to know the size
677 If your SoC is configured to have a different size, define the value
678 here with proper conditions.
680 config CPU_DCACHE_WRITETHROUGH
681 bool "Force write through D-cache"
682 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
683 default y if CPU_ARM925T
685 Say Y here to use the data cache in writethrough mode. Unless you
686 specifically require this or are unsure, say N.
688 config CPU_CACHE_ROUND_ROBIN
689 bool "Round robin I and D cache replacement algorithm"
690 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
692 Say Y here to use the predictable round-robin cache replacement
693 policy. Unless you specifically require this or are unsure, say N.
695 config CPU_BPREDICT_DISABLE
696 bool "Disable branch prediction"
697 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
699 Say Y here to disable branch prediction. If unsure, say N.
704 An SMP system using a pre-ARMv6 processor (there are apparently
705 a few prototypes like that in existence) and therefore access to
706 that required register must be emulated.
710 depends on !TLS_REG_EMUL
711 default y if SMP || CPU_32v7
713 This selects support for the CP15 thread register.
714 It is defined to be available on some ARMv6 processors (including
715 all SMP capable ARMv6's) or later processors. User space may
716 assume directly accessing that register and always obtain the
717 expected value only on ARMv7 and above.
719 config NEEDS_SYSCALL_FOR_CMPXCHG
722 SMP on a pre-ARMv6 processor? Well OK then.
723 Forget about fast user space cmpxchg support.
724 It is just not possible.
730 config CACHE_FEROCEON_L2
731 bool "Enable the Feroceon L2 cache controller"
732 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
736 This option enables the Feroceon L2 cache controller.
738 config CACHE_FEROCEON_L2_WRITETHROUGH
739 bool "Force Feroceon L2 cache write through"
740 depends on CACHE_FEROCEON_L2
743 Say Y here to use the Feroceon L2 cache in writethrough mode.
744 Unless you specifically require this, say N for writeback mode.
747 bool "Enable the L2x0 outer cache controller"
748 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
752 This option enables the L2x0 PrimeCell.
755 bool "Enable the L2 cache on XScale3"
760 This option enables the L2 cache on XScale3.