git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xf86Cursor.h"
   9 #include "xf86int10.h"
  10 #include "exa.h"
  11 #ifdef XF86DRI
  12 #define _XF86DRI_SERVER_
  13 #include "xf86drm.h"
  14 #include "dri.h"
  15 #include <stdint.h>
  16 #include "nouveau_drm.h"
  17 #include "xf86Crtc.h"
  18 #else
  19 #error "This driver requires a DRI-enabled X server"
  20 #endif
  21
  22 #include "nv50_type.h"
  23 #include "nv_pcicompat.h"
  24
  25 #include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
  26
  27 #define NV_ARCH_03  0x03
  28 #define NV_ARCH_04  0x04
  29 #define NV_ARCH_10  0x10
  30 #define NV_ARCH_20  0x20
  31 #define NV_ARCH_30  0x30
  32 #define NV_ARCH_40  0x40
  33 #define NV_ARCH_50  0x50
  34
  35 #define CHIPSET_NV03     0x0010
  36 #define CHIPSET_NV04     0x0020
  37 #define CHIPSET_NV10     0x0100
  38 #define CHIPSET_NV11     0x0110
  39 #define CHIPSET_NV15     0x0150
  40 #define CHIPSET_NV17     0x0170
  41 #define CHIPSET_NV18     0x0180
  42 #define CHIPSET_NFORCE   0x01A0
  43 #define CHIPSET_NFORCE2  0x01F0
  44 #define CHIPSET_NV20     0x0200
  45 #define CHIPSET_NV25     0x0250
  46 #define CHIPSET_NV28     0x0280
  47 #define CHIPSET_NV30     0x0300
  48 #define CHIPSET_NV31     0x0310
  49 #define CHIPSET_NV34     0x0320
  50 #define CHIPSET_NV35     0x0330
  51 #define CHIPSET_NV36     0x0340
  52 #define CHIPSET_NV40     0x0040
  53 #define CHIPSET_NV41     0x00C0
  54 #define CHIPSET_NV43     0x0140
  55 #define CHIPSET_NV44     0x0160
  56 #define CHIPSET_NV44A    0x0220
  57 #define CHIPSET_NV45     0x0210
  58 #define CHIPSET_NV50     0x0190
  59 #define CHIPSET_NV84     0x0400
  60 #define CHIPSET_MISC_BRIDGED  0x00F0
  61 #define CHIPSET_G70      0x0090
  62 #define CHIPSET_G71      0x0290
  63 #define CHIPSET_G72      0x01D0
  64 #define CHIPSET_G73      0x0390
  65 // integrated GeForces (6100, 6150)
  66 #define CHIPSET_C51      0x0240
  67 // variant of C51, seems based on a G70 design
  68 #define CHIPSET_C512     0x03D0
  69 #define CHIPSET_G73_BRIDGED 0x02E0
  70
  71
  72 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  73 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  74 #define SetBF(mask,value) ((value) << (0?mask))
  75 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  76 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  77 #define SetBit(n) (1<<(n))
  78 #define Set8Bits(value) ((value)&0xff)
  79
  80 #define MAX_NUM_DCB_ENTRIES 16
  81
  82 typedef enum /* matches DCB types */
  83 {
  84     OUTPUT_NONE = 4,
  85     OUTPUT_ANALOG = 0,
  86     OUTPUT_TMDS = 2,
  87     OUTPUT_LVDS = 3,
  88     OUTPUT_TV = 1,
  89 } NVOutputType;
  90
  91 typedef struct {
  92     int bitsPerPixel;
  93     int depth;
  94     int displayWidth;
  95     rgb weight;
  96     DisplayModePtr mode;
  97 } NVFBLayout;
  98
  99 typedef struct _nv_crtc_reg
 100 {
 101         unsigned char MiscOutReg;     /* */
 102         CARD8 CRTC[0xff];
 103         CARD8 CR58[0x10];
 104         CARD8 Sequencer[5];
 105         CARD8 Graphics[9];
 106         CARD8 Attribute[21];
 107         unsigned char DAC[768];       /* Internal Colorlookuptable */
 108         CARD32 cursorConfig;
 109         CARD32 crtcOwner;
 110         CARD32 gpio;
 111         CARD32 unk830;
 112         CARD32 unk834;
 113         CARD32 unk850;
 114         CARD32 unk81c;
 115         CARD32 head;
 116         uint32_t config;
 117
 118         /* These are former output regs, but are believed to be crtc related */
 119         CARD32 general;
 120         CARD32 debug_0;
 121         CARD32 debug_1;
 122         CARD32 debug_2;
 123         CARD32 unk_a20;
 124         CARD32 unk_a24;
 125         CARD32 unk_a34;
 126         CARD32 fp_horiz_regs[7];
 127         CARD32 fp_vert_regs[7];
 128         CARD32 fp_hvalid_start;
 129         CARD32 fp_hvalid_end;
 130         CARD32 fp_vvalid_start;
 131         CARD32 fp_vvalid_end;
 132         CARD32 bpp;
 133         CARD32 nv10_cursync;
 134         CARD32 fp_control;
 135         CARD32 crtcSync;
 136         CARD32 dither;
 137 } NVCrtcRegRec, *NVCrtcRegPtr;
 138
 139 typedef struct _nv_output_reg
 140 {
 141         CARD32 test_control;
 142         CARD32 unk_670;
 143
 144         CARD32 output;
 145         CARD8 TMDS[0xFF];
 146         CARD8 TMDS2[0xFF];
 147 } NVOutputRegRec, *NVOutputRegPtr;
 148
 149 typedef struct _riva_hw_state
 150 {
 151     CARD32 bpp;
 152     CARD32 width;
 153     CARD32 height;
 154     CARD32 interlace;
 155     CARD32 repaint0;
 156     CARD32 repaint1;
 157     CARD32 screen;
 158     CARD32 scale;
 159     CARD32 dither;
 160     CARD32 extra;
 161     CARD32 fifo;
 162     CARD32 pixel;
 163     CARD32 horiz;
 164     CARD32 arbitration0;
 165     CARD32 arbitration1;
 166     CARD32 pll;
 167     CARD32 pllB;
 168     CARD32 vpll;
 169     CARD32 vpll2;
 170     CARD32 vpllB;
 171     CARD32 vpll2B;
 172     CARD32 pllsel;
 173         CARD32 sel_clk;
 174         Bool crosswired;
 175         Bool db1_ratio[2];
 176         /* These vpll values are only for nv4x hardware */
 177         uint32_t vpll1_a;
 178         uint32_t vpll1_b;
 179         uint32_t vpll2_a;
 180         uint32_t vpll2_b;
 181         uint32_t reg580;
 182         uint32_t reg594;
 183     CARD32 general;
 184     CARD32 crtcOwner;
 185     CARD32 head;
 186     CARD32 head2;
 187     CARD32 config;
 188     CARD32 cursorConfig;
 189     CARD32 cursor0;
 190     CARD32 cursor1;
 191     CARD32 cursor2;
 192     CARD32 timingH;
 193     CARD32 timingV;
 194     CARD32 displayV;
 195     CARD32 crtcSync;
 196
 197     NVCrtcRegRec crtc_reg[2];
 198     NVOutputRegRec dac_reg[2];
 199 } RIVA_HW_STATE, *NVRegPtr;
 200
 201 typedef struct _nv50_crtc_reg
 202 {
 203
 204 } NV50CrtcRegRec, *NV50CrtcRegPtr;
 205
 206 typedef struct _nv50_hw_state
 207 {
 208         NV50CrtcRegRec crtc_reg[2];
 209 } NV50_HW_STATE, *NV50RegPtr;
 210
 211 typedef enum {
 212         OUTPUT_0 = (1 << 0),
 213         OUTPUT_1 = (1 << 1)
 214 } ValidRamdac;
 215
 216 typedef struct _NVOutputPrivateRec {
 217         uint8_t preferred_output;
 218         uint8_t bus;
 219         I2CBusPtr pDDCBus;
 220         NVOutputType type;
 221         int dcb_entry;
 222         CARD32 fpSyncs;
 223         CARD32 fpWidth;
 224         CARD32 fpHeight;
 225         DisplayModePtr native_mode;
 226         Bool fpdither;
 227         uint8_t scaling_mode;
 228 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 229
 230 typedef struct _MiscStartupInfo {
 231         CARD8 crtc_0_reg_52;
 232         CARD32 ramdac_0_reg_580;
 233         CARD32 ramdac_0_pllsel;
 234         CARD32 reg_c040;
 235         CARD32 sel_clk;
 236         uint32_t output[2];
 237 } MiscStartupInfo;
 238
 239 typedef enum {
 240         OUTPUT_0_SLAVED = (1 << 0),
 241         OUTPUT_1_SLAVED = (1 << 1),
 242         OUTPUT_0_LVDS = (1 << 2),
 243         OUTPUT_1_LVDS = (1 << 3),
 244         OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
 245         OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
 246 } OutputInfo;
 247
 248 struct dcb_entry {
 249         uint8_t type;
 250         uint8_t i2c_index;
 251         uint8_t heads;
 252         uint8_t bus;
 253         uint8_t location;
 254         uint8_t or;
 255         Bool duallink_possible;
 256         union {
 257                 struct {
 258                         Bool use_straps_for_mode;
 259                         Bool use_power_scripts;
 260                 } lvdsconf;
 261         };
 262 };
 263
 264 enum pll_types {
 265         VPLL1,
 266         VPLL2
 267 };
 268
 269 struct pll_lims {
 270         struct {
 271                 /* nv3x needs 32 bit values */
 272                 uint32_t minfreq;
 273                 uint32_t maxfreq;
 274                 uint32_t min_inputfreq;
 275                 uint16_t max_inputfreq;
 276
 277                 uint8_t min_m;
 278                 uint8_t max_m;
 279                 uint8_t min_n;
 280                 uint8_t max_n;
 281         } vco1, vco2;
 282
 283         uint8_t unk1c;
 284         uint8_t unk1d;
 285         uint8_t unk1e;
 286 };
 287
 288 typedef struct {
 289         uint8_t *data;
 290         unsigned int length;
 291         Bool execute;
 292
 293         uint8_t major_version, chip_version;
 294
 295         uint32_t fmaxvco, fminvco;
 296
 297         uint16_t init_script_tbls_ptr;
 298         uint16_t extra_init_script_tbl_ptr;
 299         uint16_t macro_index_tbl_ptr;
 300         uint16_t macro_tbl_ptr;
 301         uint16_t condition_tbl_ptr;
 302         uint16_t io_condition_tbl_ptr;
 303         uint16_t io_flag_condition_tbl_ptr;
 304         uint16_t init_function_tbl_ptr;
 305
 306         uint16_t pll_limit_tbl_ptr;
 307         uint16_t ram_restrict_tbl_ptr;
 308
 309         struct {
 310                 DisplayModePtr native_mode;
 311                 uint16_t lvdsmanufacturerpointer;
 312                 uint16_t xlated_entry;
 313                 Bool dual_link;
 314                 Bool if_is_18bit;
 315                 Bool BITbit1;
 316         } fp;
 317
 318         struct {
 319                 uint16_t output0_script_ptr;
 320                 uint16_t output1_script_ptr;
 321         } tmds;
 322
 323         struct {
 324                 uint8_t crt, tv, panel;
 325         } legacy_i2c_indices;
 326 } bios_t;
 327
 328 enum LVDS_script {
 329         /* Order *does* matter here */
 330         LVDS_INIT = 1,
 331         LVDS_RESET,
 332         LVDS_BACKLIGHT_ON,
 333         LVDS_BACKLIGHT_OFF,
 334         LVDS_PANEL_ON,
 335         LVDS_PANEL_OFF
 336 };
 337
 338 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 339
 340 typedef struct _NVRec *NVPtr;
 341 typedef struct _NVRec {
 342     RIVA_HW_STATE       SavedReg;
 343     RIVA_HW_STATE       ModeReg;
 344     RIVA_HW_STATE       *CurrentState;
 345         NV50_HW_STATE   NV50SavedReg;
 346         NV50_HW_STATE   NV50ModeReg;
 347     CARD32              Architecture;
 348     EntityInfoPtr       pEnt;
 349 #ifndef XSERVER_LIBPCIACCESS
 350         pciVideoPtr     PciInfo;
 351         PCITAG          PciTag;
 352 #else
 353         struct pci_device *PciInfo;
 354 #endif /* XSERVER_LIBPCIACCESS */
 355     int                 Chipset;
 356     int                 NVArch;
 357     Bool                Primary;
 358     CARD32              IOAddress;
 359     Bool cursorOn;
 360
 361     /* VRAM physical address */
 362     unsigned long       VRAMPhysical;
 363     /* Size of VRAM BAR */
 364     unsigned long       VRAMPhysicalSize;
 365     /* Accesible VRAM size (by the GPU) */
 366     unsigned long       VRAMSize;
 367     /* Accessible AGP size */
 368     unsigned long       AGPSize;
 369
 370     /* Various pinned memory regions */
 371     struct nouveau_bo * FB;
 372     struct nouveau_bo * Cursor;
 373     struct nouveau_bo * Cursor2;
 374     struct nouveau_bo * CLUT;   /* NV50 only */
 375     struct nouveau_bo * GART;
 376
 377     bios_t              VBIOS;
 378     Bool                NoAccel;
 379     Bool                HWCursor;
 380     Bool                FpScale;
 381     Bool                ShadowFB;
 382     unsigned char *     ShadowPtr;
 383     int                 ShadowPitch;
 384     CARD32              MinVClockFreqKHz;
 385     CARD32              MaxVClockFreqKHz;
 386     CARD32              CrystalFreqKHz;
 387     CARD32              RamAmountKBytes;
 388
 389     volatile CARD32 *REGS;
 390     volatile CARD32 *PCRTC0;
 391     volatile CARD32 *PCRTC1;
 392
 393         volatile CARD32 *NV50_PCRTC;
 394
 395     volatile CARD32 *PRAMDAC0;
 396     volatile CARD32 *PRAMDAC1;
 397     volatile CARD32 *PFB;
 398     volatile CARD32 *PFIFO;
 399     volatile CARD32 *PGRAPH;
 400     volatile CARD32 *PEXTDEV;
 401     volatile CARD32 *PTIMER;
 402     volatile CARD32 *PVIDEO;
 403     volatile CARD32 *PMC;
 404     volatile CARD32 *PRAMIN;
 405     volatile CARD32 *CURSOR;
 406     volatile CARD8 *PCIO0;
 407     volatile CARD8 *PCIO1;
 408     volatile CARD8 *PVIO0;
 409     volatile CARD8 *PVIO1;
 410     volatile CARD8 *PDIO0;
 411     volatile CARD8 *PDIO1;
 412     volatile CARD8 *PROM;
 413
 414
 415     volatile CARD32 *RAMHT;
 416     CARD32 pramin_free;
 417
 418     unsigned int SaveGeneration;
 419     uint8_t cur_head;
 420     ExaDriverPtr        EXADriverPtr;
 421     xf86CursorInfoPtr   CursorInfoRec;
 422     void                (*PointerMoved)(int index, int x, int y);
 423     ScreenBlockHandlerProcPtr BlockHandler;
 424     CloseScreenProcPtr  CloseScreen;
 425     int                 Rotate;
 426     NVFBLayout          CurrentLayout;
 427     /* Cursor */
 428     CARD32              curFg, curBg;
 429     CARD32              curImage[256];
 430     /* I2C / DDC */
 431     int ddc2;
 432     xf86Int10InfoPtr    pInt10;
 433     I2CBusPtr           I2C;
 434   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 435     XF86VideoAdaptorPtr overlayAdaptor;
 436     XF86VideoAdaptorPtr blitAdaptor;
 437     int                 videoKey;
 438     int                 FlatPanel;
 439     Bool                FPDither;
 440     int                 Mobile;
 441     Bool                Television;
 442         int         vtOWNER;
 443         Bool            crtc_active[2];
 444     OptionInfoPtr       Options;
 445     Bool                alphaCursor;
 446     unsigned char       DDCBase;
 447     Bool                twoHeads;
 448     Bool                twoStagePLL;
 449     Bool                fpScaler;
 450     int                 fpWidth;
 451     int                 fpHeight;
 452     CARD32              fpSyncs;
 453     Bool                usePanelTweak;
 454     int                 PanelTweak;
 455     Bool                LVDS;
 456
 457     Bool                LockedUp;
 458
 459     CARD32              currentRop;
 460
 461     Bool                WaitVSyncPossible;
 462     Bool                BlendingPossible;
 463     Bool                RandRRotation;
 464     DRIInfoPtr          pDRIInfo;
 465     drmVersionPtr       pLibDRMVersion;
 466     drmVersionPtr       pKernelDRMVersion;
 467
 468     Bool randr12_enable;
 469     CreateScreenResourcesProcPtr    CreateScreenResources;
 470
 471     I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
 472
 473         int vga_count;
 474         int dvi_d_count;
 475         int dvi_a_count;
 476         int lvds_count;
 477
 478         /* Is our secondary (analog) output not flexible (ffs(or) != 3)? */
 479         Bool restricted_mode;
 480         Bool switchable_crtc;
 481
 482         struct {
 483                 int entries;
 484                 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
 485                 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
 486                 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
 487         } dcb_table;
 488
 489         uint32_t output_info;
 490         MiscStartupInfo misc_info;
 491
 492         struct {
 493                 ORNum dac;
 494                 ORNum sor;
 495         } i2cMap[4];
 496         struct {
 497                 Bool  present;
 498                 ORNum or;
 499         } lvds;
 500
 501         /* DRM interface */
 502         struct nouveau_device *dev;
 503
 504         /* GPU context */
 505         struct nouveau_channel *chan;
 506         struct nouveau_notifier *notify0;
 507         struct nouveau_grobj *NvNull;
 508         struct nouveau_grobj *NvContextSurfaces;
 509         struct nouveau_grobj *NvContextBeta1;
 510         struct nouveau_grobj *NvContextBeta4;
 511         struct nouveau_grobj *NvImagePattern;
 512         struct nouveau_grobj *NvRop;
 513         struct nouveau_grobj *NvRectangle;
 514         struct nouveau_grobj *NvImageBlit;
 515         struct nouveau_grobj *NvScaledImage;
 516         struct nouveau_grobj *NvClipRectangle;
 517         struct nouveau_grobj *NvMemFormat;
 518         struct nouveau_grobj *NvImageFromCpu;
 519         struct nouveau_grobj *Nv2D;
 520         struct nouveau_grobj *Nv3D;
 521
 522 } NVRec;
 523
 524 typedef struct _NVCrtcPrivateRec {
 525         int head;
 526         Bool paletteEnabled;
 527         Bool deactivate;
 528 #if NOUVEAU_EXA_PIXMAPS
 529         struct nouveau_bo *shadow;
 530 #else
 531         ExaOffscreenArea *shadow;
 532 #endif /* NOUVEAU_EXA_PIXMAPS */
 533 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 534
 535 typedef struct _NV50CrtcPrivRec {
 536         int head;
 537         int pclk; /* Target pixel clock in kHz */
 538         Bool cursorVisible;
 539         Bool skipModeFixup;
 540         Bool dither;
 541 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
 542
 543 enum scaling_modes {
 544         SCALE_PANEL,
 545         SCALE_FULLSCREEN,
 546         SCALE_ASPECT,
 547         SCALE_NOSCALE,
 548         SCALE_INVALID
 549 };
 550
 551 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 552
 553 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 554
 555 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
 556 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
 557
 558 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
 559 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 560
 561 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
 562 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
 563
 564 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
 565 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
 566
 567 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
 568 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
 569
 570 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
 571 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
 572
 573 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
 574 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
 575
 576 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
 577 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
 578
 579 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
 580 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
 581
 582 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
 583 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
 584
 585 #endif /* __NV_STRUCT_H__ */