1 #ifndef __NV_STRUCT_H__
2 #define __NV_STRUCT_H__
4 #include "colormapst.h"
6 #include "xf86Cursor.h"
10 #define _XF86DRI_SERVER_
15 #include "nouveau_drm.h"
18 #error "This driver requires a DRI-enabled X server"
21 #include "nv_pcicompat.h"
23 #include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
25 #include "nouveau_crtc.h"
26 #include "nouveau_connector.h"
27 #include "nouveau_output.h"
29 #include "drmmode_display.h"
31 #define NV_ARCH_03 0x03
32 #define NV_ARCH_04 0x04
33 #define NV_ARCH_10 0x10
34 #define NV_ARCH_20 0x20
35 #define NV_ARCH_30 0x30
36 #define NV_ARCH_40 0x40
37 #define NV_ARCH_50 0x50
39 #define CHIPSET_NV03 0x0010
40 #define CHIPSET_NV04 0x0020
41 #define CHIPSET_NV10 0x0100
42 #define CHIPSET_NV11 0x0110
43 #define CHIPSET_NV15 0x0150
44 #define CHIPSET_NV17 0x0170
45 #define CHIPSET_NV18 0x0180
46 #define CHIPSET_NFORCE 0x01A0
47 #define CHIPSET_NFORCE2 0x01F0
48 #define CHIPSET_NV20 0x0200
49 #define CHIPSET_NV25 0x0250
50 #define CHIPSET_NV28 0x0280
51 #define CHIPSET_NV30 0x0300
52 #define CHIPSET_NV31 0x0310
53 #define CHIPSET_NV34 0x0320
54 #define CHIPSET_NV35 0x0330
55 #define CHIPSET_NV36 0x0340
56 #define CHIPSET_NV40 0x0040
57 #define CHIPSET_NV41 0x00C0
58 #define CHIPSET_NV43 0x0140
59 #define CHIPSET_NV44 0x0160
60 #define CHIPSET_NV44A 0x0220
61 #define CHIPSET_NV45 0x0210
62 #define CHIPSET_NV50 0x0190
63 #define CHIPSET_NV84 0x0400
64 #define CHIPSET_MISC_BRIDGED 0x00F0
65 #define CHIPSET_G70 0x0090
66 #define CHIPSET_G71 0x0290
67 #define CHIPSET_G72 0x01D0
68 #define CHIPSET_G73 0x0390
69 // integrated GeForces (6100, 6150)
70 #define CHIPSET_C51 0x0240
71 // variant of C51, seems based on a G70 design
72 #define CHIPSET_C512 0x03D0
73 #define CHIPSET_G73_BRIDGED 0x02E0
76 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
77 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
78 #define SetBF(mask,value) ((value) << (0?mask))
79 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
80 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
81 #define SetBit(n) (1<<(n))
82 #define Set8Bits(value) ((value)&0xff)
84 #define MAX_NUM_DCB_ENTRIES 16
96 bool duallink_possible;
99 bool use_straps_for_mode;
100 bool use_power_scripts;
106 {/* matches DCB types */
138 typedef struct _nv_crtc_reg
140 unsigned char MiscOutReg; /* */
143 uint8_t Sequencer[5];
145 uint8_t Attribute[21];
146 unsigned char DAC[768]; /* Internal Colorlookuptable */
147 uint32_t cursorConfig;
158 /* These are former output regs, but are believed to be crtc related */
167 uint32_t dither_regs[6];
168 uint32_t fp_horiz_regs[7];
169 uint32_t fp_vert_regs[7];
170 uint32_t nv10_cursync;
175 } NVCrtcRegRec, *NVCrtcRegPtr;
177 typedef struct _nv_output_reg
181 } NVOutputRegRec, *NVOutputRegPtr;
183 typedef struct _riva_hw_state
198 uint8_t arbitration0;
199 uint16_t arbitration1;
213 uint32_t cursorConfig;
222 NVCrtcRegRec crtc_reg[2];
223 } RIVA_HW_STATE, *NVRegPtr;
225 struct nouveau_crtc {
228 #if NOUVEAU_EXA_PIXMAPS
229 struct nouveau_bo *shadow;
231 ExaOffscreenArea *shadow;
232 #endif /* NOUVEAU_EXA_PIXMAPS */
240 } ValidOutputResource;
242 struct nouveau_encoder {
244 struct dcb_entry *dcb;
245 DisplayModePtr native_mode;
246 uint8_t scaling_mode;
248 NVOutputRegRec restore;
251 struct nouveau_connector {
254 uint16_t possible_encoders;
255 struct nouveau_encoder *detected_encoder;
256 struct nouveau_encoder *nv_encoder;
259 #define to_nouveau_connector(x) ((struct nouveau_connector *)(x)->driver_private)
260 #define to_nouveau_crtc(x) ((struct nouveau_crtc *)(x)->driver_private)
261 #define to_nouveau_encoder(x) ((struct nouveau_connector *)(x)->driver_private)->nv_encoder
263 /* changing these requires matching changes to reg tables in nv_get_clock */
264 #define MAX_PLL_TYPES 4
286 uint8_t max_log2p_bias;
296 uint8_t major_version, chip_version;
297 uint8_t feature_byte;
299 uint32_t fmaxvco, fminvco;
303 uint16_t init_script_tbls_ptr;
304 uint16_t extra_init_script_tbl_ptr;
305 uint16_t macro_index_tbl_ptr;
306 uint16_t macro_tbl_ptr;
307 uint16_t condition_tbl_ptr;
308 uint16_t io_condition_tbl_ptr;
309 uint16_t io_flag_condition_tbl_ptr;
310 uint16_t init_function_tbl_ptr;
312 uint16_t pll_limit_tbl_ptr;
313 uint16_t ram_restrict_tbl_ptr;
315 uint8_t digital_min_front_porch;
318 DisplayModePtr native_mode;
320 uint16_t lvdsmanufacturerpointer;
321 uint16_t fpxlatemanufacturertableptr;
322 uint16_t xlated_entry;
323 bool power_off_for_reset;
324 bool reset_after_pclk_change;
326 bool link_c_increment;
329 int duallink_transition_clk;
330 /* lower nibble stores PEXTDEV_BOOT_0 strap
331 * upper nibble stores xlated display strap */
336 uint16_t output0_script_ptr;
337 uint16_t output1_script_ptr;
341 uint16_t mem_init_tbl_ptr;
342 uint16_t sdr_seq_tbl_ptr;
343 uint16_t ddr_seq_tbl_ptr;
346 uint8_t crt, tv, panel;
352 /* Order *does* matter here */
361 typedef struct _NVRec *NVPtr;
362 typedef struct _NVRec {
363 RIVA_HW_STATE SavedReg;
364 RIVA_HW_STATE ModeReg;
365 uint32_t saved_vga_font[4][16384];
366 uint32_t Architecture;
368 #ifndef XSERVER_LIBPCIACCESS
372 struct pci_device *PciInfo;
373 #endif /* XSERVER_LIBPCIACCESS */
379 /* VRAM physical address */
380 unsigned long VRAMPhysical;
381 /* Size of VRAM BAR */
382 unsigned long VRAMPhysicalSize;
383 /* Accesible VRAM size (by the GPU) */
384 unsigned long VRAMSize;
385 /* Accessible AGP size */
386 unsigned long AGPSize;
388 /* Various pinned memory regions */
389 struct nouveau_bo * FB;
390 //struct nouveau_bo * FB_old; /* for KMS */
391 struct nouveau_bo * shadow[2]; /* for easy acces by exa */
392 struct nouveau_bo * Cursor;
393 struct nouveau_bo * Cursor2;
394 struct nouveau_bo * CLUT0; /* NV50 only */
395 struct nouveau_bo * CLUT1; /* NV50 only */
396 struct nouveau_bo * GART;
403 unsigned char * ShadowPtr;
405 CARD32 MinVClockFreqKHz;
406 CARD32 MaxVClockFreqKHz;
407 CARD32 CrystalFreqKHz;
408 CARD32 RamAmountKBytes;
410 volatile CARD32 *REGS;
411 volatile CARD32 *FB_BAR;
412 volatile CARD32 *PGRAPH;
413 volatile CARD32 *PRAMIN;
414 volatile CARD32 *CURSOR;
415 volatile CARD8 *PCIO0;
416 volatile CARD8 *PCIO1;
417 volatile CARD8 *PVIO0;
418 volatile CARD8 *PVIO1;
419 volatile CARD8 *PDIO0;
420 volatile CARD8 *PDIO1;
423 ExaDriverPtr EXADriverPtr;
424 xf86CursorInfoPtr CursorInfoRec;
425 ScreenBlockHandlerProcPtr BlockHandler;
426 CloseScreenProcPtr CloseScreen;
429 CARD32 curImage[256];
431 xf86Int10InfoPtr pInt10;
434 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
435 XF86VideoAdaptorPtr overlayAdaptor;
436 XF86VideoAdaptorPtr blitAdaptor;
437 XF86VideoAdaptorPtr textureAdaptor[2];
445 OptionInfoPtr Options;
447 unsigned char DDCBase;
462 Bool WaitVSyncPossible;
463 Bool BlendingPossible;
465 drmVersionPtr pLibDRMVersion;
466 drmVersionPtr pKernelDRMVersion;
471 I2CBusPtr pI2CBus[MAX_NUM_DCB_ENTRIES];
472 struct nouveau_encoder *encoders;
475 void *drmmode; /* for KMS */
480 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
481 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
482 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
485 nouveauCrtcPtr crtc[2];
486 nouveauOutputPtr output; /* this a linked list. */
487 /* Assume a connector can exist for each i2c bus. */
488 nouveauConnectorPtr connector[MAX_NUM_DCB_ENTRIES];
500 struct nouveau_device *dev;
503 struct nouveau_channel *chan;
504 struct nouveau_notifier *notify0;
505 struct nouveau_grobj *NvNull;
506 struct nouveau_grobj *NvContextSurfaces;
507 struct nouveau_grobj *NvContextBeta1;
508 struct nouveau_grobj *NvContextBeta4;
509 struct nouveau_grobj *NvImagePattern;
510 struct nouveau_grobj *NvRop;
511 struct nouveau_grobj *NvRectangle;
512 struct nouveau_grobj *NvImageBlit;
513 struct nouveau_grobj *NvScaledImage;
514 struct nouveau_grobj *NvClipRectangle;
515 struct nouveau_grobj *NvMemFormat;
516 struct nouveau_grobj *NvImageFromCpu;
517 struct nouveau_grobj *Nv2D;
518 struct nouveau_grobj *Nv3D;
519 struct nouveau_bo *tesla_scratch;
520 struct nouveau_bo *shader_mem;
521 struct nouveau_bo *xv_filtertable_mem;
524 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
526 #define NVShowHideCursor(pScrn, show) nv_show_cursor(NVPTR(pScrn), NVPTR(pScrn)->cur_head, show)
527 #define NVLockUnlock(pScrn, lock) NVLockVgaCrtc(NVPTR(pScrn), NVPTR(pScrn)->cur_head, lock)
529 #define nvReadCurVGA(pNv, reg) NVReadVgaCrtc(pNv, pNv->cur_head, reg)
530 #define nvWriteCurVGA(pNv, reg, val) NVWriteVgaCrtc(pNv, pNv->cur_head, reg, val)
532 #define nvReadCurRAMDAC(pNv, reg) NVReadRAMDAC(pNv, pNv->cur_head, reg)
533 #define nvWriteCurRAMDAC(pNv, reg, val) NVWriteRAMDAC(pNv, pNv->cur_head, reg, val)
535 #define nvReadCurCRTC(pNv, reg) NVReadCRTC(pNv, pNv->cur_head, reg)
536 #define nvWriteCurCRTC(pNv, reg, val) NVWriteCRTC(pNv, pNv->cur_head, reg, val)
538 #define nvReadFB(pNv, reg) DDXMMIOW("nvReadFB: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
539 #define nvWriteFB(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteFB: reg %08x val %08x\n", reg, val))
541 #define nvReadGRAPH(pNv, reg) DDXMMIOW("nvReadGRAPH: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
542 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteGRAPH: reg %08x val %08x\n", reg, val))
544 #define nvReadMC(pNv, reg) DDXMMIOW("nvReadMC: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
545 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteMC: reg %08x val %08x\n", reg, val))
547 #define nvReadME(pNv, reg) DDXMMIOW("nvReadME: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
548 #define nvWriteME(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteME: reg %08x val %08x\n", reg, val))
550 #define nvReadEXTDEV(pNv, reg) DDXMMIOW("nvReadEXTDEV: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
551 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteEXTDEV: reg %08x val %08x\n", reg, val))
553 #define nvReadTIMER(pNv, reg) DDXMMIOW("nvReadTIMER: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
554 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteTIMER: reg %08x val %08x\n", reg, val))
556 #define nvReadVIDEO(pNv, reg) DDXMMIOW("nvReadVIDEO: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
557 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteVIDEO: reg %08x val %08x\n", reg, val))
559 typedef struct _NVPortPrivRec {
566 Bool autopaintColorKey;
576 Bool bicubic; /* only for texture adapter */
578 struct nouveau_bo *video_mem;
581 struct nouveau_bo *TT_mem_chunk[2];
582 int currentHostBuffer;
583 struct nouveau_notifier *DMANotifier[2];
584 } NVPortPrivRec, *NVPortPrivPtr;
586 #define GET_OVERLAY_PRIVATE(pNv) \
587 (NVPortPrivPtr)((pNv)->overlayAdaptor->pPortPrivates[0].ptr)
589 #define GET_BLIT_PRIVATE(pNv) \
590 (NVPortPrivPtr)((pNv)->blitAdaptor->pPortPrivates[0].ptr)
592 #define OFF_TIMER 0x01
593 #define FREE_TIMER 0x02
594 #define CLIENT_VIDEO_ON 0x04
595 #define OFF_DELAY 500 /* milliseconds */
596 #define FREE_DELAY 5000
598 #define TIMER_MASK (OFF_TIMER | FREE_TIMER)
600 #endif /* __NV_STRUCT_H__ */