git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xf86Cursor.h"
   9 #include "xf86int10.h"
  10 #include "exa.h"
  11 #ifdef XF86DRI
  12 #define _XF86DRI_SERVER_
  13 #include "xf86drm.h"
  14 #include "dri.h"
  15 #include <stdint.h>
  16 #include "nouveau_drm.h"
  17 #include "xf86Crtc.h"
  18 #else
  19 #error "This driver requires a DRI-enabled X server"
  20 #endif
  21
  22 #include "nv50_type.h"
  23 #include "nv_pcicompat.h"
  24
  25 #include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
  26
  27 #define NV_ARCH_03  0x03
  28 #define NV_ARCH_04  0x04
  29 #define NV_ARCH_10  0x10
  30 #define NV_ARCH_20  0x20
  31 #define NV_ARCH_30  0x30
  32 #define NV_ARCH_40  0x40
  33 #define NV_ARCH_50  0x50
  34
  35 #define CHIPSET_NV03     0x0010
  36 #define CHIPSET_NV04     0x0020
  37 #define CHIPSET_NV10     0x0100
  38 #define CHIPSET_NV11     0x0110
  39 #define CHIPSET_NV15     0x0150
  40 #define CHIPSET_NV17     0x0170
  41 #define CHIPSET_NV18     0x0180
  42 #define CHIPSET_NFORCE   0x01A0
  43 #define CHIPSET_NFORCE2  0x01F0
  44 #define CHIPSET_NV20     0x0200
  45 #define CHIPSET_NV25     0x0250
  46 #define CHIPSET_NV28     0x0280
  47 #define CHIPSET_NV30     0x0300
  48 #define CHIPSET_NV31     0x0310
  49 #define CHIPSET_NV34     0x0320
  50 #define CHIPSET_NV35     0x0330
  51 #define CHIPSET_NV36     0x0340
  52 #define CHIPSET_NV40     0x0040
  53 #define CHIPSET_NV41     0x00C0
  54 #define CHIPSET_NV43     0x0140
  55 #define CHIPSET_NV44     0x0160
  56 #define CHIPSET_NV44A    0x0220
  57 #define CHIPSET_NV45     0x0210
  58 #define CHIPSET_NV50     0x0190
  59 #define CHIPSET_NV84     0x0400
  60 #define CHIPSET_MISC_BRIDGED  0x00F0
  61 #define CHIPSET_G70      0x0090
  62 #define CHIPSET_G71      0x0290
  63 #define CHIPSET_G72      0x01D0
  64 #define CHIPSET_G73      0x0390
  65 // integrated GeForces (6100, 6150)
  66 #define CHIPSET_C51      0x0240
  67 // variant of C51, seems based on a G70 design
  68 #define CHIPSET_C512     0x03D0
  69 #define CHIPSET_G73_BRIDGED 0x02E0
  70
  71
  72 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  73 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  74 #define SetBF(mask,value) ((value) << (0?mask))
  75 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  76 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  77 #define SetBit(n) (1<<(n))
  78 #define Set8Bits(value) ((value)&0xff)
  79
  80 #define MAX_NUM_DCB_ENTRIES 16
  81
  82 typedef enum /* matches DCB types */
  83 {
  84     OUTPUT_NONE = 4,
  85     OUTPUT_ANALOG = 0,
  86     OUTPUT_TMDS = 2,
  87     OUTPUT_LVDS = 3,
  88     OUTPUT_TV = 1,
  89 } NVOutputType;
  90
  91 typedef struct {
  92     int bitsPerPixel;
  93     int depth;
  94     int displayWidth;
  95     rgb weight;
  96     DisplayModePtr mode;
  97 } NVFBLayout;
  98
  99 typedef struct _nv_crtc_reg
 100 {
 101         unsigned char MiscOutReg;     /* */
 102         CARD8 CRTC[0xff];
 103         CARD8 CR58[0x10];
 104         CARD8 Sequencer[5];
 105         CARD8 Graphics[9];
 106         CARD8 Attribute[21];
 107         unsigned char DAC[768];       /* Internal Colorlookuptable */
 108         CARD32 cursorConfig;
 109         CARD32 crtcOwner;
 110         CARD32 gpio;
 111         CARD32 unk830;
 112         CARD32 unk834;
 113         CARD32 unk850;
 114         CARD32 unk81c;
 115         CARD32 head;
 116         uint32_t config;
 117
 118         /* These are former output regs, but are believed to be crtc related */
 119         CARD32 general;
 120         CARD32 debug_0;
 121         CARD32 debug_1;
 122         CARD32 debug_2;
 123         CARD32 unk_a20;
 124         CARD32 unk_a24;
 125         CARD32 unk_a34;
 126         CARD32 fp_horiz_regs[7];
 127         CARD32 fp_vert_regs[7];
 128         CARD32 fp_hvalid_start;
 129         CARD32 fp_hvalid_end;
 130         CARD32 fp_vvalid_start;
 131         CARD32 fp_vvalid_end;
 132         CARD32 bpp;
 133         CARD32 nv10_cursync;
 134         CARD32 fp_control;
 135         CARD32 crtcSync;
 136         CARD32 dither;
 137 } NVCrtcRegRec, *NVCrtcRegPtr;
 138
 139 typedef struct _nv_output_reg
 140 {
 141         CARD32 test_control;
 142         CARD32 unk_670;
 143
 144         CARD32 output;
 145         CARD8 TMDS[0xFF];
 146         CARD8 TMDS2[0xFF];
 147 } NVOutputRegRec, *NVOutputRegPtr;
 148
 149 typedef struct _riva_hw_state
 150 {
 151     CARD32 bpp;
 152     CARD32 width;
 153     CARD32 height;
 154     CARD32 interlace;
 155     CARD32 repaint0;
 156     CARD32 repaint1;
 157     CARD32 screen;
 158     CARD32 scale;
 159     CARD32 dither;
 160     CARD32 extra;
 161     CARD32 fifo;
 162     CARD32 pixel;
 163     CARD32 horiz;
 164     CARD32 arbitration0;
 165     CARD32 arbitration1;
 166     CARD32 pll;
 167     CARD32 pllB;
 168     CARD32 vpll;
 169     CARD32 vpll2;
 170     CARD32 vpllB;
 171     CARD32 vpll2B;
 172     CARD32 pllsel;
 173         CARD32 sel_clk;
 174         Bool crosswired;
 175         Bool db1_ratio[2];
 176         /* These vpll values are only for nv4x hardware */
 177         uint32_t vpll1_a;
 178         uint32_t vpll1_b;
 179         uint32_t vpll2_a;
 180         uint32_t vpll2_b;
 181         uint32_t reg580;
 182         uint32_t reg594;
 183     CARD32 general;
 184     CARD32 crtcOwner;
 185     CARD32 head;
 186     CARD32 head2;
 187     CARD32 config;
 188     CARD32 cursorConfig;
 189     CARD32 cursor0;
 190     CARD32 cursor1;
 191     CARD32 cursor2;
 192     CARD32 timingH;
 193     CARD32 timingV;
 194     CARD32 displayV;
 195     CARD32 crtcSync;
 196
 197     NVCrtcRegRec crtc_reg[2];
 198     NVOutputRegRec dac_reg[2];
 199 } RIVA_HW_STATE, *NVRegPtr;
 200
 201 typedef struct _nv50_crtc_reg
 202 {
 203
 204 } NV50CrtcRegRec, *NV50CrtcRegPtr;
 205
 206 typedef struct _nv50_hw_state
 207 {
 208         NV50CrtcRegRec crtc_reg[2];
 209 } NV50_HW_STATE, *NV50RegPtr;
 210
 211 typedef enum {
 212         OUTPUT_0 = (1 << 0),
 213         OUTPUT_1 = (1 << 1)
 214 } ValidRamdac;
 215
 216 typedef struct _NVOutputPrivateRec {
 217         uint8_t preferred_output;
 218         uint8_t bus;
 219         I2CBusPtr pDDCBus;
 220         NVOutputType type;
 221         int dcb_entry;
 222         CARD32 fpSyncs;
 223         CARD32 fpWidth;
 224         CARD32 fpHeight;
 225         DisplayModePtr native_mode;
 226         Bool fpdither;
 227         uint8_t scaling_mode;
 228 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 229
 230 typedef struct _MiscStartupInfo {
 231         CARD8 crtc_0_reg_52;
 232         CARD32 ramdac_0_reg_580;
 233         CARD32 ramdac_0_pllsel;
 234         CARD32 reg_c040;
 235         CARD32 sel_clk;
 236 } MiscStartupInfo;
 237
 238 typedef enum {
 239         OUTPUT_0_SLAVED = (1 << 0),
 240         OUTPUT_1_SLAVED = (1 << 1),
 241         OUTPUT_0_LVDS = (1 << 2),
 242         OUTPUT_1_LVDS = (1 << 3),
 243         OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
 244         OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
 245 } OutputInfo;
 246
 247 struct dcb_entry {
 248         uint8_t type;
 249         uint8_t i2c_index;
 250         uint8_t heads;
 251         uint8_t bus;
 252         uint8_t location;
 253         uint8_t or;
 254         Bool duallink_possible;
 255         union {
 256                 struct {
 257                         Bool use_straps_for_mode;
 258                         Bool use_power_scripts;
 259                 } lvdsconf;
 260         };
 261 };
 262
 263 typedef struct {
 264         uint8_t *data;
 265         unsigned int length;
 266         Bool execute;
 267
 268         uint8_t major_version;
 269
 270         uint16_t init_script_tbls_ptr;
 271         uint16_t macro_index_tbl_ptr;
 272         uint16_t macro_tbl_ptr;
 273         uint16_t condition_tbl_ptr;
 274         uint16_t io_condition_tbl_ptr;
 275         uint16_t io_flag_condition_tbl_ptr;
 276         uint16_t init_function_tbl_ptr;
 277
 278         uint16_t ram_restrict_tbl_ptr;
 279
 280         struct {
 281                 DisplayModePtr native_mode;
 282                 uint16_t lvdsmanufacturerpointer;
 283                 uint16_t xlated_entry;
 284                 Bool dual_link;
 285                 Bool if_is_18bit;
 286                 Bool BITbit1;
 287         } fp;
 288
 289         struct {
 290                 uint16_t output0_script_ptr;
 291                 uint16_t output1_script_ptr;
 292         } tmds;
 293
 294         struct {
 295                 uint8_t version;
 296                 uint8_t start;
 297                 uint8_t entry_size;
 298                 uint8_t num_entries;
 299
 300                 struct {
 301                         uint16_t minfreq;
 302                         uint16_t maxfreq;
 303                         uint16_t min_inputfreq;
 304                         uint16_t max_inputfreq;
 305
 306                         uint8_t min_m;
 307                         uint8_t max_m;
 308                         uint8_t min_n;
 309                         uint8_t max_n;
 310                 } vco1, vco2;
 311
 312                 uint8_t unk1c;
 313                 uint8_t unk1d;
 314                 uint8_t unk1e;
 315         } pll;
 316 } bios_t;
 317
 318 enum LVDS_script {
 319         /* Order *does* matter here */
 320         LVDS_INIT = 1,
 321         LVDS_RESET,
 322         LVDS_BACKLIGHT_ON,
 323         LVDS_BACKLIGHT_OFF,
 324         LVDS_PANEL_ON,
 325         LVDS_PANEL_OFF
 326 };
 327
 328 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 329
 330 typedef struct _NVRec *NVPtr;
 331 typedef struct _NVRec {
 332     RIVA_HW_STATE       SavedReg;
 333     RIVA_HW_STATE       ModeReg;
 334     RIVA_HW_STATE       *CurrentState;
 335         NV50_HW_STATE   NV50SavedReg;
 336         NV50_HW_STATE   NV50ModeReg;
 337     CARD32              Architecture;
 338     EntityInfoPtr       pEnt;
 339 #ifndef XSERVER_LIBPCIACCESS
 340         pciVideoPtr     PciInfo;
 341         PCITAG          PciTag;
 342 #else
 343         struct pci_device *PciInfo;
 344 #endif /* XSERVER_LIBPCIACCESS */
 345     int                 Chipset;
 346     int                 NVArch;
 347     Bool                Primary;
 348     CARD32              IOAddress;
 349     Bool cursorOn;
 350
 351     /* VRAM physical address */
 352     unsigned long       VRAMPhysical;
 353     /* Size of VRAM BAR */
 354     unsigned long       VRAMPhysicalSize;
 355     /* Accesible VRAM size (by the GPU) */
 356     unsigned long       VRAMSize;
 357     /* Accessible AGP size */
 358     unsigned long       AGPSize;
 359
 360     /* Various pinned memory regions */
 361     struct nouveau_bo * FB;
 362     struct nouveau_bo * Cursor;
 363     struct nouveau_bo * Cursor2;
 364     struct nouveau_bo * CLUT;   /* NV50 only */
 365     struct nouveau_bo * GART;
 366
 367     bios_t              VBIOS;
 368     Bool                NoAccel;
 369     Bool                HWCursor;
 370     Bool                FpScale;
 371     Bool                ShadowFB;
 372     unsigned char *     ShadowPtr;
 373     int                 ShadowPitch;
 374     CARD32              MinVClockFreqKHz;
 375     CARD32              MaxVClockFreqKHz;
 376     CARD32              CrystalFreqKHz;
 377     CARD32              RamAmountKBytes;
 378
 379     volatile CARD32 *REGS;
 380     volatile CARD32 *PCRTC0;
 381     volatile CARD32 *PCRTC1;
 382
 383         volatile CARD32 *NV50_PCRTC;
 384
 385     volatile CARD32 *PRAMDAC0;
 386     volatile CARD32 *PRAMDAC1;
 387     volatile CARD32 *PFB;
 388     volatile CARD32 *PFIFO;
 389     volatile CARD32 *PGRAPH;
 390     volatile CARD32 *PEXTDEV;
 391     volatile CARD32 *PTIMER;
 392     volatile CARD32 *PVIDEO;
 393     volatile CARD32 *PMC;
 394     volatile CARD32 *PRAMIN;
 395     volatile CARD32 *CURSOR;
 396     volatile CARD8 *PCIO0;
 397     volatile CARD8 *PCIO1;
 398     volatile CARD8 *PVIO0;
 399     volatile CARD8 *PVIO1;
 400     volatile CARD8 *PDIO0;
 401     volatile CARD8 *PDIO1;
 402     volatile CARD8 *PROM;
 403
 404
 405     volatile CARD32 *RAMHT;
 406     CARD32 pramin_free;
 407
 408     unsigned int SaveGeneration;
 409     uint8_t cur_head;
 410     ExaDriverPtr        EXADriverPtr;
 411     xf86CursorInfoPtr   CursorInfoRec;
 412     void                (*PointerMoved)(int index, int x, int y);
 413     ScreenBlockHandlerProcPtr BlockHandler;
 414     CloseScreenProcPtr  CloseScreen;
 415     int                 Rotate;
 416     NVFBLayout          CurrentLayout;
 417     /* Cursor */
 418     CARD32              curFg, curBg;
 419     CARD32              curImage[256];
 420     /* I2C / DDC */
 421     int ddc2;
 422     xf86Int10InfoPtr    pInt10;
 423     I2CBusPtr           I2C;
 424   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 425     XF86VideoAdaptorPtr overlayAdaptor;
 426     XF86VideoAdaptorPtr blitAdaptor;
 427     int                 videoKey;
 428     int                 FlatPanel;
 429     Bool                FPDither;
 430     int                 Mobile;
 431     Bool                Television;
 432         int         vtOWNER;
 433         Bool            crtc_active[2];
 434         Bool            ramdac_active[2];
 435     OptionInfoPtr       Options;
 436     Bool                alphaCursor;
 437     unsigned char       DDCBase;
 438     Bool                twoHeads;
 439     Bool                twoStagePLL;
 440     Bool                fpScaler;
 441     int                 fpWidth;
 442     int                 fpHeight;
 443     CARD32              fpSyncs;
 444     Bool                usePanelTweak;
 445     int                 PanelTweak;
 446     Bool                LVDS;
 447
 448     Bool                LockedUp;
 449
 450     CARD32              currentRop;
 451
 452     Bool                WaitVSyncPossible;
 453     Bool                BlendingPossible;
 454     Bool                RandRRotation;
 455     DRIInfoPtr          pDRIInfo;
 456     drmVersionPtr       pLibDRMVersion;
 457     drmVersionPtr       pKernelDRMVersion;
 458
 459     Bool randr12_enable;
 460     CreateScreenResourcesProcPtr    CreateScreenResources;
 461
 462     I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
 463
 464         int vga_count;
 465         int dvi_d_count;
 466         int dvi_a_count;
 467         int lvds_count;
 468
 469         /* Is our secondary (analog) output not flexible (ffs(or) != 3)? */
 470         Bool restricted_mode;
 471
 472         struct {
 473                 int entries;
 474                 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
 475                 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
 476                 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
 477         } dcb_table;
 478
 479         uint32_t output_info;
 480         MiscStartupInfo misc_info;
 481
 482         struct {
 483                 ORNum dac;
 484                 ORNum sor;
 485         } i2cMap[4];
 486         struct {
 487                 Bool  present;
 488                 ORNum or;
 489         } lvds;
 490
 491         /* DRM interface */
 492         struct nouveau_device *dev;
 493
 494         /* GPU context */
 495         struct nouveau_channel *chan;
 496         struct nouveau_notifier *notify0;
 497         struct nouveau_grobj *NvNull;
 498         struct nouveau_grobj *NvContextSurfaces;
 499         struct nouveau_grobj *NvContextBeta1;
 500         struct nouveau_grobj *NvContextBeta4;
 501         struct nouveau_grobj *NvImagePattern;
 502         struct nouveau_grobj *NvRop;
 503         struct nouveau_grobj *NvRectangle;
 504         struct nouveau_grobj *NvImageBlit;
 505         struct nouveau_grobj *NvScaledImage;
 506         struct nouveau_grobj *NvClipRectangle;
 507         struct nouveau_grobj *NvMemFormat;
 508         struct nouveau_grobj *NvImageFromCpu;
 509         struct nouveau_grobj *Nv2D;
 510         struct nouveau_grobj *Nv3D;
 511
 512 } NVRec;
 513
 514 typedef struct _NVCrtcPrivateRec {
 515         int crtc;
 516         int head;
 517         Bool paletteEnabled;
 518         Bool deactivate;
 519 #if NOUVEAU_EXA_PIXMAPS
 520         struct nouveau_bo *shadow;
 521 #else
 522         ExaOffscreenArea *shadow;
 523 #endif /* NOUVEAU_EXA_PIXMAPS */
 524 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 525
 526 typedef struct _NV50CrtcPrivRec {
 527         int head;
 528         int pclk; /* Target pixel clock in kHz */
 529         Bool cursorVisible;
 530         Bool skipModeFixup;
 531         Bool dither;
 532 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
 533
 534 enum scaling_modes {
 535         SCALE_PANEL,
 536         SCALE_FULLSCREEN,
 537         SCALE_ASPECT,
 538         SCALE_NOSCALE,
 539         SCALE_INVALID
 540 };
 541
 542 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 543
 544 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 545
 546 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
 547 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
 548
 549 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
 550 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 551
 552 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
 553 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
 554
 555 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
 556 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
 557
 558 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
 559 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
 560
 561 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
 562 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
 563
 564 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
 565 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
 566
 567 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
 568 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
 569
 570 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
 571 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
 572
 573 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
 574 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
 575
 576 #endif /* __NV_STRUCT_H__ */