1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
3 #ifndef __NV_STRUCT_H__
4 #define __NV_STRUCT_H__
6 #include "colormapst.h"
9 #include "xf86Cursor.h"
10 #include "xf86int10.h"
13 #define _XF86DRI_SERVER_
17 #include "nouveau_drm.h"
19 #error "This driver requires a DRI-enabled X server"
22 #define NV_ARCH_03 0x03
23 #define NV_ARCH_04 0x04
24 #define NV_ARCH_10 0x10
25 #define NV_ARCH_20 0x20
26 #define NV_ARCH_30 0x30
27 #define NV_ARCH_40 0x40
29 #define CHIPSET_NV03 0x0010
30 #define CHIPSET_NV04 0x0020
31 #define CHIPSET_NV10 0x0100
32 #define CHIPSET_NV11 0x0110
33 #define CHIPSET_NV15 0x0150
34 #define CHIPSET_NV17 0x0170
35 #define CHIPSET_NV18 0x0180
36 #define CHIPSET_NFORCE 0x01A0
37 #define CHIPSET_NFORCE2 0x01F0
38 #define CHIPSET_NV20 0x0200
39 #define CHIPSET_NV25 0x0250
40 #define CHIPSET_NV28 0x0280
41 #define CHIPSET_NV30 0x0300
42 #define CHIPSET_NV31 0x0310
43 #define CHIPSET_NV34 0x0320
44 #define CHIPSET_NV35 0x0330
45 #define CHIPSET_NV36 0x0340
46 #define CHIPSET_NV40 0x0040
47 #define CHIPSET_NV41 0x00C0
48 #define CHIPSET_NV43 0x0140
49 #define CHIPSET_NV44 0x0160
50 #define CHIPSET_NV44A 0x0220
51 #define CHIPSET_NV45 0x0210
52 #define CHIPSET_MISC_BRIDGED 0x00F0
53 #define CHIPSET_G70 0x0090
54 #define CHIPSET_G71 0x0290
55 #define CHIPSET_G72 0x01D0
56 #define CHIPSET_G73 0x0390
57 // integrated GeForces (6100, 6150)
58 #define CHIPSET_C51 0x0240
59 // variant of C51, seems based on a G70 design
60 #define CHIPSET_C512 0x03D0
61 #define CHIPSET_G73_BRIDGED 0x02E0
64 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
65 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
66 #define SetBF(mask,value) ((value) << (0?mask))
67 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
68 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
69 #define SetBit(n) (1<<(n))
70 #define Set8Bits(value) ((value)&0xff)
80 typedef struct _riva_hw_state
117 } RIVA_HW_STATE, *NVRegPtr;
126 typedef struct _NVRec *NVPtr;
127 typedef struct _NVRec {
128 RIVA_HW_STATE SavedReg;
129 RIVA_HW_STATE ModeReg;
130 RIVA_HW_STATE *CurrentState;
139 unsigned long VRAMPhysical;
140 unsigned long VRAMPhysicalSize;
143 NVAllocRec * ScratchBuffer;
144 NVAllocRec * AGPScratch;
149 unsigned char * ShadowPtr;
151 CARD32 MinVClockFreqKHz;
152 CARD32 MaxVClockFreqKHz;
153 CARD32 CrystalFreqKHz;
154 CARD32 RamAmountKBytes;
157 volatile CARD32 *REGS;
158 volatile CARD32 *PCRTC0;
159 volatile CARD32 *PCRTC1;
161 volatile CARD32 *PRAMDAC0;
162 volatile CARD32 *PRAMDAC1;
163 volatile CARD32 *PFB;
164 volatile CARD32 *PFIFO;
165 volatile CARD32 *PGRAPH;
166 volatile CARD32 *PEXTDEV;
167 volatile CARD32 *PTIMER;
168 volatile CARD32 *PMC;
169 volatile CARD32 *PRAMIN;
170 volatile CARD32 *FIFO;
171 volatile CARD32 *CURSOR;
172 volatile CARD8 *PCIO0;
173 volatile CARD8 *PCIO1;
174 volatile CARD8 *PVIO;
175 volatile CARD8 *PDIO0;
176 volatile CARD8 *PDIO1;
177 volatile CARD8 *PROM;
180 volatile CARD32 *RAMHT;
184 XAAInfoRecPtr AccelInfoRec;
185 ExaDriverPtr EXADriverPtr;
187 xf86CursorInfoPtr CursorInfoRec;
188 void (*PointerMoved)(int index, int x, int y);
189 ScreenBlockHandlerProcPtr BlockHandler;
190 CloseScreenProcPtr CloseScreen;
192 NVFBLayout CurrentLayout;
195 CARD32 curImage[256];
198 xf86Int10InfoPtr pInt;
199 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
200 void (*DMAKickoffCallback)(NVPtr pNv);
201 XF86VideoAdaptorPtr overlayAdaptor;
202 XF86VideoAdaptorPtr blitAdaptor;
209 OptionInfoPtr Options;
211 unsigned char DDCBase;
226 drm_nouveau_fifo_init_t fifo;
236 Bool WaitVSyncPossible;
237 Bool BlendingPossible;
244 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
246 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
247 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
249 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
250 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
252 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
253 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
255 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
256 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
258 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
259 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
261 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
262 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
264 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
265 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
267 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
268 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
270 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
271 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
273 #endif /* __NV_STRUCT_H__ */