git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xf86Cursor.h"
   9 #include "xf86int10.h"
  10 #include "exa.h"
  11 #ifdef XF86DRI
  12 #define _XF86DRI_SERVER_
  13 #include "xf86drm.h"
  14 #include "dri.h"
  15 #include <stdbool.h>
  16 #include <stdint.h>
  17 #include "nouveau_drm.h"
  18 #include "xf86Crtc.h"
  19 #else
  20 #error "This driver requires a DRI-enabled X server"
  21 #endif
  22
  23 #include "nv50_type.h"
  24 #include "nv_pcicompat.h"
  25
  26 #include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
  27
  28 #define NV_ARCH_03  0x03
  29 #define NV_ARCH_04  0x04
  30 #define NV_ARCH_10  0x10
  31 #define NV_ARCH_20  0x20
  32 #define NV_ARCH_30  0x30
  33 #define NV_ARCH_40  0x40
  34 #define NV_ARCH_50  0x50
  35
  36 #define CHIPSET_NV03     0x0010
  37 #define CHIPSET_NV04     0x0020
  38 #define CHIPSET_NV10     0x0100
  39 #define CHIPSET_NV11     0x0110
  40 #define CHIPSET_NV15     0x0150
  41 #define CHIPSET_NV17     0x0170
  42 #define CHIPSET_NV18     0x0180
  43 #define CHIPSET_NFORCE   0x01A0
  44 #define CHIPSET_NFORCE2  0x01F0
  45 #define CHIPSET_NV20     0x0200
  46 #define CHIPSET_NV25     0x0250
  47 #define CHIPSET_NV28     0x0280
  48 #define CHIPSET_NV30     0x0300
  49 #define CHIPSET_NV31     0x0310
  50 #define CHIPSET_NV34     0x0320
  51 #define CHIPSET_NV35     0x0330
  52 #define CHIPSET_NV36     0x0340
  53 #define CHIPSET_NV40     0x0040
  54 #define CHIPSET_NV41     0x00C0
  55 #define CHIPSET_NV43     0x0140
  56 #define CHIPSET_NV44     0x0160
  57 #define CHIPSET_NV44A    0x0220
  58 #define CHIPSET_NV45     0x0210
  59 #define CHIPSET_NV50     0x0190
  60 #define CHIPSET_NV84     0x0400
  61 #define CHIPSET_MISC_BRIDGED  0x00F0
  62 #define CHIPSET_G70      0x0090
  63 #define CHIPSET_G71      0x0290
  64 #define CHIPSET_G72      0x01D0
  65 #define CHIPSET_G73      0x0390
  66 // integrated GeForces (6100, 6150)
  67 #define CHIPSET_C51      0x0240
  68 // variant of C51, seems based on a G70 design
  69 #define CHIPSET_C512     0x03D0
  70 #define CHIPSET_G73_BRIDGED 0x02E0
  71
  72
  73 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  74 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  75 #define SetBF(mask,value) ((value) << (0?mask))
  76 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  77 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  78 #define SetBit(n) (1<<(n))
  79 #define Set8Bits(value) ((value)&0xff)
  80
  81 #define MAX_NUM_DCB_ENTRIES 16
  82
  83 typedef enum /* matches DCB types */
  84 {
  85     OUTPUT_NONE = 4,
  86     OUTPUT_ANALOG = 0,
  87     OUTPUT_TMDS = 2,
  88     OUTPUT_LVDS = 3,
  89     OUTPUT_TV = 1,
  90 } NVOutputType;
  91
  92 typedef struct _nv_crtc_reg
  93 {
  94         unsigned char MiscOutReg;     /* */
  95         uint8_t CRTC[0xff];
  96         uint8_t CR58[0x10];
  97         uint8_t Sequencer[5];
  98         uint8_t Graphics[9];
  99         uint8_t Attribute[21];
 100         unsigned char DAC[768];       /* Internal Colorlookuptable */
 101         uint32_t cursorConfig;
 102         uint32_t crtcOwner;
 103         uint32_t gpio;
 104         uint32_t gpio_ext;
 105         uint32_t unk830;
 106         uint32_t unk834;
 107         uint32_t unk850;
 108         uint32_t head;
 109         uint32_t config;
 110
 111         /* These are former output regs, but are believed to be crtc related */
 112         uint32_t general;
 113         uint32_t debug_0[2];
 114         uint32_t debug_1;
 115         uint32_t debug_2;
 116         uint32_t unk_a20;
 117         uint32_t unk_a24;
 118         uint32_t unk_a34;
 119         uint32_t dither_regs[6];
 120         uint32_t fp_horiz_regs[7];
 121         uint32_t fp_vert_regs[7];
 122         uint32_t fp_hvalid_start;
 123         uint32_t fp_hvalid_end;
 124         uint32_t fp_vvalid_start;
 125         uint32_t fp_vvalid_end;
 126         uint32_t bpp;
 127         uint32_t nv10_cursync;
 128         uint32_t fp_control[2];
 129         uint32_t crtcSync;
 130         uint32_t dither;
 131 } NVCrtcRegRec, *NVCrtcRegPtr;
 132
 133 typedef struct _nv_output_reg
 134 {
 135         uint32_t output;
 136         uint8_t TMDS[0xFF];
 137 } NVOutputRegRec, *NVOutputRegPtr;
 138
 139 typedef struct _riva_hw_state
 140 {
 141         uint32_t bpp;
 142         uint32_t width;
 143         uint32_t height;
 144         uint32_t interlace;
 145         uint32_t repaint0;
 146         uint32_t repaint1;
 147         uint32_t screen;
 148         uint32_t scale;
 149         uint32_t dither;
 150         uint32_t extra;
 151         uint32_t fifo;
 152         uint32_t pixel;
 153         uint32_t horiz;
 154         uint32_t arbitration0;
 155         uint32_t arbitration1;
 156         uint32_t pll;
 157         uint32_t pllB;
 158         uint32_t vpll;
 159         uint32_t vpll2;
 160         uint32_t vpllB;
 161         uint32_t vpll2B;
 162         uint32_t pllsel;
 163         uint32_t sel_clk;
 164         Bool crosswired;
 165         Bool vpll_changed[2];
 166         /* These vpll values are only for nv4x hardware */
 167         uint32_t vpll1_a;
 168         uint32_t vpll1_b;
 169         uint32_t vpll2_a;
 170         uint32_t vpll2_b;
 171         uint32_t reg580;
 172         uint32_t general;
 173         uint32_t crtcOwner;
 174         uint32_t head;
 175         uint32_t head2;
 176         uint32_t config;
 177         uint32_t cursorConfig;
 178         uint32_t cursor0;
 179         uint32_t cursor1;
 180         uint32_t cursor2;
 181         uint32_t timingH;
 182         uint32_t timingV;
 183         uint32_t displayV;
 184         uint32_t crtcSync;
 185
 186         NVCrtcRegRec crtc_reg[2];
 187         NVOutputRegRec dac_reg[2];
 188 } RIVA_HW_STATE, *NVRegPtr;
 189
 190 typedef struct _NVCrtcPrivateRec {
 191         int head;
 192         uint8_t last_dpms;
 193         Bool cursorVisible;
 194         Bool ditherEnabled;
 195         Bool skipModeFixup; /* NV50 only */
 196         int pclk; /* Pixel clock in kHz */ /* NV50 only */
 197 #if NOUVEAU_EXA_PIXMAPS
 198         struct nouveau_bo *shadow;
 199 #else
 200         ExaOffscreenArea *shadow;
 201 #endif /* NOUVEAU_EXA_PIXMAPS */
 202 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 203
 204 typedef enum {
 205         OUTPUT_0 = (1 << 0),
 206         OUTPUT_1 = (1 << 1)
 207 } ValidOutputResource;
 208
 209 typedef struct _NVOutputPrivateRec {
 210         uint8_t preferred_output;
 211         uint8_t output_resource;
 212         uint8_t last_dpms;
 213         I2CBusPtr pDDCBus;
 214         NVOutputType type;
 215         int dcb_entry;
 216         uint32_t fpWidth;
 217         uint32_t fpHeight;
 218         DisplayModePtr native_mode;
 219         uint8_t scaling_mode;
 220         uint32_t restore_output;
 221 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 222
 223 typedef struct _MiscStartupInfo {
 224         uint8_t crtc_reg_52[2];
 225         uint32_t ramdac_0_reg_580;
 226         uint32_t ramdac_0_pllsel;
 227         uint32_t ramdac_general_control[2];
 228         uint32_t reg_c040;
 229         uint32_t sel_clk;
 230         uint32_t output[2];
 231 } MiscStartupInfo;
 232
 233 struct dcb_entry {
 234         uint8_t type;
 235         uint8_t i2c_index;
 236         uint8_t heads;
 237         uint8_t bus;
 238         uint8_t location;
 239         uint8_t or;
 240         Bool duallink_possible;
 241         union {
 242                 struct {
 243                         Bool use_straps_for_mode;
 244                         Bool use_power_scripts;
 245                 } lvdsconf;
 246         };
 247 };
 248
 249 #define MAX_PLL_TYPES   2
 250 enum pll_types {
 251         VPLL1,
 252         VPLL2
 253 };
 254
 255 struct pll_lims {
 256         struct {
 257                 int minfreq;
 258                 int maxfreq;
 259                 int min_inputfreq;
 260                 int max_inputfreq;
 261
 262                 uint8_t min_m;
 263                 uint8_t max_m;
 264                 uint8_t min_n;
 265                 uint8_t max_n;
 266         } vco1, vco2;
 267
 268         uint8_t unk1c;
 269         uint8_t max_log2p_bias;
 270         uint8_t log2p_bias;
 271         int refclk;
 272 };
 273
 274 typedef struct {
 275         uint8_t *data;
 276         unsigned int length;
 277         Bool execute;
 278
 279         uint8_t major_version, chip_version;
 280         uint8_t feature_byte;
 281
 282         uint32_t fmaxvco, fminvco;
 283
 284         uint32_t dactestval;
 285
 286         uint16_t init_script_tbls_ptr;
 287         uint16_t extra_init_script_tbl_ptr;
 288         uint16_t macro_index_tbl_ptr;
 289         uint16_t macro_tbl_ptr;
 290         uint16_t condition_tbl_ptr;
 291         uint16_t io_condition_tbl_ptr;
 292         uint16_t io_flag_condition_tbl_ptr;
 293         uint16_t init_function_tbl_ptr;
 294
 295         uint16_t pll_limit_tbl_ptr;
 296         uint16_t ram_restrict_tbl_ptr;
 297
 298         struct {
 299                 DisplayModePtr native_mode;
 300                 uint8_t *edid;
 301                 uint16_t lvdsmanufacturerpointer;
 302                 uint16_t xlated_entry;
 303                 bool reset_after_pclk_change;
 304                 bool dual_link;
 305                 bool link_c_increment;
 306                 bool if_is_24bit;
 307                 bool BITbit1;
 308                 int duallink_transition_clk;
 309                 /* lower nibble stores PEXTDEV_BOOT_0 strap
 310                  * upper nibble stores xlated display strap */
 311                 uint8_t strapping;
 312         } fp;
 313
 314         struct {
 315                 uint16_t output0_script_ptr;
 316                 uint16_t output1_script_ptr;
 317         } tmds;
 318
 319         struct {
 320                 uint16_t mem_init_tbl_ptr;
 321                 uint16_t sdr_seq_tbl_ptr;
 322                 uint16_t ddr_seq_tbl_ptr;
 323
 324                 struct {
 325                         uint8_t crt, tv, panel;
 326                 } i2c_indices;
 327         } legacy;
 328 } bios_t;
 329
 330 enum LVDS_script {
 331         /* Order *does* matter here */
 332         LVDS_INIT = 1,
 333         LVDS_RESET,
 334         LVDS_BACKLIGHT_ON,
 335         LVDS_BACKLIGHT_OFF,
 336         LVDS_PANEL_ON,
 337         LVDS_PANEL_OFF
 338 };
 339
 340 typedef struct {
 341         Bool vga_mode;
 342         uint8_t depth; /* mode related */
 343         uint8_t bpp; /* pitch related */
 344         uint16_t x_res;
 345         uint16_t y_res;
 346         Bool enabled;
 347         uint32_t fb_start;
 348 } NVConsoleMode;
 349
 350 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 351
 352 typedef struct _NVRec *NVPtr;
 353 typedef struct _NVRec {
 354     RIVA_HW_STATE       SavedReg;
 355     RIVA_HW_STATE       ModeReg;
 356     uint32_t              Architecture;
 357     EntityInfoPtr       pEnt;
 358 #ifndef XSERVER_LIBPCIACCESS
 359         pciVideoPtr     PciInfo;
 360         PCITAG          PciTag;
 361 #else
 362         struct pci_device *PciInfo;
 363 #endif /* XSERVER_LIBPCIACCESS */
 364     int                 Chipset;
 365     int                 NVArch;
 366     Bool                Primary;
 367     CARD32              IOAddress;
 368
 369     /* VRAM physical address */
 370     unsigned long       VRAMPhysical;
 371     /* Size of VRAM BAR */
 372     unsigned long       VRAMPhysicalSize;
 373     /* Accesible VRAM size (by the GPU) */
 374     unsigned long       VRAMSize;
 375     /* Accessible AGP size */
 376     unsigned long       AGPSize;
 377
 378     /* Various pinned memory regions */
 379     struct nouveau_bo * FB;
 380     struct nouveau_bo * Cursor;
 381     struct nouveau_bo * Cursor2;
 382     struct nouveau_bo * CLUT;   /* NV50 only */
 383     struct nouveau_bo * GART;
 384
 385     bios_t              VBIOS;
 386     Bool                NoAccel;
 387     Bool                HWCursor;
 388     Bool                FpScale;
 389     Bool                ShadowFB;
 390     unsigned char *     ShadowPtr;
 391     int                 ShadowPitch;
 392     CARD32              MinVClockFreqKHz;
 393     CARD32              MaxVClockFreqKHz;
 394     CARD32              CrystalFreqKHz;
 395     CARD32              RamAmountKBytes;
 396
 397     volatile CARD32 *REGS;
 398         volatile CARD32 *NV50_PCRTC;
 399     volatile CARD32 *PGRAPH;
 400     volatile CARD32 *PRAMIN;
 401     volatile CARD32 *CURSOR;
 402     volatile CARD8 *PCIO0;
 403     volatile CARD8 *PCIO1;
 404     volatile CARD8 *PVIO0;
 405     volatile CARD8 *PVIO1;
 406     volatile CARD8 *PDIO0;
 407     volatile CARD8 *PDIO1;
 408
 409     unsigned int SaveGeneration;
 410     uint8_t cur_head;
 411     ExaDriverPtr        EXADriverPtr;
 412     xf86CursorInfoPtr   CursorInfoRec;
 413     void                (*PointerMoved)(int index, int x, int y);
 414     ScreenBlockHandlerProcPtr BlockHandler;
 415     CloseScreenProcPtr  CloseScreen;
 416     int                 Rotate;
 417     /* Cursor */
 418     CARD32              curFg, curBg;
 419     CARD32              curImage[256];
 420     /* I2C / DDC */
 421     xf86Int10InfoPtr    pInt10;
 422     I2CBusPtr           I2C;
 423   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 424     XF86VideoAdaptorPtr overlayAdaptor;
 425     XF86VideoAdaptorPtr blitAdaptor;
 426     XF86VideoAdaptorPtr textureAdaptor[2];
 427     int                 videoKey;
 428     int                 FlatPanel;
 429     Bool                FPDither;
 430     int                 Mobile;
 431     Bool                Television;
 432         int         vtOWNER;
 433         Bool            crtc_active[2];
 434     OptionInfoPtr       Options;
 435     Bool                alphaCursor;
 436     unsigned char       DDCBase;
 437     Bool                twoHeads;
 438     Bool                twoStagePLL;
 439     Bool                fpScaler;
 440     int                 fpWidth;
 441     int                 fpHeight;
 442     CARD32              fpSyncs;
 443     Bool                usePanelTweak;
 444     int                 PanelTweak;
 445     Bool                LVDS;
 446
 447     Bool                LockedUp;
 448
 449     CARD32              currentRop;
 450
 451     Bool                WaitVSyncPossible;
 452     Bool                BlendingPossible;
 453     Bool                RandRRotation;
 454     DRIInfoPtr          pDRIInfo;
 455     drmVersionPtr       pLibDRMVersion;
 456     drmVersionPtr       pKernelDRMVersion;
 457
 458         Bool randr12_enable;
 459         Bool new_restore;
 460
 461         I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
 462
 463         uint8_t fp_regs_owner[2];
 464
 465         struct {
 466                 int entries;
 467                 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
 468                 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
 469                 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
 470         } dcb_table;
 471
 472         MiscStartupInfo misc_info;
 473         NVConsoleMode console_mode[2];
 474
 475         struct {
 476                 ORNum dac;
 477                 ORNum sor;
 478         } i2cMap[4];
 479         struct {
 480                 Bool  present;
 481                 ORNum or;
 482         } lvds;
 483
 484         /* DRM interface */
 485         struct nouveau_device *dev;
 486
 487         /* GPU context */
 488         struct nouveau_channel *chan;
 489         struct nouveau_notifier *notify0;
 490         struct nouveau_grobj *NvNull;
 491         struct nouveau_grobj *NvContextSurfaces;
 492         struct nouveau_grobj *NvContextBeta1;
 493         struct nouveau_grobj *NvContextBeta4;
 494         struct nouveau_grobj *NvImagePattern;
 495         struct nouveau_grobj *NvRop;
 496         struct nouveau_grobj *NvRectangle;
 497         struct nouveau_grobj *NvImageBlit;
 498         struct nouveau_grobj *NvScaledImage;
 499         struct nouveau_grobj *NvClipRectangle;
 500         struct nouveau_grobj *NvMemFormat;
 501         struct nouveau_grobj *NvImageFromCpu;
 502         struct nouveau_grobj *Nv2D;
 503         struct nouveau_grobj *Nv3D;
 504
 505 } NVRec;
 506
 507 enum scaling_modes {
 508         SCALE_PANEL,
 509         SCALE_FULLSCREEN,
 510         SCALE_ASPECT,
 511         SCALE_NOSCALE,
 512         SCALE_INVALID
 513 };
 514
 515 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 516
 517 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 518
 519 #define NVShowHideCursor(pScrn, show) do {                                                      \
 520         NVPtr pNv = NVPTR(pScrn);                                                                               \
 521         nv_crtc_show_hide_cursor(pScrn, pNv->cur_head, show);                           \
 522 } while(0)
 523
 524 #define NVLockUnlock(pScrn, lock) NVLockVgaCrtc(NVPTR(pScrn), NVPTR(pScrn)->cur_head, lock)
 525
 526 #define nvReadCurVGA(pNv, reg) NVReadVgaCrtc(pNv, pNv->cur_head, reg)
 527 #define nvWriteCurVGA(pNv, reg, val) NVWriteVgaCrtc(pNv, pNv->cur_head, reg, val)
 528
 529 #define nvReadCurRAMDAC(pNv, reg) NVReadRAMDAC(pNv, pNv->cur_head, reg)
 530 #define nvWriteCurRAMDAC(pNv, reg, val) NVWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 531
 532 #define nvReadCurCRTC(pNv, reg) NVReadCRTC(pNv, pNv->cur_head, reg)
 533 #define nvWriteCurCRTC(pNv, reg, val) NVWriteCRTC(pNv, pNv->cur_head, reg, val)
 534
 535 #define nvReadFB(pNv, reg) DDXMMIOW("nvReadFB: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 536 #define nvWriteFB(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteFB: reg %08x val %08x\n", reg, val))
 537
 538 #define nvReadGRAPH(pNv, reg) DDXMMIOW("nvReadGRAPH: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 539 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteGRAPH: reg %08x val %08x\n", reg, val))
 540
 541 #define nvReadMC(pNv, reg) DDXMMIOW("nvReadMC: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 542 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteMC: reg %08x val %08x\n", reg, val))
 543
 544 #define nvReadME(pNv, reg) DDXMMIOW("nvReadME: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 545 #define nvWriteME(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteME: reg %08x val %08x\n", reg, val))
 546
 547 #define nvReadEXTDEV(pNv, reg) DDXMMIOW("nvReadEXTDEV: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 548 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteEXTDEV: reg %08x val %08x\n", reg, val))
 549
 550 #define nvReadTIMER(pNv, reg) DDXMMIOW("nvReadTIMER: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 551 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteTIMER: reg %08x val %08x\n", reg, val))
 552
 553 #define nvReadVIDEO(pNv, reg) DDXMMIOW("nvReadVIDEO: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
 554 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteVIDEO: reg %08x val %08x\n", reg, val))
 555
 556 typedef struct _NVPortPrivRec {
 557         short           brightness;
 558         short           contrast;
 559         short           saturation;
 560         short           hue;
 561         RegionRec       clip;
 562         CARD32          colorKey;
 563         Bool            autopaintColorKey;
 564         Bool            doubleBuffer;
 565         CARD32          videoStatus;
 566         int             currentBuffer;
 567         Time            videoTime;
 568         int             overlayCRTC;
 569         Bool            grabbedByV4L;
 570         Bool            iturbt_709;
 571         Bool            blitter;
 572         Bool            texture;
 573         Bool            bicubic; /* only for texture adapter */
 574         Bool            SyncToVBlank;
 575         struct nouveau_bo *video_mem;
 576         int             pitch;
 577         int             offset;
 578         struct nouveau_bo *TT_mem_chunk[2];
 579         int             currentHostBuffer;
 580         struct nouveau_notifier *DMANotifier[2];
 581 } NVPortPrivRec, *NVPortPrivPtr;
 582
 583 #define GET_OVERLAY_PRIVATE(pNv) \
 584             (NVPortPrivPtr)((pNv)->overlayAdaptor->pPortPrivates[0].ptr)
 585
 586 #define GET_BLIT_PRIVATE(pNv) \
 587             (NVPortPrivPtr)((pNv)->blitAdaptor->pPortPrivates[0].ptr)
 588
 589 #define OFF_TIMER       0x01
 590 #define FREE_TIMER      0x02
 591 #define CLIENT_VIDEO_ON 0x04
 592 #define OFF_DELAY       500  /* milliseconds */
 593 #define FREE_DELAY      5000
 594
 595 #define TIMER_MASK      (OFF_TIMER | FREE_TIMER)
 596
 597 #endif /* __NV_STRUCT_H__ */