git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xaa.h"
   9 #include "xf86Cursor.h"
  10 #include "xf86int10.h"
  11 #include "exa.h"
  12 #ifdef XF86DRI
  13 #define _XF86DRI_SERVER_
  14 #include "xf86drm.h"
  15 #include "dri.h"
  16 #include <stdint.h>
  17 #include "nouveau_drm.h"
  18 #ifdef ENABLE_RANDR12
  19 #include "xf86Crtc.h"
  20 #endif
  21 #else
  22 #error "This driver requires a DRI-enabled X server"
  23 #endif
  24
  25 #include "nv50_type.h"
  26 #include "nv_pcicompat.h"
  27
  28 #define NV_ARCH_03  0x03
  29 #define NV_ARCH_04  0x04
  30 #define NV_ARCH_10  0x10
  31 #define NV_ARCH_20  0x20
  32 #define NV_ARCH_30  0x30
  33 #define NV_ARCH_40  0x40
  34 #define NV_ARCH_50  0x50
  35
  36 #define CHIPSET_NV03     0x0010
  37 #define CHIPSET_NV04     0x0020
  38 #define CHIPSET_NV10     0x0100
  39 #define CHIPSET_NV11     0x0110
  40 #define CHIPSET_NV15     0x0150
  41 #define CHIPSET_NV17     0x0170
  42 #define CHIPSET_NV18     0x0180
  43 #define CHIPSET_NFORCE   0x01A0
  44 #define CHIPSET_NFORCE2  0x01F0
  45 #define CHIPSET_NV20     0x0200
  46 #define CHIPSET_NV25     0x0250
  47 #define CHIPSET_NV28     0x0280
  48 #define CHIPSET_NV30     0x0300
  49 #define CHIPSET_NV31     0x0310
  50 #define CHIPSET_NV34     0x0320
  51 #define CHIPSET_NV35     0x0330
  52 #define CHIPSET_NV36     0x0340
  53 #define CHIPSET_NV40     0x0040
  54 #define CHIPSET_NV41     0x00C0
  55 #define CHIPSET_NV43     0x0140
  56 #define CHIPSET_NV44     0x0160
  57 #define CHIPSET_NV44A    0x0220
  58 #define CHIPSET_NV45     0x0210
  59 #define CHIPSET_NV50     0x0190
  60 #define CHIPSET_NV84     0x0400
  61 #define CHIPSET_MISC_BRIDGED  0x00F0
  62 #define CHIPSET_G70      0x0090
  63 #define CHIPSET_G71      0x0290
  64 #define CHIPSET_G72      0x01D0
  65 #define CHIPSET_G73      0x0390
  66 // integrated GeForces (6100, 6150)
  67 #define CHIPSET_C51      0x0240
  68 // variant of C51, seems based on a G70 design
  69 #define CHIPSET_C512     0x03D0
  70 #define CHIPSET_G73_BRIDGED 0x02E0
  71
  72
  73 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  74 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  75 #define SetBF(mask,value) ((value) << (0?mask))
  76 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  77 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  78 #define SetBit(n) (1<<(n))
  79 #define Set8Bits(value) ((value)&0xff)
  80
  81
  82 #define NV_I2C_BUSES 3
  83 #define NV40_NUM_DCB_ENTRIES 10
  84
  85 typedef enum
  86 {
  87     OUTPUT_NONE,
  88     OUTPUT_ANALOG,
  89     OUTPUT_DIGITAL,
  90     OUTPUT_PANEL,
  91     OUTPUT_TV,
  92 } NVOutputType;
  93
  94 typedef struct {
  95     int bitsPerPixel;
  96     int depth;
  97     int displayWidth;
  98     rgb weight;
  99     DisplayModePtr mode;
 100 } NVFBLayout;
 101
 102 typedef struct _nv_crtc_reg
 103 {
 104     unsigned char MiscOutReg;     /* */
 105     CARD8 CRTC[90];
 106     CARD8 Sequencer[5];
 107     CARD8 Graphics[9];
 108     CARD8 Attribute[21];
 109     unsigned char DAC[768];       /* Internal Colorlookuptable */
 110     CARD32 cursorConfig;
 111     CARD32 crtcOwner;
 112     CARD32 unk830;
 113     CARD32 unk834;
 114     CARD32 head;
 115 } NVCrtcRegRec, *NVCrtcRegPtr;
 116
 117 typedef struct _nv_output_reg
 118 {
 119         CARD32 fp_control;
 120         CARD32 crtcSync;
 121         CARD32 dither;
 122         CARD32 general;
 123         CARD32 bpp;
 124         CARD32 nv10_cursync;
 125         CARD32 output;
 126         CARD32 debug_0;
 127         CARD32 debug_1;
 128         CARD32 debug_2;
 129         CARD32 fp_horiz_regs[7];
 130         CARD32 fp_vert_regs[7];
 131         CARD32 fp_hvalid_start;
 132         CARD32 fp_hvalid_end;
 133         CARD32 fp_vvalid_start;
 134         CARD32 fp_vvalid_end;
 135         CARD8 TMDS[128];
 136 } NVOutputRegRec, *NVOutputRegPtr;
 137
 138 typedef struct _riva_hw_state
 139 {
 140     CARD32 bpp;
 141     CARD32 width;
 142     CARD32 height;
 143     CARD32 interlace;
 144     CARD32 repaint0;
 145     CARD32 repaint1;
 146     CARD32 screen;
 147     CARD32 scale;
 148     CARD32 dither;
 149     CARD32 extra;
 150     CARD32 fifo;
 151     CARD32 pixel;
 152     CARD32 horiz;
 153     CARD32 arbitration0;
 154     CARD32 arbitration1;
 155     CARD32 pll;
 156     CARD32 pllB;
 157     CARD32 vpll;
 158     CARD32 vpll2;
 159     CARD32 vpllB;
 160     CARD32 vpll2B;
 161     CARD32 pllsel;
 162     CARD32 general;
 163     CARD32 crtcOwner;
 164     CARD32 head;
 165     CARD32 head2;
 166     CARD32 config;
 167     CARD32 cursorConfig;
 168     CARD32 cursor0;
 169     CARD32 cursor1;
 170     CARD32 cursor2;
 171     CARD32 timingH;
 172     CARD32 timingV;
 173     CARD32 displayV;
 174     CARD32 crtcSync;
 175
 176     NVCrtcRegRec crtc_reg[2];
 177     NVOutputRegRec dac_reg[2];
 178 } RIVA_HW_STATE, *NVRegPtr;
 179
 180 typedef struct _nv50_crtc_reg
 181 {
 182
 183 } NV50CrtcRegRec, *NV50CrtcRegPtr;
 184
 185 typedef struct _nv50_hw_state
 186 {
 187         NV50CrtcRegRec crtc_reg[2];
 188 } NV50_HW_STATE, *NV50RegPtr;
 189
 190 typedef struct {
 191         int type;
 192         uint64_t size;
 193         uint64_t offset;
 194         void *map;
 195 } NVAllocRec;
 196
 197 typedef struct _NVOutputPrivateRec {
 198         int ramdac;
 199         I2CBusPtr                   pDDCBus;
 200         NVOutputType type;
 201         CARD32 fpSyncs;
 202         CARD32 fpWidth;
 203         CARD32 fpHeight;
 204         Bool fpdither;
 205 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 206
 207 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 208
 209 typedef struct _NVRec *NVPtr;
 210 typedef struct _NVRec {
 211     RIVA_HW_STATE       SavedReg;
 212     RIVA_HW_STATE       ModeReg;
 213     RIVA_HW_STATE       *CurrentState;
 214         NV50_HW_STATE   NV50SavedReg;
 215         NV50_HW_STATE   NV50ModeReg;
 216     CARD32              Architecture;
 217     EntityInfoPtr       pEnt;
 218 #ifndef XSERVER_LIBPCIACCESS
 219         pciVideoPtr     PciInfo;
 220         PCITAG          PciTag;
 221 #else
 222         struct pci_device *PciInfo;
 223 #endif /* XSERVER_LIBPCIACCESS */
 224     int                 Chipset;
 225     int                 NVArch;
 226     Bool                Primary;
 227     CARD32              IOAddress;
 228     Bool cursorOn;
 229
 230     /* VRAM physical address */
 231     unsigned long       VRAMPhysical;
 232     /* Size of VRAM BAR */
 233     unsigned long       VRAMPhysicalSize;
 234     /* Accesible VRAM size (by the GPU) */
 235     unsigned long       VRAMSize;
 236     /* AGP physical address */
 237     unsigned long       AGPPhysical;
 238     /* Accessible AGP size */
 239     unsigned long       AGPSize;
 240     /* PCI buffer virtual address */
 241     unsigned long       SGPhysical;
 242
 243     uint32_t *          VBIOS;
 244     NVAllocRec *        FB;
 245     NVAllocRec *        Cursor;
 246     NVAllocRec *        CLUT;   /* NV50 only */
 247     NVAllocRec *        ScratchBuffer;
 248     NVAllocRec *        GARTScratch;
 249     Bool                NoAccel;
 250     Bool                HWCursor;
 251     Bool                FpScale;
 252     Bool                ShadowFB;
 253     unsigned char *     ShadowPtr;
 254     int                 ShadowPitch;
 255     CARD32              MinVClockFreqKHz;
 256     CARD32              MaxVClockFreqKHz;
 257     CARD32              CrystalFreqKHz;
 258     CARD32              RamAmountKBytes;
 259     int drm_fd;
 260
 261     volatile CARD32 *REGS;
 262     volatile CARD32 *PCRTC0;
 263     volatile CARD32 *PCRTC1;
 264
 265         volatile CARD32 *NV50_PCRTC;
 266
 267     volatile CARD32 *PRAMDAC0;
 268     volatile CARD32 *PRAMDAC1;
 269     volatile CARD32 *PFB;
 270     volatile CARD32 *PFIFO;
 271     volatile CARD32 *PGRAPH;
 272     volatile CARD32 *PEXTDEV;
 273     volatile CARD32 *PTIMER;
 274     volatile CARD32 *PVIDEO;
 275     volatile CARD32 *PMC;
 276     volatile CARD32 *PRAMIN;
 277     volatile CARD32 *FIFO;
 278     volatile CARD32 *CURSOR;
 279     volatile CARD8 *PCIO0;
 280     volatile CARD8 *PCIO1;
 281     volatile CARD8 *PVIO;
 282     volatile CARD8 *PDIO0;
 283     volatile CARD8 *PDIO1;
 284     volatile CARD8 *PROM;
 285
 286
 287     volatile CARD32 *RAMHT;
 288     CARD32 pramin_free;
 289
 290     unsigned int SaveGeneration;
 291     uint8_t cur_head;
 292     ExaDriverPtr        EXADriverPtr;
 293     xf86CursorInfoPtr   CursorInfoRec;
 294     void                (*PointerMoved)(int index, int x, int y);
 295     ScreenBlockHandlerProcPtr BlockHandler;
 296     CloseScreenProcPtr  CloseScreen;
 297     int                 Rotate;
 298     NVFBLayout          CurrentLayout;
 299     /* Cursor */
 300     CARD32              curFg, curBg;
 301     CARD32              curImage[256];
 302     /* I2C / DDC */
 303     int ddc2;
 304     xf86Int10InfoPtr    pInt10;
 305     I2CBusPtr           I2C;
 306   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 307     void                (*DMAKickoffCallback)(NVPtr pNv);
 308     XF86VideoAdaptorPtr overlayAdaptor;
 309     XF86VideoAdaptorPtr blitAdaptor;
 310     int                 videoKey;
 311     int                 FlatPanel;
 312     Bool                FPDither;
 313     int                 Mobile;
 314     Bool                Television;
 315         int         vtOWNER;
 316         Bool            crtc_active[2];
 317     OptionInfoPtr       Options;
 318     Bool                alphaCursor;
 319     unsigned char       DDCBase;
 320     Bool                twoHeads;
 321     Bool                twoStagePLL;
 322     Bool                fpScaler;
 323     int                 fpWidth;
 324     int                 fpHeight;
 325     CARD32              fpSyncs;
 326     Bool                usePanelTweak;
 327     int                 PanelTweak;
 328     Bool                LVDS;
 329
 330     Bool                LockedUp;
 331
 332     volatile void *     NotifierBlock;
 333     struct drm_nouveau_notifierobj_alloc *Notifier0;
 334
 335     struct drm_nouveau_channel_alloc fifo;
 336     CARD32              dmaPut;
 337     CARD32              dmaCurrent;
 338     CARD32              dmaFree;
 339     CARD32              dmaMax;
 340     CARD32              *dmaBase;
 341
 342     CARD32              currentRop;
 343     int                 M2MFDirection;
 344
 345     Bool                WaitVSyncPossible;
 346     Bool                BlendingPossible;
 347     Bool                RandRRotation;
 348     DRIInfoPtr          pDRIInfo;
 349     drmVersionPtr       pLibDRMVersion;
 350     drmVersionPtr       pKernelDRMVersion;
 351
 352     Bool randr12_enable;
 353     CreateScreenResourcesProcPtr    CreateScreenResources;
 354
 355     /* we know about 3 i2c buses */
 356     I2CBusPtr           pI2CBus[3];
 357     int dcb_entries;
 358
 359     int analog_count;
 360     int digital_count;
 361     CARD32 dcb_table[NV40_NUM_DCB_ENTRIES]; /* 10 is a good limit */
 362     Bool crosswired_tmds;
 363     Bool ramdac_occupied[2];
 364     int crtc_associated[2];
 365
 366     struct {
 367             ORNum dac;
 368             ORNum sor;
 369     } i2cMap[4];
 370     struct {
 371             Bool  present;
 372             ORNum or;
 373     } lvds;
 374 } NVRec;
 375
 376 typedef struct _NVCrtcPrivateRec {
 377         int crtc;
 378         int head;
 379         Bool paletteEnabled;
 380 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 381
 382 typedef struct _NV50CrtcPrivRec {
 383         int head;
 384         int pclk; /* Target pixel clock in kHz */
 385         Bool cursorVisible;
 386         Bool skipModeFixup;
 387         Bool dither;
 388 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
 389
 390 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 391
 392 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 393
 394 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
 395 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
 396
 397 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
 398 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 399
 400 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
 401 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
 402
 403 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
 404 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
 405
 406 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
 407 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
 408
 409 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
 410 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
 411
 412 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
 413 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
 414
 415 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
 416 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
 417
 418 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
 419 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
 420
 421 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
 422 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
 423
 424 #endif /* __NV_STRUCT_H__ */