fence: ref could destroy the object it was referencing, fix that!
[nouveau] / src / nv_type.h
1 #ifndef __NV_STRUCT_H__
2 #define __NV_STRUCT_H__
3
4 #include "colormapst.h"
5 #include "vgaHW.h"
6 #include "xf86Cursor.h"
7 #include "xf86int10.h"
8 #include "exa.h"
9 #ifdef XF86DRI
10 #define _XF86DRI_SERVER_
11 #include "xf86drm.h"
12 #include "dri.h"
13 #include <stdbool.h>
14 #include <stdint.h>
15 #include "nouveau_drm.h"
16 #include "xf86Crtc.h"
17 #else
18 #error "This driver requires a DRI-enabled X server"
19 #endif
20
21 #include "nv_pcicompat.h"
22
23 #include "nouveau_local.h"
24
25 #include "nouveau_crtc.h"
26 #include "nouveau_connector.h"
27 #include "nouveau_output.h"
28
29 #include "drmmode_display.h"
30
31 #define NV_ARCH_03  0x03
32 #define NV_ARCH_04  0x04
33 #define NV_ARCH_10  0x10
34 #define NV_ARCH_20  0x20
35 #define NV_ARCH_30  0x30
36 #define NV_ARCH_40  0x40
37 #define NV_ARCH_50  0x50
38
39 #define CHIPSET_NV03     0x0010
40 #define CHIPSET_NV04     0x0020
41 #define CHIPSET_NV10     0x0100
42 #define CHIPSET_NV11     0x0110
43 #define CHIPSET_NV15     0x0150
44 #define CHIPSET_NV17     0x0170
45 #define CHIPSET_NV18     0x0180
46 #define CHIPSET_NFORCE   0x01A0
47 #define CHIPSET_NFORCE2  0x01F0
48 #define CHIPSET_NV20     0x0200
49 #define CHIPSET_NV25     0x0250
50 #define CHIPSET_NV28     0x0280
51 #define CHIPSET_NV30     0x0300
52 #define CHIPSET_NV31     0x0310
53 #define CHIPSET_NV34     0x0320
54 #define CHIPSET_NV35     0x0330
55 #define CHIPSET_NV36     0x0340
56 #define CHIPSET_NV40     0x0040
57 #define CHIPSET_NV41     0x00C0
58 #define CHIPSET_NV43     0x0140
59 #define CHIPSET_NV44     0x0160
60 #define CHIPSET_NV44A    0x0220
61 #define CHIPSET_NV45     0x0210
62 #define CHIPSET_NV50     0x0190
63 #define CHIPSET_NV84     0x0400
64 #define CHIPSET_MISC_BRIDGED  0x00F0
65 #define CHIPSET_G70      0x0090
66 #define CHIPSET_G71      0x0290
67 #define CHIPSET_G72      0x01D0
68 #define CHIPSET_G73      0x0390
69 // integrated GeForces (6100, 6150)
70 #define CHIPSET_C51      0x0240
71 // variant of C51, seems based on a G70 design
72 #define CHIPSET_C512     0x03D0
73 #define CHIPSET_G73_BRIDGED 0x02E0
74
75
76 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
77 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
78 #define SetBF(mask,value) ((value) << (0?mask))
79 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
80 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
81 #define SetBit(n) (1<<(n))
82 #define Set8Bits(value) ((value)&0xff)
83
84 #define MAX_NUM_DCB_ENTRIES 16
85
86 #define LOC_ON_CHIP 0
87
88 struct dcb_entry {
89         int index;
90         uint8_t type;
91         uint8_t i2c_index;
92         uint8_t heads;
93         uint8_t bus;
94         uint8_t location;
95         uint8_t or;
96         bool duallink_possible;
97         union {
98                 struct {
99                         bool use_straps_for_mode;
100                         bool use_power_scripts;
101                 } lvdsconf;
102         };
103 };
104
105 typedef enum
106 {/* matches DCB types */
107         OUTPUT_NONE = 4,
108         OUTPUT_ANALOG = 0,
109         OUTPUT_TMDS = 2,
110         OUTPUT_LVDS = 3,
111         OUTPUT_TV = 1,
112 } NVOutputType;
113
114 /* NV50 */
115 typedef enum Head {
116         HEAD0 = 0,
117         HEAD1
118 } Head;
119
120 /* NV50 */
121 typedef enum ORNum {
122         DAC0 = 0,
123         DAC1 = 1,
124         DAC2 = 2,
125         SOR0 = 0,
126         SOR1 = 1
127 } ORNum;
128
129 enum scaling_modes {
130         SCALE_PANEL,
131         SCALE_FULLSCREEN,
132         SCALE_ASPECT,
133         SCALE_NOSCALE,
134         SCALE_INVALID
135 };
136
137 typedef struct _nv_crtc_reg 
138 {
139         unsigned char MiscOutReg;     /* */
140         uint8_t CRTC[0xff];
141         uint8_t CR58[0x10];
142         uint8_t Sequencer[5];
143         uint8_t Graphics[9];
144         uint8_t Attribute[21];
145         unsigned char DAC[768];       /* Internal Colorlookuptable */
146         uint32_t cursorConfig;
147         uint32_t crtcOwner;
148         uint32_t gpio;
149         uint32_t gpio_ext;
150         uint32_t unk830;
151         uint32_t unk834;
152         uint32_t unk850;
153         uint32_t head;
154         uint32_t config;
155         uint32_t fb_start;
156
157         /* These are former output regs, but are believed to be crtc related */
158         uint32_t general;
159         uint32_t unk_630;
160         uint32_t debug_0;
161         uint32_t debug_1;
162         uint32_t debug_2;
163         uint32_t unk_a20;
164         uint32_t unk_a24;
165         uint32_t unk_a34;
166         uint32_t dither_regs[6];
167         uint32_t fp_horiz_regs[7];
168         uint32_t fp_vert_regs[7];
169         uint32_t nv10_cursync;
170         uint32_t fp_control;
171         uint32_t dither;
172         uint32_t vpll_a;
173         uint32_t vpll_b;
174 } NVCrtcRegRec, *NVCrtcRegPtr;
175
176 typedef struct _nv_output_reg
177 {
178         uint32_t output;
179         int head;
180 } NVOutputRegRec, *NVOutputRegPtr;
181
182 typedef struct _riva_hw_state
183 {
184         uint32_t bpp;
185         uint32_t width;
186         uint32_t height;
187         uint32_t interlace;
188         uint32_t repaint0;
189         uint32_t repaint1;
190         uint32_t screen;
191         uint32_t scale;
192         uint32_t dither;
193         uint32_t extra;
194         uint32_t fifo;
195         uint32_t pixel;
196         uint32_t horiz;
197         uint32_t arbitration0;
198         uint32_t arbitration1;
199         uint32_t pll;
200         uint32_t pllB;
201         uint32_t vpll;
202         uint32_t vpll2;
203         uint32_t vpllB;
204         uint32_t vpll2B;
205         uint32_t pllsel;
206         uint32_t sel_clk;
207         uint32_t reg580;
208         uint32_t general;
209         uint32_t crtcOwner;
210         uint32_t head;
211         uint32_t head2;
212         uint32_t cursorConfig;
213         uint32_t cursor0;
214         uint32_t cursor1;
215         uint32_t cursor2;
216         uint32_t timingH;
217         uint32_t timingV;
218         uint32_t displayV;
219         uint32_t crtcSync;
220
221         NVCrtcRegRec crtc_reg[2];
222 } RIVA_HW_STATE, *NVRegPtr;
223
224 struct nouveau_crtc {
225         int head;
226         uint8_t last_dpms;
227         struct nouveau_bo *shadow;
228         int fp_users;
229 };
230
231 typedef enum {
232         OUTPUT_A = (1 << 0),
233         OUTPUT_B = (1 << 1),
234         OUTPUT_C = (1 << 2)
235 } ValidOutputResource;
236
237 struct nouveau_output {
238         xf86MonPtr mon;
239         uint8_t last_dpms;
240         I2CBusPtr pDDCBus;
241         struct dcb_entry *dcb;
242         DisplayModePtr native_mode;
243         uint8_t scaling_mode;
244         bool dithering;
245         NVOutputRegRec restore;
246 };
247
248 #define to_nouveau_crtc(x) ((struct nouveau_crtc *)(x)->driver_private)
249 #define to_nouveau_output(x) ((struct nouveau_output *)(x)->driver_private)
250
251 /* changing these requires matching changes to reg tables in nv_get_clock */
252 #define MAX_PLL_TYPES   4
253 enum pll_types {
254         NVPLL,
255         MPLL,
256         VPLL1,
257         VPLL2
258 };
259
260 struct pll_lims {
261         struct {
262                 int minfreq;
263                 int maxfreq;
264                 int min_inputfreq;
265                 int max_inputfreq;
266
267                 uint8_t min_m;
268                 uint8_t max_m;
269                 uint8_t min_n;
270                 uint8_t max_n;
271         } vco1, vco2;
272
273         uint8_t unk1c;
274         uint8_t max_log2p_bias;
275         uint8_t log2p_bias;
276         int refclk;
277 };
278
279 typedef struct {
280         uint8_t *data;
281         unsigned int length;
282         bool execute;
283
284         uint8_t major_version, chip_version;
285         uint8_t feature_byte;
286
287         uint32_t fmaxvco, fminvco;
288
289         uint32_t dactestval;
290
291         uint16_t init_script_tbls_ptr;
292         uint16_t extra_init_script_tbl_ptr;
293         uint16_t macro_index_tbl_ptr;
294         uint16_t macro_tbl_ptr;
295         uint16_t condition_tbl_ptr;
296         uint16_t io_condition_tbl_ptr;
297         uint16_t io_flag_condition_tbl_ptr;
298         uint16_t init_function_tbl_ptr;
299
300         uint16_t pll_limit_tbl_ptr;
301         uint16_t ram_restrict_tbl_ptr;
302
303         uint8_t digital_min_front_porch;
304
305         struct {
306                 DisplayModePtr native_mode;
307                 uint8_t *edid;
308                 uint16_t lvdsmanufacturerpointer;
309                 uint16_t fpxlatemanufacturertableptr;
310                 uint16_t xlated_entry;
311                 bool power_off_for_reset;
312                 bool reset_after_pclk_change;
313                 bool dual_link;
314                 bool link_c_increment;
315                 bool if_is_24bit;
316                 bool BITbit1;
317                 int duallink_transition_clk;
318                 /* lower nibble stores PEXTDEV_BOOT_0 strap
319                  * upper nibble stores xlated display strap */
320                 uint8_t strapping;
321         } fp;
322
323         struct {
324                 uint16_t output0_script_ptr;
325                 uint16_t output1_script_ptr;
326         } tmds;
327
328         struct {
329                 uint16_t mem_init_tbl_ptr;
330                 uint16_t sdr_seq_tbl_ptr;
331                 uint16_t ddr_seq_tbl_ptr;
332
333                 struct {
334                         uint8_t crt, tv, panel;
335                 } i2c_indices;
336         } legacy;
337 } bios_t;
338
339 enum LVDS_script {
340         /* Order *does* matter here */
341         LVDS_INIT = 1,
342         LVDS_RESET,
343         LVDS_BACKLIGHT_ON,
344         LVDS_BACKLIGHT_OFF,
345         LVDS_PANEL_ON,
346         LVDS_PANEL_OFF
347 };
348
349 typedef struct _NVRec *NVPtr;
350 typedef struct _NVRec {
351     RIVA_HW_STATE       SavedReg;
352     RIVA_HW_STATE       ModeReg;
353     uint32_t saved_vga_font[4][16384];
354     uint32_t              Architecture;
355     EntityInfoPtr       pEnt;
356 #ifndef XSERVER_LIBPCIACCESS
357         pciVideoPtr     PciInfo;
358         PCITAG          PciTag;
359 #else
360         struct pci_device *PciInfo;
361 #endif /* XSERVER_LIBPCIACCESS */
362     int                 Chipset;
363     int                 NVArch;
364     Bool                Primary;
365     CARD32              IOAddress;
366
367     /* VRAM physical address */
368     unsigned long       VRAMPhysical;
369     /* Size of VRAM BAR */
370     unsigned long       VRAMPhysicalSize;
371     /* Accesible VRAM size (by the GPU) */
372     unsigned long       VRAMSize;
373     /* Accessible AGP size */
374     unsigned long       AGPSize;
375
376     /* Various pinned memory regions */
377     struct nouveau_bo * FB;
378     void *              FBMap;
379     //struct nouveau_bo * FB_old; /* for KMS */
380     struct nouveau_bo * shadow[2]; /* for easy acces by exa */
381     struct nouveau_bo * Cursor;
382     struct nouveau_bo * Cursor2;
383     struct nouveau_bo * CLUT0;  /* NV50 only */
384     struct nouveau_bo * CLUT1;  /* NV50 only */
385     struct nouveau_bo * GART;
386
387     bios_t              VBIOS;
388     Bool                NoAccel;
389     Bool                HWCursor;
390     Bool                FpScale;
391     Bool                ShadowFB;
392     unsigned char *     ShadowPtr;
393     int                 ShadowPitch;
394     CARD32              MinVClockFreqKHz;
395     CARD32              MaxVClockFreqKHz;
396     CARD32              CrystalFreqKHz;
397     CARD32              RamAmountKBytes;
398
399     volatile CARD32 *REGS;
400     volatile CARD32 *FB_BAR;
401     volatile CARD32 *PGRAPH;
402     volatile CARD32 *PRAMIN;
403     volatile CARD32 *CURSOR;
404     volatile CARD8 *PCIO0;
405     volatile CARD8 *PCIO1;
406     volatile CARD8 *PVIO0;
407     volatile CARD8 *PVIO1;
408     volatile CARD8 *PDIO0;
409     volatile CARD8 *PDIO1;
410
411     unsigned int SaveGeneration;
412     uint8_t cur_head;
413     ExaDriverPtr        EXADriverPtr;
414     xf86CursorInfoPtr   CursorInfoRec;
415     ScreenBlockHandlerProcPtr BlockHandler;
416     CloseScreenProcPtr  CloseScreen;
417     /* Cursor */
418     CARD32              curFg, curBg;
419     CARD32              curImage[256];
420     /* I2C / DDC */
421     xf86Int10InfoPtr    pInt10;
422     unsigned            Int10Mode;
423     I2CBusPtr           I2C;
424   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
425     XF86VideoAdaptorPtr overlayAdaptor;
426     XF86VideoAdaptorPtr blitAdaptor;
427     XF86VideoAdaptorPtr textureAdaptor[2];
428     int                 videoKey;
429     int                 FlatPanel;
430     Bool                FPDither;
431     int                 Mobile;
432     Bool                Television;
433         int         vtOWNER;
434         Bool            crtc_active[2];
435     OptionInfoPtr       Options;
436     Bool                alphaCursor;
437     unsigned char       DDCBase;
438     Bool                twoHeads;
439     Bool                twoStagePLL;
440     Bool                fpScaler;
441     int                 fpWidth;
442     int                 fpHeight;
443     CARD32              fpSyncs;
444     Bool                usePanelTweak;
445     int                 PanelTweak;
446     Bool                LVDS;
447
448     Bool                LockedUp;
449
450     CARD32              currentRop;
451
452     Bool                WaitVSyncPossible;
453     Bool                BlendingPossible;
454     DRIInfoPtr          pDRIInfo;
455     drmVersionPtr       pLibDRMVersion;
456     drmVersionPtr       pKernelDRMVersion;
457
458         Bool randr12_enable;
459         Bool kms_enable;
460
461         I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
462
463 #ifdef XF86DRM_MODE
464         void *drmmode; /* for KMS */
465 #endif
466
467         struct {
468                 int entries;
469                 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
470                 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
471                 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
472         } dcb_table;
473
474         nouveauCrtcPtr crtc[2];
475         nouveauOutputPtr output; /* this a linked list. */
476         /* Assume a connector can exist for each i2c bus. */
477         nouveauConnectorPtr connector[MAX_NUM_DCB_ENTRIES];
478
479         struct {
480                 ORNum dac;
481                 ORNum sor;
482         } i2cMap[4];
483         struct {
484                 Bool  present;
485                 ORNum or;
486         } lvds;
487
488         /* DRM interface */
489         struct nouveau_device *dev;
490
491         /* GPU context */
492         struct nouveau_channel *chan;
493         struct nouveau_notifier *notify0;
494         struct nouveau_grobj *NvContextSurfaces;
495         struct nouveau_grobj *NvContextBeta1;
496         struct nouveau_grobj *NvContextBeta4;
497         struct nouveau_grobj *NvImagePattern;
498         struct nouveau_grobj *NvRop;
499         struct nouveau_grobj *NvRectangle;
500         struct nouveau_grobj *NvImageBlit;
501         struct nouveau_grobj *NvScaledImage;
502         struct nouveau_grobj *NvClipRectangle;
503         struct nouveau_grobj *NvMemFormat;
504         struct nouveau_grobj *NvImageFromCpu;
505         struct nouveau_grobj *Nv2D;
506         struct nouveau_grobj *Nv3D;
507         struct nouveau_bo *tesla_scratch;
508
509         struct nouveau_fence *exa_sync;
510 } NVRec;
511
512 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
513
514 #define NVShowHideCursor(pScrn, show) do {                                                      \
515         NVPtr pNv = NVPTR(pScrn);                                                                               \
516         nv_crtc_show_hide_cursor(pScrn, pNv->cur_head, show);                           \
517 } while(0)
518
519 #define NVLockUnlock(pScrn, lock) NVLockVgaCrtc(NVPTR(pScrn), NVPTR(pScrn)->cur_head, lock)
520
521 #define nvReadCurVGA(pNv, reg) NVReadVgaCrtc(pNv, pNv->cur_head, reg)
522 #define nvWriteCurVGA(pNv, reg, val) NVWriteVgaCrtc(pNv, pNv->cur_head, reg, val)
523
524 #define nvReadCurRAMDAC(pNv, reg) NVReadRAMDAC(pNv, pNv->cur_head, reg)
525 #define nvWriteCurRAMDAC(pNv, reg, val) NVWriteRAMDAC(pNv, pNv->cur_head, reg, val)
526
527 #define nvReadCurCRTC(pNv, reg) NVReadCRTC(pNv, pNv->cur_head, reg)
528 #define nvWriteCurCRTC(pNv, reg, val) NVWriteCRTC(pNv, pNv->cur_head, reg, val)
529
530 #define nvReadFB(pNv, reg) DDXMMIOW("nvReadFB: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
531 #define nvWriteFB(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteFB: reg %08x val %08x\n", reg, val))
532
533 #define nvReadGRAPH(pNv, reg) DDXMMIOW("nvReadGRAPH: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
534 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteGRAPH: reg %08x val %08x\n", reg, val))
535
536 #define nvReadMC(pNv, reg) DDXMMIOW("nvReadMC: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
537 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteMC: reg %08x val %08x\n", reg, val))
538
539 #define nvReadME(pNv, reg) DDXMMIOW("nvReadME: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
540 #define nvWriteME(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteME: reg %08x val %08x\n", reg, val))
541
542 #define nvReadEXTDEV(pNv, reg) DDXMMIOW("nvReadEXTDEV: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
543 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteEXTDEV: reg %08x val %08x\n", reg, val))
544
545 #define nvReadTIMER(pNv, reg) DDXMMIOW("nvReadTIMER: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
546 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteTIMER: reg %08x val %08x\n", reg, val))
547
548 #define nvReadVIDEO(pNv, reg) DDXMMIOW("nvReadVIDEO: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
549 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteVIDEO: reg %08x val %08x\n", reg, val))
550
551 typedef struct _NVPortPrivRec {
552         short           brightness;
553         short           contrast;
554         short           saturation;
555         short           hue;
556         RegionRec       clip;
557         CARD32          colorKey;
558         Bool            autopaintColorKey;
559         Bool            doubleBuffer;
560         CARD32          videoStatus;
561         int             currentBuffer;
562         Time            videoTime;
563         int             overlayCRTC;
564         Bool            grabbedByV4L;
565         Bool            iturbt_709;
566         Bool            blitter;
567         Bool            texture;
568         Bool            bicubic; /* only for texture adapter */
569         Bool            SyncToVBlank;
570         struct nouveau_bo *video_mem;
571         int             pitch;
572         int             offset;
573         struct nouveau_bo *TT_mem_chunk[2];
574         int             currentHostBuffer;
575 } NVPortPrivRec, *NVPortPrivPtr;
576
577 #define GET_OVERLAY_PRIVATE(pNv) \
578             (NVPortPrivPtr)((pNv)->overlayAdaptor->pPortPrivates[0].ptr)
579
580 #define GET_BLIT_PRIVATE(pNv) \
581             (NVPortPrivPtr)((pNv)->blitAdaptor->pPortPrivates[0].ptr)
582
583 #define OFF_TIMER       0x01
584 #define FREE_TIMER      0x02
585 #define CLIENT_VIDEO_ON 0x04
586 #define OFF_DELAY       500  /* milliseconds */
587 #define FREE_DELAY      5000
588
589 #define TIMER_MASK      (OFF_TIMER | FREE_TIMER)
590
591 #endif /* __NV_STRUCT_H__ */