1 #ifndef __NV_STRUCT_H__
2 #define __NV_STRUCT_H__
4 #include "colormapst.h"
6 #include "xf86Cursor.h"
10 #define _XF86DRI_SERVER_
15 #include "nouveau_drm.h"
18 #error "This driver requires a DRI-enabled X server"
21 #include "nv_pcicompat.h"
23 #include "nouveau_local.h"
25 #include "nouveau_crtc.h"
26 #include "nouveau_connector.h"
27 #include "nouveau_output.h"
29 #include "drmmode_display.h"
31 #define NV_ARCH_03 0x03
32 #define NV_ARCH_04 0x04
33 #define NV_ARCH_10 0x10
34 #define NV_ARCH_20 0x20
35 #define NV_ARCH_30 0x30
36 #define NV_ARCH_40 0x40
37 #define NV_ARCH_50 0x50
39 #define CHIPSET_NV03 0x0010
40 #define CHIPSET_NV04 0x0020
41 #define CHIPSET_NV10 0x0100
42 #define CHIPSET_NV11 0x0110
43 #define CHIPSET_NV15 0x0150
44 #define CHIPSET_NV17 0x0170
45 #define CHIPSET_NV18 0x0180
46 #define CHIPSET_NFORCE 0x01A0
47 #define CHIPSET_NFORCE2 0x01F0
48 #define CHIPSET_NV20 0x0200
49 #define CHIPSET_NV25 0x0250
50 #define CHIPSET_NV28 0x0280
51 #define CHIPSET_NV30 0x0300
52 #define CHIPSET_NV31 0x0310
53 #define CHIPSET_NV34 0x0320
54 #define CHIPSET_NV35 0x0330
55 #define CHIPSET_NV36 0x0340
56 #define CHIPSET_NV40 0x0040
57 #define CHIPSET_NV41 0x00C0
58 #define CHIPSET_NV43 0x0140
59 #define CHIPSET_NV44 0x0160
60 #define CHIPSET_NV44A 0x0220
61 #define CHIPSET_NV45 0x0210
62 #define CHIPSET_NV50 0x0190
63 #define CHIPSET_NV84 0x0400
64 #define CHIPSET_MISC_BRIDGED 0x00F0
65 #define CHIPSET_G70 0x0090
66 #define CHIPSET_G71 0x0290
67 #define CHIPSET_G72 0x01D0
68 #define CHIPSET_G73 0x0390
69 // integrated GeForces (6100, 6150)
70 #define CHIPSET_C51 0x0240
71 // variant of C51, seems based on a G70 design
72 #define CHIPSET_C512 0x03D0
73 #define CHIPSET_G73_BRIDGED 0x02E0
76 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
77 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
78 #define SetBF(mask,value) ((value) << (0?mask))
79 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
80 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
81 #define SetBit(n) (1<<(n))
82 #define Set8Bits(value) ((value)&0xff)
84 #define MAX_NUM_DCB_ENTRIES 16
96 bool duallink_possible;
99 bool use_straps_for_mode;
100 bool use_power_scripts;
106 {/* matches DCB types */
137 typedef struct _nv_crtc_reg
139 unsigned char MiscOutReg; /* */
142 uint8_t Sequencer[5];
144 uint8_t Attribute[21];
145 unsigned char DAC[768]; /* Internal Colorlookuptable */
146 uint32_t cursorConfig;
157 /* These are former output regs, but are believed to be crtc related */
166 uint32_t dither_regs[6];
167 uint32_t fp_horiz_regs[7];
168 uint32_t fp_vert_regs[7];
169 uint32_t nv10_cursync;
174 } NVCrtcRegRec, *NVCrtcRegPtr;
176 typedef struct _nv_output_reg
180 } NVOutputRegRec, *NVOutputRegPtr;
182 typedef struct _riva_hw_state
197 uint32_t arbitration0;
198 uint32_t arbitration1;
212 uint32_t cursorConfig;
221 NVCrtcRegRec crtc_reg[2];
222 } RIVA_HW_STATE, *NVRegPtr;
224 struct nouveau_crtc {
227 struct nouveau_bo *shadow;
235 } ValidOutputResource;
237 struct nouveau_output {
241 struct dcb_entry *dcb;
242 DisplayModePtr native_mode;
243 uint8_t scaling_mode;
245 NVOutputRegRec restore;
248 #define to_nouveau_crtc(x) ((struct nouveau_crtc *)(x)->driver_private)
249 #define to_nouveau_output(x) ((struct nouveau_output *)(x)->driver_private)
251 /* changing these requires matching changes to reg tables in nv_get_clock */
252 #define MAX_PLL_TYPES 4
274 uint8_t max_log2p_bias;
284 uint8_t major_version, chip_version;
285 uint8_t feature_byte;
287 uint32_t fmaxvco, fminvco;
291 uint16_t init_script_tbls_ptr;
292 uint16_t extra_init_script_tbl_ptr;
293 uint16_t macro_index_tbl_ptr;
294 uint16_t macro_tbl_ptr;
295 uint16_t condition_tbl_ptr;
296 uint16_t io_condition_tbl_ptr;
297 uint16_t io_flag_condition_tbl_ptr;
298 uint16_t init_function_tbl_ptr;
300 uint16_t pll_limit_tbl_ptr;
301 uint16_t ram_restrict_tbl_ptr;
303 uint8_t digital_min_front_porch;
306 DisplayModePtr native_mode;
308 uint16_t lvdsmanufacturerpointer;
309 uint16_t fpxlatemanufacturertableptr;
310 uint16_t xlated_entry;
311 bool power_off_for_reset;
312 bool reset_after_pclk_change;
314 bool link_c_increment;
317 int duallink_transition_clk;
318 /* lower nibble stores PEXTDEV_BOOT_0 strap
319 * upper nibble stores xlated display strap */
324 uint16_t output0_script_ptr;
325 uint16_t output1_script_ptr;
329 uint16_t mem_init_tbl_ptr;
330 uint16_t sdr_seq_tbl_ptr;
331 uint16_t ddr_seq_tbl_ptr;
334 uint8_t crt, tv, panel;
340 /* Order *does* matter here */
349 typedef struct _NVRec *NVPtr;
350 typedef struct _NVRec {
351 RIVA_HW_STATE SavedReg;
352 RIVA_HW_STATE ModeReg;
353 uint32_t saved_vga_font[4][16384];
354 uint32_t Architecture;
356 #ifndef XSERVER_LIBPCIACCESS
360 struct pci_device *PciInfo;
361 #endif /* XSERVER_LIBPCIACCESS */
367 /* VRAM physical address */
368 unsigned long VRAMPhysical;
369 /* Size of VRAM BAR */
370 unsigned long VRAMPhysicalSize;
371 /* Accesible VRAM size (by the GPU) */
372 unsigned long VRAMSize;
373 /* Accessible AGP size */
374 unsigned long AGPSize;
376 /* Various pinned memory regions */
377 struct nouveau_bo * FB;
379 //struct nouveau_bo * FB_old; /* for KMS */
380 struct nouveau_bo * shadow[2]; /* for easy acces by exa */
381 struct nouveau_bo * Cursor;
382 struct nouveau_bo * Cursor2;
383 struct nouveau_bo * CLUT0; /* NV50 only */
384 struct nouveau_bo * CLUT1; /* NV50 only */
385 struct nouveau_bo * GART;
392 unsigned char * ShadowPtr;
394 CARD32 MinVClockFreqKHz;
395 CARD32 MaxVClockFreqKHz;
396 CARD32 CrystalFreqKHz;
397 CARD32 RamAmountKBytes;
399 volatile CARD32 *REGS;
400 volatile CARD32 *FB_BAR;
401 volatile CARD32 *PGRAPH;
402 volatile CARD32 *PRAMIN;
403 volatile CARD32 *CURSOR;
404 volatile CARD8 *PCIO0;
405 volatile CARD8 *PCIO1;
406 volatile CARD8 *PVIO0;
407 volatile CARD8 *PVIO1;
408 volatile CARD8 *PDIO0;
409 volatile CARD8 *PDIO1;
411 unsigned int SaveGeneration;
413 ExaDriverPtr EXADriverPtr;
414 xf86CursorInfoPtr CursorInfoRec;
415 ScreenBlockHandlerProcPtr BlockHandler;
416 CloseScreenProcPtr CloseScreen;
419 CARD32 curImage[256];
421 xf86Int10InfoPtr pInt10;
424 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
425 XF86VideoAdaptorPtr overlayAdaptor;
426 XF86VideoAdaptorPtr blitAdaptor;
427 XF86VideoAdaptorPtr textureAdaptor[2];
435 OptionInfoPtr Options;
437 unsigned char DDCBase;
452 Bool WaitVSyncPossible;
453 Bool BlendingPossible;
455 drmVersionPtr pLibDRMVersion;
456 drmVersionPtr pKernelDRMVersion;
461 I2CBusPtr pI2CBus[MAX_NUM_DCB_ENTRIES];
464 void *drmmode; /* for KMS */
469 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
470 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
471 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
474 nouveauCrtcPtr crtc[2];
475 nouveauOutputPtr output; /* this a linked list. */
476 /* Assume a connector can exist for each i2c bus. */
477 nouveauConnectorPtr connector[MAX_NUM_DCB_ENTRIES];
489 struct nouveau_device *dev;
492 struct nouveau_channel *chan;
493 struct nouveau_notifier *notify0;
494 struct nouveau_grobj *NvContextSurfaces;
495 struct nouveau_grobj *NvContextBeta1;
496 struct nouveau_grobj *NvContextBeta4;
497 struct nouveau_grobj *NvImagePattern;
498 struct nouveau_grobj *NvRop;
499 struct nouveau_grobj *NvRectangle;
500 struct nouveau_grobj *NvImageBlit;
501 struct nouveau_grobj *NvScaledImage;
502 struct nouveau_grobj *NvClipRectangle;
503 struct nouveau_grobj *NvMemFormat;
504 struct nouveau_grobj *NvImageFromCpu;
505 struct nouveau_grobj *Nv2D;
506 struct nouveau_grobj *Nv3D;
507 struct nouveau_bo *tesla_scratch;
509 struct nouveau_fence *exa_sync;
512 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
514 #define NVShowHideCursor(pScrn, show) do { \
515 NVPtr pNv = NVPTR(pScrn); \
516 nv_crtc_show_hide_cursor(pScrn, pNv->cur_head, show); \
519 #define NVLockUnlock(pScrn, lock) NVLockVgaCrtc(NVPTR(pScrn), NVPTR(pScrn)->cur_head, lock)
521 #define nvReadCurVGA(pNv, reg) NVReadVgaCrtc(pNv, pNv->cur_head, reg)
522 #define nvWriteCurVGA(pNv, reg, val) NVWriteVgaCrtc(pNv, pNv->cur_head, reg, val)
524 #define nvReadCurRAMDAC(pNv, reg) NVReadRAMDAC(pNv, pNv->cur_head, reg)
525 #define nvWriteCurRAMDAC(pNv, reg, val) NVWriteRAMDAC(pNv, pNv->cur_head, reg, val)
527 #define nvReadCurCRTC(pNv, reg) NVReadCRTC(pNv, pNv->cur_head, reg)
528 #define nvWriteCurCRTC(pNv, reg, val) NVWriteCRTC(pNv, pNv->cur_head, reg, val)
530 #define nvReadFB(pNv, reg) DDXMMIOW("nvReadFB: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
531 #define nvWriteFB(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteFB: reg %08x val %08x\n", reg, val))
533 #define nvReadGRAPH(pNv, reg) DDXMMIOW("nvReadGRAPH: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
534 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteGRAPH: reg %08x val %08x\n", reg, val))
536 #define nvReadMC(pNv, reg) DDXMMIOW("nvReadMC: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
537 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteMC: reg %08x val %08x\n", reg, val))
539 #define nvReadME(pNv, reg) DDXMMIOW("nvReadME: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
540 #define nvWriteME(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteME: reg %08x val %08x\n", reg, val))
542 #define nvReadEXTDEV(pNv, reg) DDXMMIOW("nvReadEXTDEV: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
543 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteEXTDEV: reg %08x val %08x\n", reg, val))
545 #define nvReadTIMER(pNv, reg) DDXMMIOW("nvReadTIMER: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
546 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteTIMER: reg %08x val %08x\n", reg, val))
548 #define nvReadVIDEO(pNv, reg) DDXMMIOW("nvReadVIDEO: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
549 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteVIDEO: reg %08x val %08x\n", reg, val))
551 typedef struct _NVPortPrivRec {
558 Bool autopaintColorKey;
568 Bool bicubic; /* only for texture adapter */
570 struct nouveau_bo *video_mem;
573 struct nouveau_bo *TT_mem_chunk[2];
574 int currentHostBuffer;
575 } NVPortPrivRec, *NVPortPrivPtr;
577 #define GET_OVERLAY_PRIVATE(pNv) \
578 (NVPortPrivPtr)((pNv)->overlayAdaptor->pPortPrivates[0].ptr)
580 #define GET_BLIT_PRIVATE(pNv) \
581 (NVPortPrivPtr)((pNv)->blitAdaptor->pPortPrivates[0].ptr)
583 #define OFF_TIMER 0x01
584 #define FREE_TIMER 0x02
585 #define CLIENT_VIDEO_ON 0x04
586 #define OFF_DELAY 500 /* milliseconds */
587 #define FREE_DELAY 5000
589 #define TIMER_MASK (OFF_TIMER | FREE_TIMER)
591 #endif /* __NV_STRUCT_H__ */