git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xf86Cursor.h"
   9 #include "xf86int10.h"
  10 #include "exa.h"
  11 #ifdef XF86DRI
  12 #define _XF86DRI_SERVER_
  13 #include "xf86drm.h"
  14 #include "dri.h"
  15 #include <stdint.h>
  16 #include "nouveau_drm.h"
  17 #include "xf86Crtc.h"
  18 #else
  19 #error "This driver requires a DRI-enabled X server"
  20 #endif
  21
  22 #include "nv50_type.h"
  23 #include "nv_pcicompat.h"
  24
  25 #define NV_ARCH_03  0x03
  26 #define NV_ARCH_04  0x04
  27 #define NV_ARCH_10  0x10
  28 #define NV_ARCH_20  0x20
  29 #define NV_ARCH_30  0x30
  30 #define NV_ARCH_40  0x40
  31 #define NV_ARCH_50  0x50
  32
  33 #define CHIPSET_NV03     0x0010
  34 #define CHIPSET_NV04     0x0020
  35 #define CHIPSET_NV10     0x0100
  36 #define CHIPSET_NV11     0x0110
  37 #define CHIPSET_NV15     0x0150
  38 #define CHIPSET_NV17     0x0170
  39 #define CHIPSET_NV18     0x0180
  40 #define CHIPSET_NFORCE   0x01A0
  41 #define CHIPSET_NFORCE2  0x01F0
  42 #define CHIPSET_NV20     0x0200
  43 #define CHIPSET_NV25     0x0250
  44 #define CHIPSET_NV28     0x0280
  45 #define CHIPSET_NV30     0x0300
  46 #define CHIPSET_NV31     0x0310
  47 #define CHIPSET_NV34     0x0320
  48 #define CHIPSET_NV35     0x0330
  49 #define CHIPSET_NV36     0x0340
  50 #define CHIPSET_NV40     0x0040
  51 #define CHIPSET_NV41     0x00C0
  52 #define CHIPSET_NV43     0x0140
  53 #define CHIPSET_NV44     0x0160
  54 #define CHIPSET_NV44A    0x0220
  55 #define CHIPSET_NV45     0x0210
  56 #define CHIPSET_NV50     0x0190
  57 #define CHIPSET_NV84     0x0400
  58 #define CHIPSET_MISC_BRIDGED  0x00F0
  59 #define CHIPSET_G70      0x0090
  60 #define CHIPSET_G71      0x0290
  61 #define CHIPSET_G72      0x01D0
  62 #define CHIPSET_G73      0x0390
  63 // integrated GeForces (6100, 6150)
  64 #define CHIPSET_C51      0x0240
  65 // variant of C51, seems based on a G70 design
  66 #define CHIPSET_C512     0x03D0
  67 #define CHIPSET_G73_BRIDGED 0x02E0
  68
  69
  70 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  71 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  72 #define SetBF(mask,value) ((value) << (0?mask))
  73 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  74 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  75 #define SetBit(n) (1<<(n))
  76 #define Set8Bits(value) ((value)&0xff)
  77
  78
  79 #define MAX_NUM_DCB_ENTRIES 16
  80
  81 typedef enum /* matches DCB types */
  82 {
  83     OUTPUT_NONE = 4,
  84     OUTPUT_ANALOG = 0,
  85     OUTPUT_TMDS = 2,
  86     OUTPUT_LVDS = 3,
  87     OUTPUT_TV = 1,
  88 } NVOutputType;
  89
  90 typedef struct {
  91     int bitsPerPixel;
  92     int depth;
  93     int displayWidth;
  94     rgb weight;
  95     DisplayModePtr mode;
  96 } NVFBLayout;
  97
  98 typedef struct _nv_crtc_reg
  99 {
 100         unsigned char MiscOutReg;     /* */
 101         CARD8 CRTC[90];
 102         CARD8 Sequencer[5];
 103         CARD8 Graphics[9];
 104         CARD8 Attribute[21];
 105         unsigned char DAC[768];       /* Internal Colorlookuptable */
 106         CARD32 cursorConfig;
 107         CARD32 crtcOwner;
 108         CARD32 gpio;
 109         CARD32 unk830;
 110         CARD32 unk834;
 111         CARD32 unk850;
 112         CARD32 unk81c;
 113         CARD32 head;
 114 } NVCrtcRegRec, *NVCrtcRegPtr;
 115
 116 typedef struct _nv_output_reg
 117 {
 118         CARD32 fp_control;
 119         CARD32 crtcSync;
 120         CARD32 dither;
 121         CARD32 general;
 122         CARD32 test_control;
 123         CARD32 unk_670;
 124         CARD32 unk_900;
 125         CARD32 bpp;
 126         CARD32 nv10_cursync;
 127         CARD32 output;
 128         CARD32 debug_0;
 129         CARD32 debug_1;
 130         CARD32 debug_2;
 131         CARD32 sel_clk;
 132         CARD32 unk_a20;
 133         CARD32 unk_a24;
 134         CARD32 unk_a34;
 135         CARD32 fp_horiz_regs[7];
 136         CARD32 fp_vert_regs[7];
 137         CARD32 fp_hvalid_start;
 138         CARD32 fp_hvalid_end;
 139         CARD32 fp_vvalid_start;
 140         CARD32 fp_vvalid_end;
 141         CARD8 TMDS[128];
 142 } NVOutputRegRec, *NVOutputRegPtr;
 143
 144 typedef struct _riva_hw_state
 145 {
 146     CARD32 bpp;
 147     CARD32 width;
 148     CARD32 height;
 149     CARD32 interlace;
 150     CARD32 repaint0;
 151     CARD32 repaint1;
 152     CARD32 screen;
 153     CARD32 scale;
 154     CARD32 dither;
 155     CARD32 extra;
 156     CARD32 fifo;
 157     CARD32 pixel;
 158     CARD32 horiz;
 159     CARD32 arbitration0;
 160     CARD32 arbitration1;
 161     CARD32 pll;
 162     CARD32 pllB;
 163     CARD32 vpll;
 164     CARD32 vpll2;
 165     CARD32 vpllB;
 166     CARD32 vpll2B;
 167     CARD32 pllsel;
 168         CARD32 reg580;
 169         CARD32 sel_clk;
 170         Bool crosswired;
 171     CARD32 general;
 172     CARD32 crtcOwner;
 173     CARD32 head;
 174     CARD32 head2;
 175     CARD32 config;
 176     CARD32 cursorConfig;
 177     CARD32 cursor0;
 178     CARD32 cursor1;
 179     CARD32 cursor2;
 180     CARD32 timingH;
 181     CARD32 timingV;
 182     CARD32 displayV;
 183     CARD32 crtcSync;
 184
 185     NVCrtcRegRec crtc_reg[2];
 186     NVOutputRegRec dac_reg[2];
 187 } RIVA_HW_STATE, *NVRegPtr;
 188
 189 typedef struct _nv50_crtc_reg
 190 {
 191
 192 } NV50CrtcRegRec, *NV50CrtcRegPtr;
 193
 194 typedef struct _nv50_hw_state
 195 {
 196         NV50CrtcRegRec crtc_reg[2];
 197 } NV50_HW_STATE, *NV50RegPtr;
 198
 199 typedef struct {
 200         int type;
 201         uint64_t size;
 202         uint64_t offset;
 203         void *map;
 204 } NVAllocRec;
 205
 206 typedef enum {
 207         RAMDAC_0 = (1 << 0),
 208         RAMDAC_1 = (1 << 1)
 209 } ValidRamdac;
 210
 211 typedef struct _NVOutputPrivateRec {
 212         int ramdac;
 213         Bool ramdac_assigned;
 214         uint8_t valid_ramdac;
 215         I2CBusPtr                   pDDCBus;
 216         NVOutputType type;
 217         CARD32 fpSyncs;
 218         CARD32 fpWidth;
 219         CARD32 fpHeight;
 220         DisplayModePtr native_mode;
 221         Bool fpdither;
 222 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 223
 224 typedef struct _MiscStartupInfo {
 225         CARD8 crtc_0_reg_52;
 226         CARD32 ramdac_0_reg_580;
 227         CARD32 ramdac_0_pllsel;
 228         CARD32 reg_c040;
 229         CARD32 sel_clk;
 230 } MiscStartupInfo;
 231
 232 typedef enum {
 233         OUTPUT_0_SLAVED = (1 << 0),
 234         OUTPUT_1_SLAVED = (1 << 1),
 235         OUTPUT_0_LVDS = (1 << 2),
 236         OUTPUT_1_LVDS = (1 << 3),
 237         OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
 238         OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
 239 } OutputInfo;
 240
 241 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 242
 243 typedef struct _NVRec *NVPtr;
 244 typedef struct _NVRec {
 245     RIVA_HW_STATE       SavedReg;
 246     RIVA_HW_STATE       ModeReg;
 247     RIVA_HW_STATE       *CurrentState;
 248         NV50_HW_STATE   NV50SavedReg;
 249         NV50_HW_STATE   NV50ModeReg;
 250     CARD32              Architecture;
 251     EntityInfoPtr       pEnt;
 252 #ifndef XSERVER_LIBPCIACCESS
 253         pciVideoPtr     PciInfo;
 254         PCITAG          PciTag;
 255 #else
 256         struct pci_device *PciInfo;
 257 #endif /* XSERVER_LIBPCIACCESS */
 258     int                 Chipset;
 259     int                 NVArch;
 260     Bool                Primary;
 261     CARD32              IOAddress;
 262     Bool cursorOn;
 263
 264     /* VRAM physical address */
 265     unsigned long       VRAMPhysical;
 266     /* Size of VRAM BAR */
 267     unsigned long       VRAMPhysicalSize;
 268     /* Accesible VRAM size (by the GPU) */
 269     unsigned long       VRAMSize;
 270     /* AGP physical address */
 271     unsigned long       AGPPhysical;
 272     /* Accessible AGP size */
 273     unsigned long       AGPSize;
 274     /* PCI buffer virtual address */
 275     unsigned long       SGPhysical;
 276
 277     uint32_t *          VBIOS;
 278     NVAllocRec *        FB;
 279     NVAllocRec *        Cursor;
 280     NVAllocRec *        CLUT;   /* NV50 only */
 281     NVAllocRec *        ScratchBuffer;
 282     NVAllocRec *        GARTScratch;
 283     Bool                NoAccel;
 284     Bool                HWCursor;
 285     Bool                FpScale;
 286     Bool                ShadowFB;
 287     unsigned char *     ShadowPtr;
 288     int                 ShadowPitch;
 289     CARD32              MinVClockFreqKHz;
 290     CARD32              MaxVClockFreqKHz;
 291     CARD32              CrystalFreqKHz;
 292     CARD32              RamAmountKBytes;
 293     int drm_fd;
 294
 295     volatile CARD32 *REGS;
 296     volatile CARD32 *PCRTC0;
 297     volatile CARD32 *PCRTC1;
 298
 299         volatile CARD32 *NV50_PCRTC;
 300
 301     volatile CARD32 *PRAMDAC0;
 302     volatile CARD32 *PRAMDAC1;
 303     volatile CARD32 *PFB;
 304     volatile CARD32 *PFIFO;
 305     volatile CARD32 *PGRAPH;
 306     volatile CARD32 *PEXTDEV;
 307     volatile CARD32 *PTIMER;
 308     volatile CARD32 *PVIDEO;
 309     volatile CARD32 *PMC;
 310     volatile CARD32 *PRAMIN;
 311     volatile CARD32 *FIFO;
 312     volatile CARD32 *CURSOR;
 313     volatile CARD8 *PCIO0;
 314     volatile CARD8 *PCIO1;
 315     volatile CARD8 *PVIO0;
 316     volatile CARD8 *PVIO1;
 317     volatile CARD8 *PDIO0;
 318     volatile CARD8 *PDIO1;
 319     volatile CARD8 *PROM;
 320
 321
 322     volatile CARD32 *RAMHT;
 323     CARD32 pramin_free;
 324
 325     unsigned int SaveGeneration;
 326     uint8_t cur_head;
 327     ExaDriverPtr        EXADriverPtr;
 328     xf86CursorInfoPtr   CursorInfoRec;
 329     void                (*PointerMoved)(int index, int x, int y);
 330     ScreenBlockHandlerProcPtr BlockHandler;
 331     CloseScreenProcPtr  CloseScreen;
 332     int                 Rotate;
 333     NVFBLayout          CurrentLayout;
 334     /* Cursor */
 335     CARD32              curFg, curBg;
 336     CARD32              curImage[256];
 337     /* I2C / DDC */
 338     int ddc2;
 339     xf86Int10InfoPtr    pInt10;
 340     I2CBusPtr           I2C;
 341   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 342     void                (*DMAKickoffCallback)(NVPtr pNv);
 343     XF86VideoAdaptorPtr overlayAdaptor;
 344     XF86VideoAdaptorPtr blitAdaptor;
 345     int                 videoKey;
 346     int                 FlatPanel;
 347     Bool                FPDither;
 348     int                 Mobile;
 349     Bool                Television;
 350         int         vtOWNER;
 351         Bool            crtc_active[2];
 352         Bool            ramdac_active[2];
 353     OptionInfoPtr       Options;
 354     Bool                alphaCursor;
 355     unsigned char       DDCBase;
 356     Bool                twoHeads;
 357     Bool                twoStagePLL;
 358     Bool                fpScaler;
 359     int                 fpWidth;
 360     int                 fpHeight;
 361     CARD32              fpSyncs;
 362     Bool                usePanelTweak;
 363     int                 PanelTweak;
 364     Bool                LVDS;
 365
 366     Bool                LockedUp;
 367
 368     volatile void *     NotifierBlock;
 369     struct drm_nouveau_notifierobj_alloc *Notifier0;
 370
 371     struct drm_nouveau_channel_alloc fifo;
 372     CARD32              dmaPut;
 373     CARD32              dmaCurrent;
 374     CARD32              dmaFree;
 375     CARD32              dmaMax;
 376     CARD32              *dmaBase;
 377
 378     CARD32              currentRop;
 379     int                 M2MFDirection;
 380
 381     Bool                WaitVSyncPossible;
 382     Bool                BlendingPossible;
 383     Bool                RandRRotation;
 384     DRIInfoPtr          pDRIInfo;
 385     drmVersionPtr       pLibDRMVersion;
 386     drmVersionPtr       pKernelDRMVersion;
 387
 388     Bool randr12_enable;
 389     CreateScreenResourcesProcPtr    CreateScreenResources;
 390
 391     I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
 392
 393         int vga_count;
 394         int dvi_d_count;
 395         int dvi_a_count;
 396         int lvds_count;
 397
 398     struct {
 399             int entries;
 400             int i2c_entries;
 401             int version;
 402             uint32_t connection[MAX_NUM_DCB_ENTRIES];
 403             uint32_t config[MAX_NUM_DCB_ENTRIES];
 404             unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
 405             unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
 406     } dcb_table;
 407
 408     uint32_t output_info;
 409     MiscStartupInfo misc_info;
 410
 411     DisplayModePtr fp_native_mode;
 412
 413     struct {
 414             ORNum dac;
 415             ORNum sor;
 416     } i2cMap[4];
 417     struct {
 418             Bool  present;
 419             ORNum or;
 420     } lvds;
 421 } NVRec;
 422
 423 typedef struct _NVCrtcPrivateRec {
 424         int crtc;
 425         int head;
 426         Bool paletteEnabled;
 427 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 428
 429 typedef struct _NV50CrtcPrivRec {
 430         int head;
 431         int pclk; /* Target pixel clock in kHz */
 432         Bool cursorVisible;
 433         Bool skipModeFixup;
 434         Bool dither;
 435 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
 436
 437 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 438
 439 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 440
 441 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
 442 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
 443
 444 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
 445 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 446
 447 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
 448 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
 449
 450 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
 451 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
 452
 453 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
 454 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
 455
 456 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
 457 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
 458
 459 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
 460 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
 461
 462 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
 463 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
 464
 465 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
 466 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
 467
 468 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
 469 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
 470
 471 #endif /* __NV_STRUCT_H__ */