1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
3 #ifndef __NV_STRUCT_H__
4 #define __NV_STRUCT_H__
6 #include "colormapst.h"
9 #include "xf86Cursor.h"
10 #include "xf86int10.h"
13 #define _XF86DRI_SERVER_
17 #include "nouveau_drm.h"
20 #error "This driver requires a DRI-enabled X server"
23 #include "nv50_type.h"
24 #include "nv_pcicompat.h"
26 #define NV_ARCH_03 0x03
27 #define NV_ARCH_04 0x04
28 #define NV_ARCH_10 0x10
29 #define NV_ARCH_20 0x20
30 #define NV_ARCH_30 0x30
31 #define NV_ARCH_40 0x40
32 #define NV_ARCH_50 0x50
34 #define CHIPSET_NV03 0x0010
35 #define CHIPSET_NV04 0x0020
36 #define CHIPSET_NV10 0x0100
37 #define CHIPSET_NV11 0x0110
38 #define CHIPSET_NV15 0x0150
39 #define CHIPSET_NV17 0x0170
40 #define CHIPSET_NV18 0x0180
41 #define CHIPSET_NFORCE 0x01A0
42 #define CHIPSET_NFORCE2 0x01F0
43 #define CHIPSET_NV20 0x0200
44 #define CHIPSET_NV25 0x0250
45 #define CHIPSET_NV28 0x0280
46 #define CHIPSET_NV30 0x0300
47 #define CHIPSET_NV31 0x0310
48 #define CHIPSET_NV34 0x0320
49 #define CHIPSET_NV35 0x0330
50 #define CHIPSET_NV36 0x0340
51 #define CHIPSET_NV40 0x0040
52 #define CHIPSET_NV41 0x00C0
53 #define CHIPSET_NV43 0x0140
54 #define CHIPSET_NV44 0x0160
55 #define CHIPSET_NV44A 0x0220
56 #define CHIPSET_NV45 0x0210
57 #define CHIPSET_NV50 0x0190
58 #define CHIPSET_NV84 0x0400
59 #define CHIPSET_MISC_BRIDGED 0x00F0
60 #define CHIPSET_G70 0x0090
61 #define CHIPSET_G71 0x0290
62 #define CHIPSET_G72 0x01D0
63 #define CHIPSET_G73 0x0390
64 // integrated GeForces (6100, 6150)
65 #define CHIPSET_C51 0x0240
66 // variant of C51, seems based on a G70 design
67 #define CHIPSET_C512 0x03D0
68 #define CHIPSET_G73_BRIDGED 0x02E0
71 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
72 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
73 #define SetBF(mask,value) ((value) << (0?mask))
74 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
75 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
76 #define SetBit(n) (1<<(n))
77 #define Set8Bits(value) ((value)&0xff)
80 #define NV_I2C_BUSES 3
81 #define NV40_NUM_DCB_ENTRIES 10
100 typedef struct _nv_crtc_reg
102 unsigned char MiscOutReg; /* */
107 unsigned char DAC[768]; /* Internal Colorlookuptable */
113 } NVCrtcRegRec, *NVCrtcRegPtr;
115 typedef struct _nv_output_reg
127 CARD32 fp_horiz_regs[7];
128 CARD32 fp_vert_regs[7];
129 CARD32 fp_hvalid_start;
130 CARD32 fp_hvalid_end;
131 CARD32 fp_vvalid_start;
132 CARD32 fp_vvalid_end;
133 } NVOutputRegRec, *NVOutputRegPtr;
135 typedef struct _riva_hw_state
173 NVCrtcRegRec crtc_reg[2];
174 NVOutputRegRec dac_reg[2];
175 } RIVA_HW_STATE, *NVRegPtr;
184 typedef struct _NVOutputPrivateRec {
192 } NVOutputPrivateRec, *NVOutputPrivatePtr;
194 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
196 typedef struct _NVRec *NVPtr;
197 typedef struct _NVRec {
198 RIVA_HW_STATE SavedReg;
199 RIVA_HW_STATE ModeReg;
200 RIVA_HW_STATE *CurrentState;
203 #ifndef XSERVER_LIBPCIACCESS
207 struct pci_device *PciInfo;
208 #endif /* XSERVER_LIBPCIACCESS */
215 /* VRAM physical address */
216 unsigned long VRAMPhysical;
217 /* Size of VRAM BAR */
218 unsigned long VRAMPhysicalSize;
219 /* Accesible VRAM size (by the GPU) */
220 unsigned long VRAMSize;
221 /* AGP physical address */
222 unsigned long AGPPhysical;
223 /* Accessible AGP size */
224 unsigned long AGPSize;
225 /* PCI buffer virtual address */
226 unsigned long SGPhysical;
230 NVAllocRec * CLUT; /* NV50 only */
231 NVAllocRec * ScratchBuffer;
232 NVAllocRec * GARTScratch;
237 unsigned char * ShadowPtr;
239 CARD32 MinVClockFreqKHz;
240 CARD32 MaxVClockFreqKHz;
241 CARD32 CrystalFreqKHz;
242 CARD32 RamAmountKBytes;
245 volatile CARD32 *REGS;
246 volatile CARD32 *PCRTC0;
247 volatile CARD32 *PCRTC1;
249 volatile CARD32 *PRAMDAC0;
250 volatile CARD32 *PRAMDAC1;
251 volatile CARD32 *PFB;
252 volatile CARD32 *PFIFO;
253 volatile CARD32 *PGRAPH;
254 volatile CARD32 *PEXTDEV;
255 volatile CARD32 *PTIMER;
256 volatile CARD32 *PVIDEO;
257 volatile CARD32 *PMC;
258 volatile CARD32 *PRAMIN;
259 volatile CARD32 *FIFO;
260 volatile CARD32 *CURSOR;
261 volatile CARD8 *PCIO0;
262 volatile CARD8 *PCIO1;
263 volatile CARD8 *PVIO;
264 volatile CARD8 *PDIO0;
265 volatile CARD8 *PDIO1;
266 volatile CARD8 *PROM;
269 volatile CARD32 *RAMHT;
272 unsigned int SaveGeneration;
274 ExaDriverPtr EXADriverPtr;
275 xf86CursorInfoPtr CursorInfoRec;
276 void (*PointerMoved)(int index, int x, int y);
277 ScreenBlockHandlerProcPtr BlockHandler;
278 CloseScreenProcPtr CloseScreen;
280 NVFBLayout CurrentLayout;
283 CARD32 curImage[256];
286 xf86Int10InfoPtr pInt10;
288 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
289 void (*DMAKickoffCallback)(NVPtr pNv);
290 XF86VideoAdaptorPtr overlayAdaptor;
291 XF86VideoAdaptorPtr blitAdaptor;
299 OptionInfoPtr Options;
301 unsigned char DDCBase;
314 volatile void * NotifierBlock;
315 struct drm_nouveau_notifierobj_alloc *Notifier0;
317 struct drm_nouveau_channel_alloc fifo;
327 Bool WaitVSyncPossible;
328 Bool BlendingPossible;
331 drmVersionPtr pLibDRMVersion;
332 drmVersionPtr pKernelDRMVersion;
335 CreateScreenResourcesProcPtr CreateScreenResources;
337 /* we know about 3 i2c buses */
338 I2CBusPtr pI2CBus[3];
343 CARD32 dcb_table[NV40_NUM_DCB_ENTRIES]; /* 10 is a good limit */
351 typedef struct _NVCrtcPrivateRec {
355 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
357 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
359 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
361 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
362 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
364 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
365 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
367 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
368 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
370 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
371 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
373 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
374 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
376 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
377 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
379 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
380 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
382 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
383 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
385 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
386 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
388 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
389 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
391 #endif /* __NV_STRUCT_H__ */