1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
3 #ifndef __NV_STRUCT_H__
4 #define __NV_STRUCT_H__
6 #include "colormapst.h"
8 #include "xf86Cursor.h"
12 #define _XF86DRI_SERVER_
16 #include "nouveau_drm.h"
19 #error "This driver requires a DRI-enabled X server"
22 #include "nv50_type.h"
23 #include "nv_pcicompat.h"
25 #include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
27 #define NV_ARCH_03 0x03
28 #define NV_ARCH_04 0x04
29 #define NV_ARCH_10 0x10
30 #define NV_ARCH_20 0x20
31 #define NV_ARCH_30 0x30
32 #define NV_ARCH_40 0x40
33 #define NV_ARCH_50 0x50
35 #define CHIPSET_NV03 0x0010
36 #define CHIPSET_NV04 0x0020
37 #define CHIPSET_NV10 0x0100
38 #define CHIPSET_NV11 0x0110
39 #define CHIPSET_NV15 0x0150
40 #define CHIPSET_NV17 0x0170
41 #define CHIPSET_NV18 0x0180
42 #define CHIPSET_NFORCE 0x01A0
43 #define CHIPSET_NFORCE2 0x01F0
44 #define CHIPSET_NV20 0x0200
45 #define CHIPSET_NV25 0x0250
46 #define CHIPSET_NV28 0x0280
47 #define CHIPSET_NV30 0x0300
48 #define CHIPSET_NV31 0x0310
49 #define CHIPSET_NV34 0x0320
50 #define CHIPSET_NV35 0x0330
51 #define CHIPSET_NV36 0x0340
52 #define CHIPSET_NV40 0x0040
53 #define CHIPSET_NV41 0x00C0
54 #define CHIPSET_NV43 0x0140
55 #define CHIPSET_NV44 0x0160
56 #define CHIPSET_NV44A 0x0220
57 #define CHIPSET_NV45 0x0210
58 #define CHIPSET_NV50 0x0190
59 #define CHIPSET_NV84 0x0400
60 #define CHIPSET_MISC_BRIDGED 0x00F0
61 #define CHIPSET_G70 0x0090
62 #define CHIPSET_G71 0x0290
63 #define CHIPSET_G72 0x01D0
64 #define CHIPSET_G73 0x0390
65 // integrated GeForces (6100, 6150)
66 #define CHIPSET_C51 0x0240
67 // variant of C51, seems based on a G70 design
68 #define CHIPSET_C512 0x03D0
69 #define CHIPSET_G73_BRIDGED 0x02E0
72 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
73 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
74 #define SetBF(mask,value) ((value) << (0?mask))
75 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
76 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
77 #define SetBit(n) (1<<(n))
78 #define Set8Bits(value) ((value)&0xff)
80 #define MAX_NUM_DCB_ENTRIES 16
82 typedef enum /* matches DCB types */
99 typedef struct _nv_crtc_reg
101 unsigned char MiscOutReg; /* */
104 uint8_t Sequencer[5];
106 uint8_t Attribute[21];
107 unsigned char DAC[768]; /* Internal Colorlookuptable */
108 uint32_t cursorConfig;
118 /* These are former output regs, but are believed to be crtc related */
126 uint32_t fp_horiz_regs[7];
127 uint32_t fp_vert_regs[7];
128 uint32_t fp_hvalid_start;
129 uint32_t fp_hvalid_end;
130 uint32_t fp_vvalid_start;
131 uint32_t fp_vvalid_end;
133 uint32_t nv10_cursync;
137 } NVCrtcRegRec, *NVCrtcRegPtr;
139 typedef struct _nv_output_reg
141 uint32_t test_control;
147 } NVOutputRegRec, *NVOutputRegPtr;
149 typedef struct _riva_hw_state
176 /* These vpll values are only for nv4x hardware */
197 NVCrtcRegRec crtc_reg[2];
198 NVOutputRegRec dac_reg[2];
199 } RIVA_HW_STATE, *NVRegPtr;
201 typedef struct _nv50_crtc_reg
204 } NV50CrtcRegRec, *NV50CrtcRegPtr;
206 typedef struct _nv50_hw_state
208 NV50CrtcRegRec crtc_reg[2];
209 } NV50_HW_STATE, *NV50RegPtr;
214 } ValidOutputResource;
216 typedef struct _NVOutputPrivateRec {
217 uint8_t preferred_output;
218 uint8_t output_resource;
226 DisplayModePtr native_mode;
228 uint8_t scaling_mode;
229 } NVOutputPrivateRec, *NVOutputPrivatePtr;
231 typedef struct _MiscStartupInfo {
232 uint8_t crtc_0_reg_52;
233 uint32_t ramdac_0_reg_580;
234 uint32_t ramdac_0_pllsel;
241 OUTPUT_0_SLAVED = (1 << 0),
242 OUTPUT_1_SLAVED = (1 << 1),
243 OUTPUT_0_LVDS = (1 << 2),
244 OUTPUT_1_LVDS = (1 << 3),
245 OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
246 OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
256 Bool duallink_possible;
259 Bool use_straps_for_mode;
260 Bool use_power_scripts;
272 /* nv3x needs 32 bit values */
275 uint32_t min_inputfreq;
276 uint16_t max_inputfreq;
294 uint8_t major_version, chip_version;
296 uint32_t fmaxvco, fminvco;
298 uint16_t init_script_tbls_ptr;
299 uint16_t extra_init_script_tbl_ptr;
300 uint16_t macro_index_tbl_ptr;
301 uint16_t macro_tbl_ptr;
302 uint16_t condition_tbl_ptr;
303 uint16_t io_condition_tbl_ptr;
304 uint16_t io_flag_condition_tbl_ptr;
305 uint16_t init_function_tbl_ptr;
307 uint16_t pll_limit_tbl_ptr;
308 uint16_t ram_restrict_tbl_ptr;
311 DisplayModePtr native_mode;
312 uint16_t lvdsmanufacturerpointer;
313 uint16_t xlated_entry;
320 uint16_t output0_script_ptr;
321 uint16_t output1_script_ptr;
325 uint8_t crt, tv, panel;
326 } legacy_i2c_indices;
330 /* Order *does* matter here */
339 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
341 typedef struct _NVRec *NVPtr;
342 typedef struct _NVRec {
343 RIVA_HW_STATE SavedReg;
344 RIVA_HW_STATE ModeReg;
345 RIVA_HW_STATE *CurrentState;
346 NV50_HW_STATE NV50SavedReg;
347 NV50_HW_STATE NV50ModeReg;
348 uint32_t Architecture;
350 #ifndef XSERVER_LIBPCIACCESS
354 struct pci_device *PciInfo;
355 #endif /* XSERVER_LIBPCIACCESS */
362 /* VRAM physical address */
363 unsigned long VRAMPhysical;
364 /* Size of VRAM BAR */
365 unsigned long VRAMPhysicalSize;
366 /* Accesible VRAM size (by the GPU) */
367 unsigned long VRAMSize;
368 /* Accessible AGP size */
369 unsigned long AGPSize;
371 /* Various pinned memory regions */
372 struct nouveau_bo * FB;
373 struct nouveau_bo * Cursor;
374 struct nouveau_bo * Cursor2;
375 struct nouveau_bo * CLUT; /* NV50 only */
376 struct nouveau_bo * GART;
383 unsigned char * ShadowPtr;
385 CARD32 MinVClockFreqKHz;
386 CARD32 MaxVClockFreqKHz;
387 CARD32 CrystalFreqKHz;
388 CARD32 RamAmountKBytes;
390 volatile CARD32 *REGS;
391 volatile CARD32 *PCRTC0;
392 volatile CARD32 *PCRTC1;
394 volatile CARD32 *NV50_PCRTC;
396 volatile CARD32 *PRAMDAC0;
397 volatile CARD32 *PRAMDAC1;
398 volatile CARD32 *PFB;
399 volatile CARD32 *PFIFO;
400 volatile CARD32 *PGRAPH;
401 volatile CARD32 *PEXTDEV;
402 volatile CARD32 *PTIMER;
403 volatile CARD32 *PVIDEO;
404 volatile CARD32 *PMC;
405 volatile CARD32 *PRAMIN;
406 volatile CARD32 *CURSOR;
407 volatile CARD8 *PCIO0;
408 volatile CARD8 *PCIO1;
409 volatile CARD8 *PVIO0;
410 volatile CARD8 *PVIO1;
411 volatile CARD8 *PDIO0;
412 volatile CARD8 *PDIO1;
413 volatile CARD8 *PROM;
416 volatile CARD32 *RAMHT;
419 unsigned int SaveGeneration;
421 ExaDriverPtr EXADriverPtr;
422 xf86CursorInfoPtr CursorInfoRec;
423 void (*PointerMoved)(int index, int x, int y);
424 ScreenBlockHandlerProcPtr BlockHandler;
425 CloseScreenProcPtr CloseScreen;
427 NVFBLayout CurrentLayout;
430 CARD32 curImage[256];
433 xf86Int10InfoPtr pInt10;
435 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
436 XF86VideoAdaptorPtr overlayAdaptor;
437 XF86VideoAdaptorPtr blitAdaptor;
438 XF86VideoAdaptorPtr textureAdaptor;
446 OptionInfoPtr Options;
448 unsigned char DDCBase;
463 Bool WaitVSyncPossible;
464 Bool BlendingPossible;
467 drmVersionPtr pLibDRMVersion;
468 drmVersionPtr pKernelDRMVersion;
471 CreateScreenResourcesProcPtr CreateScreenResources;
473 I2CBusPtr pI2CBus[MAX_NUM_DCB_ENTRIES];
480 /* Is our secondary (analog) output not flexible (ffs(or) != 3)? */
481 Bool restricted_mode;
482 Bool switchable_crtc;
486 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
487 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
488 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
491 uint32_t output_info;
492 MiscStartupInfo misc_info;
504 struct nouveau_device *dev;
507 struct nouveau_channel *chan;
508 struct nouveau_notifier *notify0;
509 struct nouveau_grobj *NvNull;
510 struct nouveau_grobj *NvContextSurfaces;
511 struct nouveau_grobj *NvContextBeta1;
512 struct nouveau_grobj *NvContextBeta4;
513 struct nouveau_grobj *NvImagePattern;
514 struct nouveau_grobj *NvRop;
515 struct nouveau_grobj *NvRectangle;
516 struct nouveau_grobj *NvImageBlit;
517 struct nouveau_grobj *NvScaledImage;
518 struct nouveau_grobj *NvClipRectangle;
519 struct nouveau_grobj *NvMemFormat;
520 struct nouveau_grobj *NvImageFromCpu;
521 struct nouveau_grobj *Nv2D;
522 struct nouveau_grobj *Nv3D;
526 typedef struct _NVCrtcPrivateRec {
530 #if NOUVEAU_EXA_PIXMAPS
531 struct nouveau_bo *shadow;
533 ExaOffscreenArea *shadow;
534 #endif /* NOUVEAU_EXA_PIXMAPS */
535 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
537 typedef struct _NV50CrtcPrivRec {
539 int pclk; /* Target pixel clock in kHz */
543 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
553 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
555 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
557 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
558 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
560 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
561 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
563 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
564 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
566 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
567 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
569 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
570 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
572 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
573 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
575 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
576 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
578 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
579 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
581 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
582 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
584 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
585 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
587 #endif /* __NV_STRUCT_H__ */