1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
3 #ifndef __NV_STRUCT_H__
4 #define __NV_STRUCT_H__
6 #include "colormapst.h"
8 #include "xf86Cursor.h"
12 #define _XF86DRI_SERVER_
16 #include "nouveau_drm.h"
19 #error "This driver requires a DRI-enabled X server"
22 #include "nv50_type.h"
23 #include "nv_pcicompat.h"
25 #include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
27 #define NV_ARCH_03 0x03
28 #define NV_ARCH_04 0x04
29 #define NV_ARCH_10 0x10
30 #define NV_ARCH_20 0x20
31 #define NV_ARCH_30 0x30
32 #define NV_ARCH_40 0x40
33 #define NV_ARCH_50 0x50
35 #define CHIPSET_NV03 0x0010
36 #define CHIPSET_NV04 0x0020
37 #define CHIPSET_NV10 0x0100
38 #define CHIPSET_NV11 0x0110
39 #define CHIPSET_NV15 0x0150
40 #define CHIPSET_NV17 0x0170
41 #define CHIPSET_NV18 0x0180
42 #define CHIPSET_NFORCE 0x01A0
43 #define CHIPSET_NFORCE2 0x01F0
44 #define CHIPSET_NV20 0x0200
45 #define CHIPSET_NV25 0x0250
46 #define CHIPSET_NV28 0x0280
47 #define CHIPSET_NV30 0x0300
48 #define CHIPSET_NV31 0x0310
49 #define CHIPSET_NV34 0x0320
50 #define CHIPSET_NV35 0x0330
51 #define CHIPSET_NV36 0x0340
52 #define CHIPSET_NV40 0x0040
53 #define CHIPSET_NV41 0x00C0
54 #define CHIPSET_NV43 0x0140
55 #define CHIPSET_NV44 0x0160
56 #define CHIPSET_NV44A 0x0220
57 #define CHIPSET_NV45 0x0210
58 #define CHIPSET_NV50 0x0190
59 #define CHIPSET_NV84 0x0400
60 #define CHIPSET_MISC_BRIDGED 0x00F0
61 #define CHIPSET_G70 0x0090
62 #define CHIPSET_G71 0x0290
63 #define CHIPSET_G72 0x01D0
64 #define CHIPSET_G73 0x0390
65 // integrated GeForces (6100, 6150)
66 #define CHIPSET_C51 0x0240
67 // variant of C51, seems based on a G70 design
68 #define CHIPSET_C512 0x03D0
69 #define CHIPSET_G73_BRIDGED 0x02E0
72 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
73 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
74 #define SetBF(mask,value) ((value) << (0?mask))
75 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
76 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
77 #define SetBit(n) (1<<(n))
78 #define Set8Bits(value) ((value)&0xff)
80 #define MAX_NUM_DCB_ENTRIES 16
82 typedef enum /* matches DCB types */
99 typedef struct _nv_crtc_reg
101 unsigned char MiscOutReg; /* */
104 uint8_t Sequencer[5];
106 uint8_t Attribute[21];
107 unsigned char DAC[768]; /* Internal Colorlookuptable */
108 uint32_t cursorConfig;
118 /* These are former output regs, but are believed to be crtc related */
126 uint32_t fp_horiz_regs[7];
127 uint32_t fp_vert_regs[7];
128 uint32_t fp_hvalid_start;
129 uint32_t fp_hvalid_end;
130 uint32_t fp_vvalid_start;
131 uint32_t fp_vvalid_end;
133 uint32_t nv10_cursync;
134 uint32_t fp_control[2];
137 } NVCrtcRegRec, *NVCrtcRegPtr;
139 typedef struct _nv_output_reg
141 uint32_t test_control;
147 } NVOutputRegRec, *NVOutputRegPtr;
149 typedef struct _riva_hw_state
175 Bool vpll_changed[2];
177 /* These vpll values are only for nv4x hardware */
198 NVCrtcRegRec crtc_reg[2];
199 NVOutputRegRec dac_reg[2];
200 } RIVA_HW_STATE, *NVRegPtr;
202 typedef struct _nv50_crtc_reg
205 } NV50CrtcRegRec, *NV50CrtcRegPtr;
207 typedef struct _nv50_hw_state
209 NV50CrtcRegRec crtc_reg[2];
210 } NV50_HW_STATE, *NV50RegPtr;
215 } ValidOutputResource;
217 typedef struct _NVOutputPrivateRec {
218 uint8_t preferred_output;
219 uint8_t output_resource;
227 DisplayModePtr native_mode;
229 uint8_t scaling_mode;
230 } NVOutputPrivateRec, *NVOutputPrivatePtr;
232 typedef struct _MiscStartupInfo {
233 uint8_t crtc_0_reg_52;
234 uint32_t ramdac_0_reg_580;
235 uint32_t ramdac_0_pllsel;
242 OUTPUT_0_SLAVED = (1 << 0),
243 OUTPUT_1_SLAVED = (1 << 1),
244 OUTPUT_0_LVDS = (1 << 2),
245 OUTPUT_1_LVDS = (1 << 3),
246 OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
247 OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
257 Bool duallink_possible;
260 Bool use_straps_for_mode;
261 Bool use_power_scripts;
273 /* nv3x needs 32 bit values */
276 uint32_t min_inputfreq;
277 uint16_t max_inputfreq;
295 uint8_t major_version, chip_version;
297 uint32_t fmaxvco, fminvco;
299 uint16_t init_script_tbls_ptr;
300 uint16_t extra_init_script_tbl_ptr;
301 uint16_t macro_index_tbl_ptr;
302 uint16_t macro_tbl_ptr;
303 uint16_t condition_tbl_ptr;
304 uint16_t io_condition_tbl_ptr;
305 uint16_t io_flag_condition_tbl_ptr;
306 uint16_t init_function_tbl_ptr;
308 uint16_t pll_limit_tbl_ptr;
309 uint16_t ram_restrict_tbl_ptr;
312 DisplayModePtr native_mode;
314 uint16_t lvdsmanufacturerpointer;
315 uint16_t xlated_entry;
322 uint16_t output0_script_ptr;
323 uint16_t output1_script_ptr;
327 uint8_t crt, tv, panel;
328 } legacy_i2c_indices;
332 /* Order *does* matter here */
341 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
343 typedef struct _NVRec *NVPtr;
344 typedef struct _NVRec {
345 RIVA_HW_STATE SavedReg;
346 RIVA_HW_STATE ModeReg;
347 RIVA_HW_STATE *CurrentState;
348 NV50_HW_STATE NV50SavedReg;
349 NV50_HW_STATE NV50ModeReg;
350 uint32_t Architecture;
352 #ifndef XSERVER_LIBPCIACCESS
356 struct pci_device *PciInfo;
357 #endif /* XSERVER_LIBPCIACCESS */
364 /* VRAM physical address */
365 unsigned long VRAMPhysical;
366 /* Size of VRAM BAR */
367 unsigned long VRAMPhysicalSize;
368 /* Accesible VRAM size (by the GPU) */
369 unsigned long VRAMSize;
370 /* Accessible AGP size */
371 unsigned long AGPSize;
373 /* Various pinned memory regions */
374 struct nouveau_bo * FB;
375 struct nouveau_bo * Cursor;
376 struct nouveau_bo * Cursor2;
377 struct nouveau_bo * CLUT; /* NV50 only */
378 struct nouveau_bo * GART;
385 unsigned char * ShadowPtr;
387 CARD32 MinVClockFreqKHz;
388 CARD32 MaxVClockFreqKHz;
389 CARD32 CrystalFreqKHz;
390 CARD32 RamAmountKBytes;
392 volatile CARD32 *REGS;
393 volatile CARD32 *PCRTC0;
394 volatile CARD32 *PCRTC1;
396 volatile CARD32 *NV50_PCRTC;
398 volatile CARD32 *PRAMDAC0;
399 volatile CARD32 *PRAMDAC1;
400 volatile CARD32 *PFB;
401 volatile CARD32 *PFIFO;
402 volatile CARD32 *PGRAPH;
403 volatile CARD32 *PEXTDEV;
404 volatile CARD32 *PTIMER;
405 volatile CARD32 *PVIDEO;
406 volatile CARD32 *PMC;
407 volatile CARD32 *PRAMIN;
408 volatile CARD32 *CURSOR;
409 volatile CARD8 *PCIO0;
410 volatile CARD8 *PCIO1;
411 volatile CARD8 *PVIO0;
412 volatile CARD8 *PVIO1;
413 volatile CARD8 *PDIO0;
414 volatile CARD8 *PDIO1;
415 volatile CARD8 *PROM;
418 volatile CARD32 *RAMHT;
421 unsigned int SaveGeneration;
423 ExaDriverPtr EXADriverPtr;
424 xf86CursorInfoPtr CursorInfoRec;
425 void (*PointerMoved)(int index, int x, int y);
426 ScreenBlockHandlerProcPtr BlockHandler;
427 CloseScreenProcPtr CloseScreen;
429 NVFBLayout CurrentLayout;
432 CARD32 curImage[256];
435 xf86Int10InfoPtr pInt10;
437 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
438 XF86VideoAdaptorPtr overlayAdaptor;
439 XF86VideoAdaptorPtr blitAdaptor;
440 XF86VideoAdaptorPtr textureAdaptor;
448 OptionInfoPtr Options;
450 unsigned char DDCBase;
465 Bool WaitVSyncPossible;
466 Bool BlendingPossible;
469 drmVersionPtr pLibDRMVersion;
470 drmVersionPtr pKernelDRMVersion;
473 CreateScreenResourcesProcPtr CreateScreenResources;
475 I2CBusPtr pI2CBus[MAX_NUM_DCB_ENTRIES];
482 /* Is our secondary (analog) output not flexible (ffs(or) != 3)? */
483 Bool restricted_mode;
484 Bool switchable_crtc;
486 uint8_t fp_regs_owner[2];
490 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
491 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
492 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
495 uint32_t output_info;
496 MiscStartupInfo misc_info;
508 struct nouveau_device *dev;
511 struct nouveau_channel *chan;
512 struct nouveau_notifier *notify0;
513 struct nouveau_grobj *NvNull;
514 struct nouveau_grobj *NvContextSurfaces;
515 struct nouveau_grobj *NvContextBeta1;
516 struct nouveau_grobj *NvContextBeta4;
517 struct nouveau_grobj *NvImagePattern;
518 struct nouveau_grobj *NvRop;
519 struct nouveau_grobj *NvRectangle;
520 struct nouveau_grobj *NvImageBlit;
521 struct nouveau_grobj *NvScaledImage;
522 struct nouveau_grobj *NvClipRectangle;
523 struct nouveau_grobj *NvMemFormat;
524 struct nouveau_grobj *NvImageFromCpu;
525 struct nouveau_grobj *Nv2D;
526 struct nouveau_grobj *Nv3D;
530 typedef struct _NVCrtcPrivateRec {
534 #if NOUVEAU_EXA_PIXMAPS
535 struct nouveau_bo *shadow;
537 ExaOffscreenArea *shadow;
538 #endif /* NOUVEAU_EXA_PIXMAPS */
539 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
541 typedef struct _NV50CrtcPrivRec {
543 int pclk; /* Target pixel clock in kHz */
547 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
557 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
559 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
561 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
562 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
564 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
565 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
567 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
568 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
570 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
571 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
573 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
574 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
576 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
577 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
579 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
580 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
582 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
583 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
585 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
586 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
588 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
589 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
591 typedef struct _NVPortPrivRec {
598 Bool autopaintColorKey;
609 struct nouveau_bo *video_mem;
612 struct nouveau_bo *TT_mem_chunk[2];
613 int currentHostBuffer;
614 struct nouveau_notifier *DMANotifier[2];
615 } NVPortPrivRec, *NVPortPrivPtr;
617 #endif /* __NV_STRUCT_H__ */