1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
3 #ifndef __NV_STRUCT_H__
4 #define __NV_STRUCT_H__
6 #include "colormapst.h"
9 #include "xf86Cursor.h"
10 #include "xf86int10.h"
13 #define _XF86DRI_SERVER_
17 #include "nouveau_drm.h"
22 #error "This driver requires a DRI-enabled X server"
25 #include "nv50_type.h"
26 #include "nv_pcicompat.h"
28 #define NV_ARCH_03 0x03
29 #define NV_ARCH_04 0x04
30 #define NV_ARCH_10 0x10
31 #define NV_ARCH_20 0x20
32 #define NV_ARCH_30 0x30
33 #define NV_ARCH_40 0x40
34 #define NV_ARCH_50 0x50
36 #define CHIPSET_NV03 0x0010
37 #define CHIPSET_NV04 0x0020
38 #define CHIPSET_NV10 0x0100
39 #define CHIPSET_NV11 0x0110
40 #define CHIPSET_NV15 0x0150
41 #define CHIPSET_NV17 0x0170
42 #define CHIPSET_NV18 0x0180
43 #define CHIPSET_NFORCE 0x01A0
44 #define CHIPSET_NFORCE2 0x01F0
45 #define CHIPSET_NV20 0x0200
46 #define CHIPSET_NV25 0x0250
47 #define CHIPSET_NV28 0x0280
48 #define CHIPSET_NV30 0x0300
49 #define CHIPSET_NV31 0x0310
50 #define CHIPSET_NV34 0x0320
51 #define CHIPSET_NV35 0x0330
52 #define CHIPSET_NV36 0x0340
53 #define CHIPSET_NV40 0x0040
54 #define CHIPSET_NV41 0x00C0
55 #define CHIPSET_NV43 0x0140
56 #define CHIPSET_NV44 0x0160
57 #define CHIPSET_NV44A 0x0220
58 #define CHIPSET_NV45 0x0210
59 #define CHIPSET_NV50 0x0190
60 #define CHIPSET_NV84 0x0400
61 #define CHIPSET_MISC_BRIDGED 0x00F0
62 #define CHIPSET_G70 0x0090
63 #define CHIPSET_G71 0x0290
64 #define CHIPSET_G72 0x01D0
65 #define CHIPSET_G73 0x0390
66 // integrated GeForces (6100, 6150)
67 #define CHIPSET_C51 0x0240
68 // variant of C51, seems based on a G70 design
69 #define CHIPSET_C512 0x03D0
70 #define CHIPSET_G73_BRIDGED 0x02E0
73 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
74 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
75 #define SetBF(mask,value) ((value) << (0?mask))
76 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
77 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
78 #define SetBit(n) (1<<(n))
79 #define Set8Bits(value) ((value)&0xff)
82 #define NV_I2C_BUSES 3
83 #define NV40_NUM_DCB_ENTRIES 10
102 typedef struct _nv_crtc_reg
104 unsigned char MiscOutReg; /* */
109 unsigned char DAC[768]; /* Internal Colorlookuptable */
115 } NVCrtcRegRec, *NVCrtcRegPtr;
117 typedef struct _nv_output_reg
129 CARD32 fp_horiz_regs[7];
130 CARD32 fp_vert_regs[7];
131 CARD32 fp_hvalid_start;
132 CARD32 fp_hvalid_end;
133 CARD32 fp_vvalid_start;
134 CARD32 fp_vvalid_end;
136 } NVOutputRegRec, *NVOutputRegPtr;
138 typedef struct _riva_hw_state
176 NVCrtcRegRec crtc_reg[2];
177 NVOutputRegRec dac_reg[2];
178 } RIVA_HW_STATE, *NVRegPtr;
187 typedef struct _NVOutputPrivateRec {
195 } NVOutputPrivateRec, *NVOutputPrivatePtr;
197 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
199 typedef struct _NVRec *NVPtr;
200 typedef struct _NVRec {
201 RIVA_HW_STATE SavedReg;
202 RIVA_HW_STATE ModeReg;
203 RIVA_HW_STATE *CurrentState;
206 #ifndef XSERVER_LIBPCIACCESS
210 struct pci_device *PciInfo;
211 #endif /* XSERVER_LIBPCIACCESS */
218 /* VRAM physical address */
219 unsigned long VRAMPhysical;
220 /* Size of VRAM BAR */
221 unsigned long VRAMPhysicalSize;
222 /* Accesible VRAM size (by the GPU) */
223 unsigned long VRAMSize;
224 /* AGP physical address */
225 unsigned long AGPPhysical;
226 /* Accessible AGP size */
227 unsigned long AGPSize;
228 /* PCI buffer virtual address */
229 unsigned long SGPhysical;
234 NVAllocRec * CLUT; /* NV50 only */
235 NVAllocRec * ScratchBuffer;
236 NVAllocRec * GARTScratch;
241 unsigned char * ShadowPtr;
243 CARD32 MinVClockFreqKHz;
244 CARD32 MaxVClockFreqKHz;
245 CARD32 CrystalFreqKHz;
246 CARD32 RamAmountKBytes;
249 volatile CARD32 *REGS;
250 volatile CARD32 *PCRTC0;
251 volatile CARD32 *PCRTC1;
253 volatile CARD32 *PRAMDAC0;
254 volatile CARD32 *PRAMDAC1;
255 volatile CARD32 *PFB;
256 volatile CARD32 *PFIFO;
257 volatile CARD32 *PGRAPH;
258 volatile CARD32 *PEXTDEV;
259 volatile CARD32 *PTIMER;
260 volatile CARD32 *PVIDEO;
261 volatile CARD32 *PMC;
262 volatile CARD32 *PRAMIN;
263 volatile CARD32 *FIFO;
264 volatile CARD32 *CURSOR;
265 volatile CARD8 *PCIO0;
266 volatile CARD8 *PCIO1;
267 volatile CARD8 *PVIO;
268 volatile CARD8 *PDIO0;
269 volatile CARD8 *PDIO1;
270 volatile CARD8 *PROM;
273 volatile CARD32 *RAMHT;
276 unsigned int SaveGeneration;
278 ExaDriverPtr EXADriverPtr;
279 xf86CursorInfoPtr CursorInfoRec;
280 void (*PointerMoved)(int index, int x, int y);
281 ScreenBlockHandlerProcPtr BlockHandler;
282 CloseScreenProcPtr CloseScreen;
284 NVFBLayout CurrentLayout;
287 CARD32 curImage[256];
290 xf86Int10InfoPtr pInt10;
292 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
293 void (*DMAKickoffCallback)(NVPtr pNv);
294 XF86VideoAdaptorPtr overlayAdaptor;
295 XF86VideoAdaptorPtr blitAdaptor;
303 OptionInfoPtr Options;
305 unsigned char DDCBase;
318 volatile void * NotifierBlock;
319 struct drm_nouveau_notifierobj_alloc *Notifier0;
321 struct drm_nouveau_channel_alloc fifo;
331 Bool WaitVSyncPossible;
332 Bool BlendingPossible;
335 drmVersionPtr pLibDRMVersion;
336 drmVersionPtr pKernelDRMVersion;
339 CreateScreenResourcesProcPtr CreateScreenResources;
341 /* we know about 3 i2c buses */
342 I2CBusPtr pI2CBus[3];
347 CARD32 dcb_table[NV40_NUM_DCB_ENTRIES]; /* 10 is a good limit */
348 Bool crosswired_tmds;
349 Bool ramdac_occupied[2];
350 int crtc_associated[2];
362 typedef struct _NVCrtcPrivateRec {
366 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
368 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
370 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
372 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
373 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
375 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
376 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
378 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
379 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
381 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
382 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
384 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
385 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
387 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
388 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
390 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
391 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
393 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
394 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
396 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
397 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
399 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
400 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
402 #endif /* __NV_STRUCT_H__ */