git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xf86Cursor.h"
   9 #include "xf86int10.h"
  10 #include "exa.h"
  11 #ifdef XF86DRI
  12 #define _XF86DRI_SERVER_
  13 #include "xf86drm.h"
  14 #include "dri.h"
  15 #include <stdint.h>
  16 #include "nouveau_drm.h"
  17 #ifdef ENABLE_RANDR12
  18 #include "xf86Crtc.h"
  19 #endif
  20 #else
  21 #error "This driver requires a DRI-enabled X server"
  22 #endif
  23
  24 #include "nv50_type.h"
  25 #include "nv_pcicompat.h"
  26
  27 #define NV_ARCH_03  0x03
  28 #define NV_ARCH_04  0x04
  29 #define NV_ARCH_10  0x10
  30 #define NV_ARCH_20  0x20
  31 #define NV_ARCH_30  0x30
  32 #define NV_ARCH_40  0x40
  33 #define NV_ARCH_50  0x50
  34
  35 #define CHIPSET_NV03     0x0010
  36 #define CHIPSET_NV04     0x0020
  37 #define CHIPSET_NV10     0x0100
  38 #define CHIPSET_NV11     0x0110
  39 #define CHIPSET_NV15     0x0150
  40 #define CHIPSET_NV17     0x0170
  41 #define CHIPSET_NV18     0x0180
  42 #define CHIPSET_NFORCE   0x01A0
  43 #define CHIPSET_NFORCE2  0x01F0
  44 #define CHIPSET_NV20     0x0200
  45 #define CHIPSET_NV25     0x0250
  46 #define CHIPSET_NV28     0x0280
  47 #define CHIPSET_NV30     0x0300
  48 #define CHIPSET_NV31     0x0310
  49 #define CHIPSET_NV34     0x0320
  50 #define CHIPSET_NV35     0x0330
  51 #define CHIPSET_NV36     0x0340
  52 #define CHIPSET_NV40     0x0040
  53 #define CHIPSET_NV41     0x00C0
  54 #define CHIPSET_NV43     0x0140
  55 #define CHIPSET_NV44     0x0160
  56 #define CHIPSET_NV44A    0x0220
  57 #define CHIPSET_NV45     0x0210
  58 #define CHIPSET_NV50     0x0190
  59 #define CHIPSET_NV84     0x0400
  60 #define CHIPSET_MISC_BRIDGED  0x00F0
  61 #define CHIPSET_G70      0x0090
  62 #define CHIPSET_G71      0x0290
  63 #define CHIPSET_G72      0x01D0
  64 #define CHIPSET_G73      0x0390
  65 // integrated GeForces (6100, 6150)
  66 #define CHIPSET_C51      0x0240
  67 // variant of C51, seems based on a G70 design
  68 #define CHIPSET_C512     0x03D0
  69 #define CHIPSET_G73_BRIDGED 0x02E0
  70
  71
  72 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  73 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  74 #define SetBF(mask,value) ((value) << (0?mask))
  75 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  76 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  77 #define SetBit(n) (1<<(n))
  78 #define Set8Bits(value) ((value)&0xff)
  79
  80
  81 #define MAX_NUM_DCB_ENTRIES 16
  82
  83 typedef enum /* matches DCB types */
  84 {
  85     OUTPUT_NONE = 4,
  86     OUTPUT_ANALOG = 0,
  87     OUTPUT_DIGITAL = 2,
  88     OUTPUT_PANEL = 3,
  89     OUTPUT_TV = 1,
  90 } NVOutputType;
  91
  92 typedef struct {
  93     int bitsPerPixel;
  94     int depth;
  95     int displayWidth;
  96     rgb weight;
  97     DisplayModePtr mode;
  98 } NVFBLayout;
  99
 100 typedef struct _nv_crtc_reg
 101 {
 102         unsigned char MiscOutReg;     /* */
 103         CARD8 CRTC[90];
 104         CARD8 Sequencer[5];
 105         CARD8 Graphics[9];
 106         CARD8 Attribute[21];
 107         unsigned char DAC[768];       /* Internal Colorlookuptable */
 108         CARD32 cursorConfig;
 109         CARD32 crtcOwner;
 110         CARD32 gpio;
 111         CARD32 unk830;
 112         CARD32 unk834;
 113         CARD32 unk850;
 114         CARD32 unk81c;
 115         CARD32 head;
 116 } NVCrtcRegRec, *NVCrtcRegPtr;
 117
 118 typedef struct _nv_output_reg
 119 {
 120         CARD32 fp_control;
 121         CARD32 crtcSync;
 122         CARD32 dither;
 123         CARD32 general;
 124         CARD32 test_control;
 125         CARD32 bpp;
 126         CARD32 nv10_cursync;
 127         CARD32 output;
 128         CARD32 debug_0;
 129         CARD32 debug_1;
 130         CARD32 debug_2;
 131         CARD32 sel_clk;
 132         CARD32 unk_a20;
 133         CARD32 unk_a24;
 134         CARD32 unk_a34;
 135         CARD32 fp_horiz_regs[7];
 136         CARD32 fp_vert_regs[7];
 137         CARD32 fp_hvalid_start;
 138         CARD32 fp_hvalid_end;
 139         CARD32 fp_vvalid_start;
 140         CARD32 fp_vvalid_end;
 141         CARD8 TMDS[128];
 142 } NVOutputRegRec, *NVOutputRegPtr;
 143
 144 typedef struct _riva_hw_state
 145 {
 146     CARD32 bpp;
 147     CARD32 width;
 148     CARD32 height;
 149     CARD32 interlace;
 150     CARD32 repaint0;
 151     CARD32 repaint1;
 152     CARD32 screen;
 153     CARD32 scale;
 154     CARD32 dither;
 155     CARD32 extra;
 156     CARD32 fifo;
 157     CARD32 pixel;
 158     CARD32 horiz;
 159     CARD32 arbitration0;
 160     CARD32 arbitration1;
 161     CARD32 pll;
 162     CARD32 pllB;
 163     CARD32 vpll;
 164     CARD32 vpll2;
 165     CARD32 vpllB;
 166     CARD32 vpll2B;
 167     CARD32 pllsel;
 168         CARD32 reg580;
 169     CARD32 general;
 170     CARD32 crtcOwner;
 171     CARD32 head;
 172     CARD32 head2;
 173     CARD32 config;
 174     CARD32 cursorConfig;
 175     CARD32 cursor0;
 176     CARD32 cursor1;
 177     CARD32 cursor2;
 178     CARD32 timingH;
 179     CARD32 timingV;
 180     CARD32 displayV;
 181     CARD32 crtcSync;
 182
 183     NVCrtcRegRec crtc_reg[2];
 184     NVOutputRegRec dac_reg[2];
 185 } RIVA_HW_STATE, *NVRegPtr;
 186
 187 typedef struct _nv50_crtc_reg
 188 {
 189
 190 } NV50CrtcRegRec, *NV50CrtcRegPtr;
 191
 192 typedef struct _nv50_hw_state
 193 {
 194         NV50CrtcRegRec crtc_reg[2];
 195 } NV50_HW_STATE, *NV50RegPtr;
 196
 197 typedef struct {
 198         int type;
 199         uint64_t size;
 200         uint64_t offset;
 201         void *map;
 202 } NVAllocRec;
 203
 204 typedef enum {
 205         RAMDAC_0 = (1 << 0),
 206         RAMDAC_1 = (1 << 1)
 207 } ValidRamdac;
 208
 209 typedef struct _NVOutputPrivateRec {
 210         int ramdac;
 211         Bool ramdac_assigned;
 212         uint8_t valid_ramdac;
 213         I2CBusPtr                   pDDCBus;
 214         NVOutputType type;
 215         CARD32 fpSyncs;
 216         CARD32 fpWidth;
 217         CARD32 fpHeight;
 218         DisplayModePtr native_mode;
 219         Bool fpdither;
 220 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 221
 222 typedef struct _MiscStartupInfo {
 223         CARD8 crtc_0_reg_52;
 224         CARD32 ramdac_0_reg_580;
 225         CARD32 ramdac_0_pllsel;
 226         CARD32 reg_c040;
 227 } MiscStartupInfo;
 228
 229 typedef enum {
 230         OUTPUT_0_SLAVED = (1 << 0),
 231         OUTPUT_1_SLAVED = (1 << 1),
 232         OUTPUT_0_LVDS = (1 << 2),
 233         OUTPUT_1_LVDS = (1 << 3),
 234         OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
 235         OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
 236 } OutputInfo;
 237
 238 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 239
 240 typedef struct _NVRec *NVPtr;
 241 typedef struct _NVRec {
 242     RIVA_HW_STATE       SavedReg;
 243     RIVA_HW_STATE       ModeReg;
 244     RIVA_HW_STATE       *CurrentState;
 245         NV50_HW_STATE   NV50SavedReg;
 246         NV50_HW_STATE   NV50ModeReg;
 247     CARD32              Architecture;
 248     EntityInfoPtr       pEnt;
 249 #ifndef XSERVER_LIBPCIACCESS
 250         pciVideoPtr     PciInfo;
 251         PCITAG          PciTag;
 252 #else
 253         struct pci_device *PciInfo;
 254 #endif /* XSERVER_LIBPCIACCESS */
 255     int                 Chipset;
 256     int                 NVArch;
 257     Bool                Primary;
 258     CARD32              IOAddress;
 259     Bool cursorOn;
 260
 261     /* VRAM physical address */
 262     unsigned long       VRAMPhysical;
 263     /* Size of VRAM BAR */
 264     unsigned long       VRAMPhysicalSize;
 265     /* Accesible VRAM size (by the GPU) */
 266     unsigned long       VRAMSize;
 267     /* AGP physical address */
 268     unsigned long       AGPPhysical;
 269     /* Accessible AGP size */
 270     unsigned long       AGPSize;
 271     /* PCI buffer virtual address */
 272     unsigned long       SGPhysical;
 273
 274     uint32_t *          VBIOS;
 275     NVAllocRec *        FB;
 276     NVAllocRec *        Cursor;
 277     NVAllocRec *        CLUT;   /* NV50 only */
 278     NVAllocRec *        ScratchBuffer;
 279     NVAllocRec *        GARTScratch;
 280     Bool                NoAccel;
 281     Bool                HWCursor;
 282     Bool                FpScale;
 283     Bool                ShadowFB;
 284     unsigned char *     ShadowPtr;
 285     int                 ShadowPitch;
 286     CARD32              MinVClockFreqKHz;
 287     CARD32              MaxVClockFreqKHz;
 288     CARD32              CrystalFreqKHz;
 289     CARD32              RamAmountKBytes;
 290     int drm_fd;
 291
 292     volatile CARD32 *REGS;
 293     volatile CARD32 *PCRTC0;
 294     volatile CARD32 *PCRTC1;
 295
 296         volatile CARD32 *NV50_PCRTC;
 297
 298     volatile CARD32 *PRAMDAC0;
 299     volatile CARD32 *PRAMDAC1;
 300     volatile CARD32 *PFB;
 301     volatile CARD32 *PFIFO;
 302     volatile CARD32 *PGRAPH;
 303     volatile CARD32 *PEXTDEV;
 304     volatile CARD32 *PTIMER;
 305     volatile CARD32 *PVIDEO;
 306     volatile CARD32 *PMC;
 307     volatile CARD32 *PRAMIN;
 308     volatile CARD32 *FIFO;
 309     volatile CARD32 *CURSOR;
 310     volatile CARD8 *PCIO0;
 311     volatile CARD8 *PCIO1;
 312     volatile CARD8 *PVIO0;
 313     volatile CARD8 *PVIO1;
 314     volatile CARD8 *PDIO0;
 315     volatile CARD8 *PDIO1;
 316     volatile CARD8 *PROM;
 317
 318
 319     volatile CARD32 *RAMHT;
 320     CARD32 pramin_free;
 321
 322     unsigned int SaveGeneration;
 323     uint8_t cur_head;
 324     ExaDriverPtr        EXADriverPtr;
 325     xf86CursorInfoPtr   CursorInfoRec;
 326     void                (*PointerMoved)(int index, int x, int y);
 327     ScreenBlockHandlerProcPtr BlockHandler;
 328     CloseScreenProcPtr  CloseScreen;
 329     int                 Rotate;
 330     NVFBLayout          CurrentLayout;
 331     /* Cursor */
 332     CARD32              curFg, curBg;
 333     CARD32              curImage[256];
 334     /* I2C / DDC */
 335     int ddc2;
 336     xf86Int10InfoPtr    pInt10;
 337     I2CBusPtr           I2C;
 338   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 339     void                (*DMAKickoffCallback)(NVPtr pNv);
 340     XF86VideoAdaptorPtr overlayAdaptor;
 341     XF86VideoAdaptorPtr blitAdaptor;
 342     int                 videoKey;
 343     int                 FlatPanel;
 344     Bool                FPDither;
 345     int                 Mobile;
 346     Bool                Television;
 347         int         vtOWNER;
 348         Bool            crtc_active[2];
 349         Bool            ramdac_active[2];
 350     OptionInfoPtr       Options;
 351     Bool                alphaCursor;
 352     unsigned char       DDCBase;
 353     Bool                twoHeads;
 354     Bool                twoStagePLL;
 355     Bool                fpScaler;
 356     int                 fpWidth;
 357     int                 fpHeight;
 358     CARD32              fpSyncs;
 359     Bool                usePanelTweak;
 360     int                 PanelTweak;
 361     Bool                LVDS;
 362
 363     Bool                LockedUp;
 364
 365     volatile void *     NotifierBlock;
 366     struct drm_nouveau_notifierobj_alloc *Notifier0;
 367
 368     struct drm_nouveau_channel_alloc fifo;
 369     CARD32              dmaPut;
 370     CARD32              dmaCurrent;
 371     CARD32              dmaFree;
 372     CARD32              dmaMax;
 373     CARD32              *dmaBase;
 374
 375     CARD32              currentRop;
 376     int                 M2MFDirection;
 377
 378     Bool                WaitVSyncPossible;
 379     Bool                BlendingPossible;
 380     Bool                RandRRotation;
 381     DRIInfoPtr          pDRIInfo;
 382     drmVersionPtr       pLibDRMVersion;
 383     drmVersionPtr       pKernelDRMVersion;
 384
 385     Bool randr12_enable;
 386     CreateScreenResourcesProcPtr    CreateScreenResources;
 387
 388     I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
 389
 390     int analog_count;
 391     int digital_count;
 392     struct {
 393             int entries;
 394             int i2c_entries;
 395             int version;
 396             uint32_t connection[MAX_NUM_DCB_ENTRIES];
 397             uint32_t config[MAX_NUM_DCB_ENTRIES];
 398             unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
 399             unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
 400     } dcb_table;
 401
 402     uint32_t output_info;
 403     MiscStartupInfo misc_info;
 404
 405     DisplayModePtr fp_native_mode;
 406
 407     struct {
 408             ORNum dac;
 409             ORNum sor;
 410     } i2cMap[4];
 411     struct {
 412             Bool  present;
 413             ORNum or;
 414     } lvds;
 415 } NVRec;
 416
 417 typedef struct _NVCrtcPrivateRec {
 418         int crtc;
 419         int head;
 420         Bool paletteEnabled;
 421 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 422
 423 typedef struct _NV50CrtcPrivRec {
 424         int head;
 425         int pclk; /* Target pixel clock in kHz */
 426         Bool cursorVisible;
 427         Bool skipModeFixup;
 428         Bool dither;
 429 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
 430
 431 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 432
 433 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 434
 435 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
 436 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
 437
 438 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
 439 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 440
 441 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
 442 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
 443
 444 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
 445 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
 446
 447 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
 448 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
 449
 450 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
 451 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
 452
 453 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
 454 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
 455
 456 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
 457 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
 458
 459 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
 460 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
 461
 462 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
 463 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
 464
 465 #endif /* __NV_STRUCT_H__ */