git.oblomov.eu Git - nouveau/blob - src/nv_type.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.51 2005/04/16 23:57:26 mvojkovi Exp $ */
   2
   3 #ifndef __NV_STRUCT_H__
   4 #define __NV_STRUCT_H__
   5
   6 #include "colormapst.h"
   7 #include "vgaHW.h"
   8 #include "xf86Cursor.h"
   9 #include "xf86int10.h"
  10 #include "exa.h"
  11 #ifdef XF86DRI
  12 #define _XF86DRI_SERVER_
  13 #include "xf86drm.h"
  14 #include "dri.h"
  15 #include <stdint.h>
  16 #include "nouveau_drm.h"
  17 #include "xf86Crtc.h"
  18 #else
  19 #error "This driver requires a DRI-enabled X server"
  20 #endif
  21
  22 #include "nv50_type.h"
  23 #include "nv_pcicompat.h"
  24
  25 #define NV_ARCH_03  0x03
  26 #define NV_ARCH_04  0x04
  27 #define NV_ARCH_10  0x10
  28 #define NV_ARCH_20  0x20
  29 #define NV_ARCH_30  0x30
  30 #define NV_ARCH_40  0x40
  31 #define NV_ARCH_50  0x50
  32
  33 #define CHIPSET_NV03     0x0010
  34 #define CHIPSET_NV04     0x0020
  35 #define CHIPSET_NV10     0x0100
  36 #define CHIPSET_NV11     0x0110
  37 #define CHIPSET_NV15     0x0150
  38 #define CHIPSET_NV17     0x0170
  39 #define CHIPSET_NV18     0x0180
  40 #define CHIPSET_NFORCE   0x01A0
  41 #define CHIPSET_NFORCE2  0x01F0
  42 #define CHIPSET_NV20     0x0200
  43 #define CHIPSET_NV25     0x0250
  44 #define CHIPSET_NV28     0x0280
  45 #define CHIPSET_NV30     0x0300
  46 #define CHIPSET_NV31     0x0310
  47 #define CHIPSET_NV34     0x0320
  48 #define CHIPSET_NV35     0x0330
  49 #define CHIPSET_NV36     0x0340
  50 #define CHIPSET_NV40     0x0040
  51 #define CHIPSET_NV41     0x00C0
  52 #define CHIPSET_NV43     0x0140
  53 #define CHIPSET_NV44     0x0160
  54 #define CHIPSET_NV44A    0x0220
  55 #define CHIPSET_NV45     0x0210
  56 #define CHIPSET_NV50     0x0190
  57 #define CHIPSET_NV84     0x0400
  58 #define CHIPSET_MISC_BRIDGED  0x00F0
  59 #define CHIPSET_G70      0x0090
  60 #define CHIPSET_G71      0x0290
  61 #define CHIPSET_G72      0x01D0
  62 #define CHIPSET_G73      0x0390
  63 // integrated GeForces (6100, 6150)
  64 #define CHIPSET_C51      0x0240
  65 // variant of C51, seems based on a G70 design
  66 #define CHIPSET_C512     0x03D0
  67 #define CHIPSET_G73_BRIDGED 0x02E0
  68
  69
  70 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  71 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  72 #define SetBF(mask,value) ((value) << (0?mask))
  73 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  74 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  75 #define SetBit(n) (1<<(n))
  76 #define Set8Bits(value) ((value)&0xff)
  77
  78 #define MAX_NUM_DCB_ENTRIES 16
  79
  80 typedef enum /* matches DCB types */
  81 {
  82     OUTPUT_NONE = 4,
  83     OUTPUT_ANALOG = 0,
  84     OUTPUT_TMDS = 2,
  85     OUTPUT_LVDS = 3,
  86     OUTPUT_TV = 1,
  87 } NVOutputType;
  88
  89 typedef struct {
  90     int bitsPerPixel;
  91     int depth;
  92     int displayWidth;
  93     rgb weight;
  94     DisplayModePtr mode;
  95 } NVFBLayout;
  96
  97 typedef struct _nv_crtc_reg
  98 {
  99         unsigned char MiscOutReg;     /* */
 100         CARD8 CRTC[90];
 101         CARD8 CR58[0x10];
 102         CARD8 Sequencer[5];
 103         CARD8 Graphics[9];
 104         CARD8 Attribute[21];
 105         unsigned char DAC[768];       /* Internal Colorlookuptable */
 106         CARD32 cursorConfig;
 107         CARD32 crtcOwner;
 108         CARD32 gpio;
 109         CARD32 unk830;
 110         CARD32 unk834;
 111         CARD32 unk850;
 112         CARD32 unk81c;
 113         CARD32 head;
 114         uint32_t config;
 115
 116         /* These are former output regs, but are believed to be crtc related */
 117         CARD32 general;
 118         CARD32 debug_0;
 119         CARD32 debug_1;
 120         CARD32 debug_2;
 121         CARD32 unk_a20;
 122         CARD32 unk_a24;
 123         CARD32 unk_a34;
 124         CARD32 fp_horiz_regs[7];
 125         CARD32 fp_vert_regs[7];
 126         CARD32 fp_hvalid_start;
 127         CARD32 fp_hvalid_end;
 128         CARD32 fp_vvalid_start;
 129         CARD32 fp_vvalid_end;
 130         CARD32 bpp;
 131         CARD32 nv10_cursync;
 132         CARD32 fp_control;
 133         CARD32 crtcSync;
 134         CARD32 dither;
 135 } NVCrtcRegRec, *NVCrtcRegPtr;
 136
 137 typedef struct _nv_output_reg
 138 {
 139         CARD32 test_control;
 140         CARD32 unk_670;
 141         CARD32 unk_900;
 142
 143         CARD32 output;
 144         CARD8 TMDS[0xFF];
 145         CARD8 TMDS2[0xFF];
 146 } NVOutputRegRec, *NVOutputRegPtr;
 147
 148 typedef struct _riva_hw_state
 149 {
 150     CARD32 bpp;
 151     CARD32 width;
 152     CARD32 height;
 153     CARD32 interlace;
 154     CARD32 repaint0;
 155     CARD32 repaint1;
 156     CARD32 screen;
 157     CARD32 scale;
 158     CARD32 dither;
 159     CARD32 extra;
 160     CARD32 fifo;
 161     CARD32 pixel;
 162     CARD32 horiz;
 163     CARD32 arbitration0;
 164     CARD32 arbitration1;
 165     CARD32 pll;
 166     CARD32 pllB;
 167     CARD32 vpll;
 168     CARD32 vpll2;
 169     CARD32 vpllB;
 170     CARD32 vpll2B;
 171     CARD32 pllsel;
 172         CARD32 sel_clk;
 173         Bool crosswired;
 174         Bool db1_ratio[2];
 175         /* These vpll values are only for nv4x hardware */
 176         uint32_t vpll1_a;
 177         uint32_t vpll1_b;
 178         uint32_t vpll2_a;
 179         uint32_t vpll2_b;
 180         uint32_t reg580;
 181         uint32_t reg594;
 182     CARD32 general;
 183     CARD32 crtcOwner;
 184     CARD32 head;
 185     CARD32 head2;
 186     CARD32 config;
 187     CARD32 cursorConfig;
 188     CARD32 cursor0;
 189     CARD32 cursor1;
 190     CARD32 cursor2;
 191     CARD32 timingH;
 192     CARD32 timingV;
 193     CARD32 displayV;
 194     CARD32 crtcSync;
 195
 196     NVCrtcRegRec crtc_reg[2];
 197     NVOutputRegRec dac_reg[2];
 198 } RIVA_HW_STATE, *NVRegPtr;
 199
 200 typedef struct _nv50_crtc_reg
 201 {
 202
 203 } NV50CrtcRegRec, *NV50CrtcRegPtr;
 204
 205 typedef struct _nv50_hw_state
 206 {
 207         NV50CrtcRegRec crtc_reg[2];
 208 } NV50_HW_STATE, *NV50RegPtr;
 209
 210 typedef enum {
 211         OUTPUT_0 = (1 << 0),
 212         OUTPUT_1 = (1 << 1)
 213 } ValidRamdac;
 214
 215 typedef struct _NVOutputPrivateRec {
 216         uint8_t preferred_output;
 217         uint8_t bus;
 218         I2CBusPtr pDDCBus;
 219         NVOutputType type;
 220         int dcb_entry;
 221         CARD32 fpSyncs;
 222         CARD32 fpWidth;
 223         CARD32 fpHeight;
 224         DisplayModePtr native_mode;
 225         Bool fpdither;
 226         uint8_t scaling_mode;
 227 } NVOutputPrivateRec, *NVOutputPrivatePtr;
 228
 229 typedef struct _MiscStartupInfo {
 230         CARD8 crtc_0_reg_52;
 231         CARD32 ramdac_0_reg_580;
 232         CARD32 ramdac_0_pllsel;
 233         CARD32 reg_c040;
 234         CARD32 sel_clk;
 235 } MiscStartupInfo;
 236
 237 typedef enum {
 238         OUTPUT_0_SLAVED = (1 << 0),
 239         OUTPUT_1_SLAVED = (1 << 1),
 240         OUTPUT_0_LVDS = (1 << 2),
 241         OUTPUT_1_LVDS = (1 << 3),
 242         OUTPUT_0_CROSSWIRED_TMDS = (1 << 4),
 243         OUTPUT_1_CROSSWIRED_TMDS = (1 << 5)
 244 } OutputInfo;
 245
 246 struct dcb_entry {
 247         uint8_t type;
 248         uint8_t i2c_index;
 249         uint8_t heads;
 250         uint8_t bus;
 251         uint8_t location;
 252         uint8_t or;
 253         Bool duallink_possible;
 254         union {
 255                 struct {
 256                         Bool use_straps_for_mode;
 257                         Bool use_power_scripts;
 258                 } lvdsconf;
 259         };
 260 };
 261
 262 typedef struct {
 263         uint8_t *data;
 264         unsigned int length;
 265         Bool execute;
 266
 267         uint8_t major_version;
 268
 269         uint16_t init_script_tbls_ptr;
 270         uint16_t macro_index_tbl_ptr;
 271         uint16_t macro_tbl_ptr;
 272         uint16_t condition_tbl_ptr;
 273         uint16_t io_condition_tbl_ptr;
 274         uint16_t io_flag_condition_tbl_ptr;
 275         uint16_t init_function_tbl_ptr;
 276
 277         uint16_t ram_restrict_tbl_ptr;
 278
 279         struct {
 280                 DisplayModePtr native_mode;
 281                 uint16_t lvdsmanufacturerpointer;
 282                 uint16_t xlated_entry;
 283                 Bool dual_link;
 284                 Bool if_is_24bit;
 285                 Bool BITbit1;
 286         } fp;
 287
 288         struct {
 289                 uint16_t output0_script_ptr;
 290                 uint16_t output1_script_ptr;
 291         } tmds;
 292 } bios_t;
 293
 294 enum LVDS_script {
 295         /* Order *does* matter here */
 296         LVDS_INIT = 1,
 297         LVDS_RESET,
 298         LVDS_BACKLIGHT_ON,
 299         LVDS_BACKLIGHT_OFF,
 300         LVDS_PANEL_ON,
 301         LVDS_PANEL_OFF
 302 };
 303
 304 #define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
 305
 306 typedef struct _NVRec *NVPtr;
 307 typedef struct _NVRec {
 308     RIVA_HW_STATE       SavedReg;
 309     RIVA_HW_STATE       ModeReg;
 310     RIVA_HW_STATE       *CurrentState;
 311         NV50_HW_STATE   NV50SavedReg;
 312         NV50_HW_STATE   NV50ModeReg;
 313     CARD32              Architecture;
 314     EntityInfoPtr       pEnt;
 315 #ifndef XSERVER_LIBPCIACCESS
 316         pciVideoPtr     PciInfo;
 317         PCITAG          PciTag;
 318 #else
 319         struct pci_device *PciInfo;
 320 #endif /* XSERVER_LIBPCIACCESS */
 321     int                 Chipset;
 322     int                 NVArch;
 323     Bool                Primary;
 324     CARD32              IOAddress;
 325     Bool cursorOn;
 326
 327     /* VRAM physical address */
 328     unsigned long       VRAMPhysical;
 329     /* Size of VRAM BAR */
 330     unsigned long       VRAMPhysicalSize;
 331     /* Accesible VRAM size (by the GPU) */
 332     unsigned long       VRAMSize;
 333     /* Accessible AGP size */
 334     unsigned long       AGPSize;
 335
 336     /* Various pinned memory regions */
 337     struct nouveau_bo * FB;
 338     struct nouveau_bo * Cursor;
 339     struct nouveau_bo * CLUT;   /* NV50 only */
 340     struct nouveau_bo * GART;
 341
 342     bios_t              VBIOS;
 343     Bool                NoAccel;
 344     Bool                HWCursor;
 345     Bool                FpScale;
 346     Bool                ShadowFB;
 347     unsigned char *     ShadowPtr;
 348     int                 ShadowPitch;
 349     CARD32              MinVClockFreqKHz;
 350     CARD32              MaxVClockFreqKHz;
 351     CARD32              CrystalFreqKHz;
 352     CARD32              RamAmountKBytes;
 353
 354     volatile CARD32 *REGS;
 355     volatile CARD32 *PCRTC0;
 356     volatile CARD32 *PCRTC1;
 357
 358         volatile CARD32 *NV50_PCRTC;
 359
 360     volatile CARD32 *PRAMDAC0;
 361     volatile CARD32 *PRAMDAC1;
 362     volatile CARD32 *PFB;
 363     volatile CARD32 *PFIFO;
 364     volatile CARD32 *PGRAPH;
 365     volatile CARD32 *PEXTDEV;
 366     volatile CARD32 *PTIMER;
 367     volatile CARD32 *PVIDEO;
 368     volatile CARD32 *PMC;
 369     volatile CARD32 *PRAMIN;
 370     volatile CARD32 *CURSOR;
 371     volatile CARD8 *PCIO0;
 372     volatile CARD8 *PCIO1;
 373     volatile CARD8 *PVIO0;
 374     volatile CARD8 *PVIO1;
 375     volatile CARD8 *PDIO0;
 376     volatile CARD8 *PDIO1;
 377     volatile CARD8 *PROM;
 378
 379
 380     volatile CARD32 *RAMHT;
 381     CARD32 pramin_free;
 382
 383     unsigned int SaveGeneration;
 384     uint8_t cur_head;
 385     ExaDriverPtr        EXADriverPtr;
 386     xf86CursorInfoPtr   CursorInfoRec;
 387     void                (*PointerMoved)(int index, int x, int y);
 388     ScreenBlockHandlerProcPtr BlockHandler;
 389     CloseScreenProcPtr  CloseScreen;
 390     int                 Rotate;
 391     NVFBLayout          CurrentLayout;
 392     /* Cursor */
 393     CARD32              curFg, curBg;
 394     CARD32              curImage[256];
 395     /* I2C / DDC */
 396     int ddc2;
 397     xf86Int10InfoPtr    pInt10;
 398     I2CBusPtr           I2C;
 399   void          (*VideoTimerCallback)(ScrnInfoPtr, Time);
 400     XF86VideoAdaptorPtr overlayAdaptor;
 401     XF86VideoAdaptorPtr blitAdaptor;
 402     int                 videoKey;
 403     int                 FlatPanel;
 404     Bool                FPDither;
 405     int                 Mobile;
 406     Bool                Television;
 407         int         vtOWNER;
 408         Bool            crtc_active[2];
 409         Bool            ramdac_active[2];
 410     OptionInfoPtr       Options;
 411     Bool                alphaCursor;
 412     unsigned char       DDCBase;
 413     Bool                twoHeads;
 414     Bool                twoStagePLL;
 415     Bool                fpScaler;
 416     int                 fpWidth;
 417     int                 fpHeight;
 418     CARD32              fpSyncs;
 419     Bool                usePanelTweak;
 420     int                 PanelTweak;
 421     Bool                LVDS;
 422
 423     Bool                LockedUp;
 424
 425     CARD32              currentRop;
 426
 427     Bool                WaitVSyncPossible;
 428     Bool                BlendingPossible;
 429     Bool                RandRRotation;
 430     DRIInfoPtr          pDRIInfo;
 431     drmVersionPtr       pLibDRMVersion;
 432     drmVersionPtr       pKernelDRMVersion;
 433
 434     Bool randr12_enable;
 435     CreateScreenResourcesProcPtr    CreateScreenResources;
 436
 437     I2CBusPtr           pI2CBus[MAX_NUM_DCB_ENTRIES];
 438
 439         int vga_count;
 440         int dvi_d_count;
 441         int dvi_a_count;
 442         int lvds_count;
 443
 444         struct {
 445                 int entries;
 446                 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
 447                 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
 448                 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
 449         } dcb_table;
 450
 451         uint32_t output_info;
 452         MiscStartupInfo misc_info;
 453
 454         struct {
 455                 ORNum dac;
 456                 ORNum sor;
 457         } i2cMap[4];
 458         struct {
 459                 Bool  present;
 460                 ORNum or;
 461         } lvds;
 462
 463         /* DRM interface */
 464         struct nouveau_device *dev;
 465
 466         /* GPU context */
 467         struct nouveau_channel *chan;
 468         struct nouveau_notifier *notify0;
 469         struct nouveau_grobj *NvNull;
 470         struct nouveau_grobj *NvContextSurfaces;
 471         struct nouveau_grobj *NvContextBeta1;
 472         struct nouveau_grobj *NvContextBeta4;
 473         struct nouveau_grobj *NvImagePattern;
 474         struct nouveau_grobj *NvRop;
 475         struct nouveau_grobj *NvRectangle;
 476         struct nouveau_grobj *NvImageBlit;
 477         struct nouveau_grobj *NvScaledImage;
 478         struct nouveau_grobj *NvClipRectangle;
 479         struct nouveau_grobj *NvMemFormat;
 480         struct nouveau_grobj *NvImageFromCpu;
 481         struct nouveau_grobj *Nv2D;
 482         struct nouveau_grobj *Nv3D;
 483
 484 } NVRec;
 485
 486 typedef struct _NVCrtcPrivateRec {
 487         int crtc;
 488         int head;
 489         Bool paletteEnabled;
 490         Bool deactivate;
 491 } NVCrtcPrivateRec, *NVCrtcPrivatePtr;
 492
 493 typedef struct _NV50CrtcPrivRec {
 494         int head;
 495         int pclk; /* Target pixel clock in kHz */
 496         Bool cursorVisible;
 497         Bool skipModeFixup;
 498         Bool dither;
 499 } NV50CrtcPrivRec, *NV50CrtcPrivPtr;
 500
 501 #define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
 502
 503 #define NVPTR(p) ((NVPtr)((p)->driverPrivate))
 504
 505 #define nvReadRAMDAC0(pNv, reg) nvReadRAMDAC(pNv, 0, reg)
 506 #define nvWriteRAMDAC0(pNv, reg, val) nvWriteRAMDAC(pNv, 0, reg, val)
 507
 508 #define nvReadCurRAMDAC(pNv, reg) nvReadRAMDAC(pNv, pNv->cur_head, reg)
 509 #define nvWriteCurRAMDAC(pNv, reg, val) nvWriteRAMDAC(pNv, pNv->cur_head, reg, val)
 510
 511 #define nvReadCRTC0(pNv, reg) nvReadCRTC(pNv, 0, reg)
 512 #define nvWriteCRTC0(pNv, reg, val) nvWriteCRTC(pNv, 0, reg, val)
 513
 514 #define nvReadCurCRTC(pNv, reg) nvReadCRTC(pNv, pNv->cur_head, reg)
 515 #define nvWriteCurCRTC(pNv, reg, val) nvWriteCRTC(pNv, pNv->cur_head, reg, val)
 516
 517 #define nvReadFB(pNv, fb_reg) MMIO_IN32(pNv->PFB, fb_reg)
 518 #define nvWriteFB(pNv, fb_reg, val) MMIO_OUT32(pNv->PFB, fb_reg, val)
 519
 520 #define nvReadGRAPH(pNv, reg) MMIO_IN32(pNv->PGRAPH, reg)
 521 #define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->PGRAPH, reg, val)
 522
 523 #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg)
 524 #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val)
 525
 526 #define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg)
 527 #define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val)
 528
 529 #define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg)
 530 #define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val)
 531
 532 #define nvReadVIDEO(pNv, reg) MMIO_IN32(pNv->PVIDEO, reg)
 533 #define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->PVIDEO, reg, val)
 534
 535 #endif /* __NV_STRUCT_H__ */